drivers/clk/clk_stm32f7.c

   1 /*
   2  * (C) Copyright 2017
   3  * Vikas Manocha, <vikas.manocha@st.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/rcc.h>
  12 #include <asm/arch/stm32.h>
  13 #include <asm/arch/stm32_periph.h>
  14
  15 #include <dt-bindings/mfd/stm32f7-rcc.h>
  16
  17 #define RCC_CR_HSION                    BIT(0)
  18 #define RCC_CR_HSEON                    BIT(16)
  19 #define RCC_CR_HSERDY                   BIT(17)
  20 #define RCC_CR_HSEBYP                   BIT(18)
  21 #define RCC_CR_CSSON                    BIT(19)
  22 #define RCC_CR_PLLON                    BIT(24)
  23 #define RCC_CR_PLLRDY                   BIT(25)
  24
  25 #define RCC_PLLCFGR_PLLM_MASK           GENMASK(5, 0)
  26 #define RCC_PLLCFGR_PLLN_MASK           GENMASK(14, 6)
  27 #define RCC_PLLCFGR_PLLP_MASK           GENMASK(17, 16)
  28 #define RCC_PLLCFGR_PLLQ_MASK           GENMASK(27, 24)
  29 #define RCC_PLLCFGR_PLLSRC              BIT(22)
  30 #define RCC_PLLCFGR_PLLM_SHIFT          0
  31 #define RCC_PLLCFGR_PLLN_SHIFT          6
  32 #define RCC_PLLCFGR_PLLP_SHIFT          16
  33 #define RCC_PLLCFGR_PLLQ_SHIFT          24
  34
  35 #define RCC_CFGR_AHB_PSC_MASK           GENMASK(7, 4)
  36 #define RCC_CFGR_APB1_PSC_MASK          GENMASK(12, 10)
  37 #define RCC_CFGR_APB2_PSC_MASK          GENMASK(15, 13)
  38 #define RCC_CFGR_SW0                    BIT(0)
  39 #define RCC_CFGR_SW1                    BIT(1)
  40 #define RCC_CFGR_SW_MASK                GENMASK(1, 0)
  41 #define RCC_CFGR_SW_HSI                 0
  42 #define RCC_CFGR_SW_HSE                 RCC_CFGR_SW0
  43 #define RCC_CFGR_SW_PLL                 RCC_CFGR_SW1
  44 #define RCC_CFGR_SWS0                   BIT(2)
  45 #define RCC_CFGR_SWS1                   BIT(3)
  46 #define RCC_CFGR_SWS_MASK               GENMASK(3, 2)
  47 #define RCC_CFGR_SWS_HSI                0
  48 #define RCC_CFGR_SWS_HSE                RCC_CFGR_SWS0
  49 #define RCC_CFGR_SWS_PLL                RCC_CFGR_SWS1
  50 #define RCC_CFGR_HPRE_SHIFT             4
  51 #define RCC_CFGR_PPRE1_SHIFT            10
  52 #define RCC_CFGR_PPRE2_SHIFT            13
  53
  54 /*
  55  * Offsets of some PWR registers
  56  */
  57 #define PWR_CR1_ODEN                    BIT(16)
  58 #define PWR_CR1_ODSWEN                  BIT(17)
  59 #define PWR_CSR1_ODRDY                  BIT(16)
  60 #define PWR_CSR1_ODSWRDY                BIT(17)
  61
  62 struct pll_psc {
  63         u8      pll_m;
  64         u16     pll_n;
  65         u8      pll_p;
  66         u8      pll_q;
  67         u8      ahb_psc;
  68         u8      apb1_psc;
  69         u8      apb2_psc;
  70 };
  71
  72 #define AHB_PSC_1                       0
  73 #define AHB_PSC_2                       0x8
  74 #define AHB_PSC_4                       0x9
  75 #define AHB_PSC_8                       0xA
  76 #define AHB_PSC_16                      0xB
  77 #define AHB_PSC_64                      0xC
  78 #define AHB_PSC_128                     0xD
  79 #define AHB_PSC_256                     0xE
  80 #define AHB_PSC_512                     0xF
  81
  82 #define APB_PSC_1                       0
  83 #define APB_PSC_2                       0x4
  84 #define APB_PSC_4                       0x5
  85 #define APB_PSC_8                       0x6
  86 #define APB_PSC_16                      0x7
  87
  88 struct stm32_clk {
  89         struct stm32_rcc_regs *base;
  90 };
  91
  92 #if !defined(CONFIG_STM32_HSE_HZ)
  93 #error "CONFIG_STM32_HSE_HZ not defined!"
  94 #else
  95 #if (CONFIG_STM32_HSE_HZ == 25000000)
  96 #if (CONFIG_SYS_CLK_FREQ == 200000000)
  97 /* 200 MHz */
  98 struct pll_psc sys_pll_psc = {
  99         .pll_m = 25,
 100         .pll_n = 400,
 101         .pll_p = 2,
 102         .pll_q = 8,
 103         .ahb_psc = AHB_PSC_1,
 104         .apb1_psc = APB_PSC_4,
 105         .apb2_psc = APB_PSC_2
 106 };
 107 #endif
 108 #else
 109 #error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
 110 #endif
 111 #endif
 112
 113 static int configure_clocks(struct udevice *dev)
 114 {
 115         struct stm32_clk *priv = dev_get_priv(dev);
 116         struct stm32_rcc_regs *regs = priv->base;
 117
 118         /* Reset RCC configuration */
 119         setbits_le32(&regs->cr, RCC_CR_HSION);
 120         writel(0, &regs->cfgr); /* Reset CFGR */
 121         clrbits_le32(&regs->cr, (RCC_CR_HSEON | RCC_CR_CSSON
 122                 | RCC_CR_PLLON));
 123         writel(0x24003010, &regs->pllcfgr); /* Reset value from RM */
 124         clrbits_le32(&regs->cr, RCC_CR_HSEBYP);
 125         writel(0, &regs->cir); /* Disable all interrupts */
 126
 127         /* Configure for HSE+PLL operation */
 128         setbits_le32(&regs->cr, RCC_CR_HSEON);
 129         while (!(readl(&regs->cr) & RCC_CR_HSERDY))
 130                 ;
 131
 132         setbits_le32(&regs->cfgr, ((
 133                 sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
 134                 | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
 135                 | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
 136
 137         /* Configure the main PLL */
 138         uint32_t pllcfgr = 0;
 139         pllcfgr = RCC_PLLCFGR_PLLSRC; /* pll source HSE */
 140         pllcfgr |= sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT;
 141         pllcfgr |= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT;
 142         pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT;
 143         pllcfgr |= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT;
 144         writel(pllcfgr, &regs->pllcfgr);
 145
 146         /* Enable the main PLL */
 147         setbits_le32(&regs->cr, RCC_CR_PLLON);
 148         while (!(readl(&regs->cr) & RCC_CR_PLLRDY))
 149                 ;
 150
 151         /* Enable high performance mode, System frequency up to 200 MHz */
 152         setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN);
 153         setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN);
 154         /* Infinite wait! */
 155         while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY))
 156                 ;
 157         /* Enable the Over-drive switch */
 158         setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODSWEN);
 159         /* Infinite wait! */
 160         while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODSWRDY))
 161                 ;
 162
 163         stm32_flash_latency_cfg(5);
 164         clrbits_le32(&regs->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
 165         setbits_le32(&regs->cfgr, RCC_CFGR_SW_PLL);
 166
 167         while ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) !=
 168                         RCC_CFGR_SWS_PLL)
 169                 ;
 170
 171         return 0;
 172 }
 173
 174 unsigned long clock_get(enum clock clck)
 175 {
 176         u32 sysclk = 0;
 177         u32 shift = 0;
 178         /* Prescaler table lookups for clock computation */
 179         u8 ahb_psc_table[16] = {
 180                 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
 181         };
 182         u8 apb_psc_table[8] = {
 183                 0, 0, 0, 0, 1, 2, 3, 4
 184         };
 185
 186         if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
 187                         RCC_CFGR_SWS_PLL) {
 188                 u16 pllm, plln, pllp;
 189                 pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
 190                 plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
 191                         >> RCC_PLLCFGR_PLLN_SHIFT);
 192                 pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
 193                         >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
 194                 sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
 195         }
 196
 197         switch (clck) {
 198         case CLOCK_AHB:
 199                 shift = ahb_psc_table[(
 200                         (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
 201                         >> RCC_CFGR_HPRE_SHIFT)];
 202                 return sysclk >>= shift;
 203                 break;
 204         case CLOCK_APB1:
 205                 shift = apb_psc_table[(
 206                         (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
 207                         >> RCC_CFGR_PPRE1_SHIFT)];
 208                 return sysclk >>= shift;
 209                 break;
 210         case CLOCK_APB2:
 211                 shift = apb_psc_table[(
 212                         (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
 213                         >> RCC_CFGR_PPRE2_SHIFT)];
 214                 return sysclk >>= shift;
 215                 break;
 216         default:
 217                 return 0;
 218                 break;
 219         }
 220 }
 221
 222 static unsigned long stm32_clk_get_rate(struct clk *clk)
 223 {
 224         struct stm32_clk *priv = dev_get_priv(clk->dev);
 225         struct stm32_rcc_regs *regs = priv->base;
 226         u32 sysclk = 0;
 227         u32 shift = 0;
 228         /* Prescaler table lookups for clock computation */
 229         u8 ahb_psc_table[16] = {
 230                 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
 231         };
 232         u8 apb_psc_table[8] = {
 233                 0, 0, 0, 0, 1, 2, 3, 4
 234         };
 235
 236         if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) ==
 237                         RCC_CFGR_SWS_PLL) {
 238                 u16 pllm, plln, pllp;
 239                 pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
 240                 plln = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
 241                         >> RCC_PLLCFGR_PLLN_SHIFT);
 242                 pllp = ((((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
 243                         >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
 244                 sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
 245         } else {
 246                 return -EINVAL;
 247         }
 248
 249         switch (clk->id) {
 250         /*
 251          * AHB CLOCK: 3 x 32 bits consecutive registers are used :
 252          * AHB1, AHB2 and AHB3
 253          */
 254         case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
 255                 shift = ahb_psc_table[(
 256                         (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK)
 257                         >> RCC_CFGR_HPRE_SHIFT)];
 258                 return sysclk >>= shift;
 259                 break;
 260         /* APB1 CLOCK */
 261         case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
 262                 shift = apb_psc_table[(
 263                         (readl(&regs->cfgr) & RCC_CFGR_APB1_PSC_MASK)
 264                         >> RCC_CFGR_PPRE1_SHIFT)];
 265                 return sysclk >>= shift;
 266                 break;
 267         /* APB2 CLOCK */
 268         case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC):
 269                 shift = apb_psc_table[(
 270                         (readl(&regs->cfgr) & RCC_CFGR_APB2_PSC_MASK)
 271                         >> RCC_CFGR_PPRE2_SHIFT)];
 272                 return sysclk >>= shift;
 273                 break;
 274         default:
 275                 error("clock index %ld out of range\n", clk->id);
 276                 return -EINVAL;
 277                 break;
 278         }
 279 }
 280
 281 static int stm32_clk_enable(struct clk *clk)
 282 {
 283         struct stm32_clk *priv = dev_get_priv(clk->dev);
 284         struct stm32_rcc_regs *regs = priv->base;
 285         u32 offset = clk->id / 32;
 286         u32 bit_index = clk->id % 32;
 287
 288         debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
 289               __func__, clk->id, offset, bit_index);
 290         setbits_le32(&regs->ahb1enr + offset, BIT(bit_index));
 291
 292         return 0;
 293 }
 294
 295 void clock_setup(int peripheral)
 296 {
 297         switch (peripheral) {
 298         case SYSCFG_CLOCK_CFG:
 299                 setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN);
 300                 break;
 301         case TIMER2_CLOCK_CFG:
 302                 setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
 303                 break;
 304         case STMMAC_CLOCK_CFG:
 305                 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_EN);
 306                 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN);
 307                 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN);
 308                 break;
 309         default:
 310                 break;
 311         }
 312 }
 313
 314 static int stm32_clk_probe(struct udevice *dev)
 315 {
 316         debug("%s: stm32_clk_probe\n", __func__);
 317
 318         struct stm32_clk *priv = dev_get_priv(dev);
 319         fdt_addr_t addr;
 320
 321         addr = devfdt_get_addr(dev);
 322         if (addr == FDT_ADDR_T_NONE)
 323                 return -EINVAL;
 324
 325         priv->base = (struct stm32_rcc_regs *)addr;
 326
 327         configure_clocks(dev);
 328
 329         return 0;
 330 }
 331
 332 static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
 333 {
 334         debug("%s(clk=%p)\n", __func__, clk);
 335
 336         if (args->args_count != 2) {
 337                 debug("Invaild args_count: %d\n", args->args_count);
 338                 return -EINVAL;
 339         }
 340
 341         if (args->args_count)
 342                 clk->id = args->args[1];
 343         else
 344                 clk->id = 0;
 345
 346         return 0;
 347 }
 348
 349 static struct clk_ops stm32_clk_ops = {
 350         .of_xlate       = stm32_clk_of_xlate,
 351         .enable         = stm32_clk_enable,
 352         .get_rate       = stm32_clk_get_rate,
 353 };
 354
 355 static const struct udevice_id stm32_clk_ids[] = {
 356         { .compatible = "st,stm32f42xx-rcc"},
 357         {}
 358 };
 359
 360 U_BOOT_DRIVER(stm32f7_clk) = {
 361         .name           = "stm32f7_clk",
 362         .id             = UCLASS_CLK,
 363         .of_match       = stm32_clk_ids,
 364         .ops            = &stm32_clk_ops,
 365         .probe          = stm32_clk_probe,
 366         .flags          = DM_FLAG_PRE_RELOC,
 367 };