drivers/clk/renesas/renesas-cpg-mssr.h

   1 /*
   2  * Renesas RCar Gen3 CPG MSSR driver
   3  *
   4  * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
   5  *
   6  * Based on the following driver from Linux kernel:
   7  * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
   8  *
   9  * Copyright (C) 2016 Glider bvba
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #ifndef __DRIVERS_CLK_RENESAS_CPG_MSSR__
  15 #define __DRIVERS_CLK_RENESAS_CPG_MSSR__
  16
  17 struct cpg_mssr_info {
  18         const struct cpg_core_clk       *core_clk;
  19         unsigned int                    core_clk_size;
  20         const struct mssr_mod_clk       *mod_clk;
  21         unsigned int                    mod_clk_size;
  22         const struct mstp_stop_table    *mstp_table;
  23         unsigned int                    mstp_table_size;
  24         const char                      *reset_node;
  25         const char                      *extalr_node;
  26         const char                      *extal_usb_node;
  27         unsigned int                    mod_clk_base;
  28         unsigned int                    clk_extal_id;
  29         unsigned int                    clk_extalr_id;
  30         unsigned int                    clk_extal_usb_id;
  31         unsigned int                    pll0_div;
  32         const void                      *(*get_pll_config)(const u32 cpg_mode);
  33 };
  34
  35 /*
  36  * Definitions of CPG Core Clocks
  37  *
  38  * These include:
  39  *   - Clock outputs exported to DT
  40  *   - External input clocks
  41  *   - Internal CPG clocks
  42  */
  43 struct cpg_core_clk {
  44         /* Common */
  45         const char *name;
  46         unsigned int id;
  47         unsigned int type;
  48         /* Depending on type */
  49         unsigned int parent;    /* Core Clocks only */
  50         unsigned int div;
  51         unsigned int mult;
  52         unsigned int offset;
  53 };
  54
  55 enum clk_types {
  56         /* Generic */
  57         CLK_TYPE_IN,            /* External Clock Input */
  58         CLK_TYPE_FF,            /* Fixed Factor Clock */
  59         CLK_TYPE_DIV6P1,        /* DIV6 Clock with 1 parent clock */
  60         CLK_TYPE_DIV6_RO,       /* DIV6 Clock read only with extra divisor */
  61
  62         /* Custom definitions start here */
  63         CLK_TYPE_CUSTOM,
  64 };
  65
  66 #define DEF_TYPE(_name, _id, _type...)  \
  67         { .name = _name, .id = _id, .type = _type }
  68 #define DEF_BASE(_name, _id, _type, _parent...) \
  69         DEF_TYPE(_name, _id, _type, .parent = _parent)
  70
  71 #define DEF_INPUT(_name, _id) \
  72         DEF_TYPE(_name, _id, CLK_TYPE_IN)
  73 #define DEF_FIXED(_name, _id, _parent, _div, _mult)     \
  74         DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
  75 #define DEF_DIV6P1(_name, _id, _parent, _offset)        \
  76         DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
  77 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
  78         DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
  79
  80 /*
  81  * Definitions of Module Clocks
  82  */
  83 struct mssr_mod_clk {
  84         const char *name;
  85         unsigned int id;
  86         unsigned int parent;    /* Add MOD_CLK_BASE for Module Clocks */
  87 };
  88
  89 /* Convert from sparse base-100 to packed index space */
  90 #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
  91
  92 #define MOD_CLK_ID(x)   (MOD_CLK_BASE + MOD_CLK_PACK(x))
  93
  94 #define DEF_MOD(_name, _mod, _parent...)        \
  95         { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
  96
  97 struct mstp_stop_table {
  98         u32     sdis;
  99         u32     sen;
 100         u32     rdis;
 101         u32     ren;
 102 };
 103
 104 #define TSTR0           0x04
 105 #define TSTR0_STR0      BIT(0)
 106
 107 bool renesas_clk_is_mod(struct clk *clk);
 108 int renesas_clk_get_mod(struct clk *clk, struct cpg_mssr_info *info,
 109                         const struct mssr_mod_clk **mssr);
 110 int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info,
 111                          const struct cpg_core_clk **core);
 112 int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
 113                            struct clk *parent);
 114 int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable);
 115 int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info);
 116
 117 #endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */