drivers/clk/renesas/renesas-cpg-mssr.h

   1 /*
   2  * Renesas RCar Gen3 CPG MSSR driver
   3  *
   4  * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
   5  *
   6  * Based on the following driver from Linux kernel:
   7  * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
   8  *
   9  * Copyright (C) 2016 Glider bvba
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #ifndef __DRIVERS_CLK_RENESAS_CPG_MSSR__
  15 #define __DRIVERS_CLK_RENESAS_CPG_MSSR__
  16
  17 struct cpg_mssr_info {
  18         const struct cpg_core_clk       *core_clk;
  19         unsigned int                    core_clk_size;
  20         const struct mssr_mod_clk       *mod_clk;
  21         unsigned int                    mod_clk_size;
  22         const struct mstp_stop_table    *mstp_table;
  23         unsigned int                    mstp_table_size;
  24         const char                      *reset_node;
  25         const char                      *extalr_node;
  26         unsigned int                    mod_clk_base;
  27         unsigned int                    clk_extal_id;
  28         unsigned int                    clk_extalr_id;
  29         const void                      *(*get_pll_config)(const u32 cpg_mode);
  30 };
  31
  32 struct gen3_clk_priv {
  33         void __iomem            *base;
  34         struct cpg_mssr_info    *info;
  35         struct clk              clk_extal;
  36         struct clk              clk_extalr;
  37         const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
  38 };
  39
  40 /*
  41  * Definitions of CPG Core Clocks
  42  *
  43  * These include:
  44  *   - Clock outputs exported to DT
  45  *   - External input clocks
  46  *   - Internal CPG clocks
  47  */
  48 struct cpg_core_clk {
  49         /* Common */
  50         const char *name;
  51         unsigned int id;
  52         unsigned int type;
  53         /* Depending on type */
  54         unsigned int parent;    /* Core Clocks only */
  55         unsigned int div;
  56         unsigned int mult;
  57         unsigned int offset;
  58 };
  59
  60 enum clk_types {
  61         /* Generic */
  62         CLK_TYPE_IN,            /* External Clock Input */
  63         CLK_TYPE_FF,            /* Fixed Factor Clock */
  64
  65         /* Custom definitions start here */
  66         CLK_TYPE_CUSTOM,
  67 };
  68
  69 #define DEF_TYPE(_name, _id, _type...)  \
  70         { .name = _name, .id = _id, .type = _type }
  71 #define DEF_BASE(_name, _id, _type, _parent...) \
  72         DEF_TYPE(_name, _id, _type, .parent = _parent)
  73
  74 #define DEF_INPUT(_name, _id) \
  75         DEF_TYPE(_name, _id, CLK_TYPE_IN)
  76 #define DEF_FIXED(_name, _id, _parent, _div, _mult)     \
  77         DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
  78 #define DEF_GEN3_SD(_name, _id, _parent, _offset)       \
  79         DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
  80 #define DEF_GEN3_RPC(_name, _id, _parent, _offset)      \
  81         DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
  82 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
  83                     _div_clean) \
  84         DEF_BASE(_name, _id, CLK_TYPE_FF,                       \
  85                  (_parent_clean), .div = (_div_clean), 1)
  86
  87 /*
  88  * Definitions of Module Clocks
  89  */
  90 struct mssr_mod_clk {
  91         const char *name;
  92         unsigned int id;
  93         unsigned int parent;    /* Add MOD_CLK_BASE for Module Clocks */
  94 };
  95
  96 /* Convert from sparse base-100 to packed index space */
  97 #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
  98
  99 #define MOD_CLK_ID(x)   (MOD_CLK_BASE + MOD_CLK_PACK(x))
 100
 101 #define DEF_MOD(_name, _mod, _parent...)        \
 102         { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
 103
 104 enum rcar_gen3_clk_types {
 105         CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
 106         CLK_TYPE_GEN3_PLL0,
 107         CLK_TYPE_GEN3_PLL1,
 108         CLK_TYPE_GEN3_PLL2,
 109         CLK_TYPE_GEN3_PLL3,
 110         CLK_TYPE_GEN3_PLL4,
 111         CLK_TYPE_GEN3_SD,
 112         CLK_TYPE_GEN3_RPC,
 113         CLK_TYPE_GEN3_R,
 114         CLK_TYPE_GEN3_PE,
 115         CLK_TYPE_GEN3_Z2,
 116 };
 117
 118 struct rcar_gen3_cpg_pll_config {
 119         unsigned int extal_div;
 120         unsigned int pll1_mult;
 121         unsigned int pll3_mult;
 122 };
 123
 124 struct mstp_stop_table {
 125         u32     dis;
 126         u32     en;
 127 };
 128
 129 #define TSTR0           0x04
 130 #define TSTR0_STR0      BIT(0)
 131
 132 int gen3_clk_probe(struct udevice *dev);
 133 int gen3_clk_remove(struct udevice *dev);
 134
 135 extern const struct clk_ops gen3_clk_ops;
 136
 137 #endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */