]> git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/clk/rockchip/clk_rk3288.c
projects / people / ms / u-boot.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
rockchip: clk: guard set_parent implementations against OF_PLATDATA
[people/ms/u-boot.git] / drivers / clk / rockchip / clk_rk3288.c
1 /*
2 * (C) Copyright 2015 Google, Inc
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7 #include <common.h>
8 #include <bitfield.h>
9 #include <clk-uclass.h>
10 #include <dm.h>
11 #include <dt-structs.h>
12 #include <errno.h>
13 #include <mapmem.h>
14 #include <syscon.h>
15 #include <asm/io.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/cru_rk3288.h>
18 #include <asm/arch/grf_rk3288.h>
19 #include <asm/arch/hardware.h>
20 #include <dt-bindings/clock/rk3288-cru.h>
21 #include <dm/device-internal.h>
22 #include <dm/lists.h>
23 #include <dm/uclass-internal.h>
24 #include <linux/log2.h>
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 struct rk3288_clk_plat {
29 #if CONFIG_IS_ENABLED(OF_PLATDATA)
30 struct dtd_rockchip_rk3288_cru dtd;
31 #endif
32 };
33
34 struct pll_div {
35 u32 nr;
36 u32 nf;
37 u32 no;
38 };
39
40 enum {
41 VCO_MAX_HZ = 2200U * 1000000,
42 VCO_MIN_HZ = 440 * 1000000,
43 OUTPUT_MAX_HZ = 2200U * 1000000,
44 OUTPUT_MIN_HZ = 27500000,
45 FREF_MAX_HZ = 2200U * 1000000,
46 FREF_MIN_HZ = 269 * 1000,
47 };
48
49 enum {
50 /* PLL CON0 */
51 PLL_OD_MASK = 0x0f,
52
53 /* PLL CON1 */
54 PLL_NF_MASK = 0x1fff,
55
56 /* PLL CON2 */
57 PLL_BWADJ_MASK = 0x0fff,
58
59 /* PLL CON3 */
60 PLL_RESET_SHIFT = 5,
61
62 /* CLKSEL0 */
63 CORE_SEL_PLL_SHIFT = 15,
64 CORE_SEL_PLL_MASK = 1 << CORE_SEL_PLL_SHIFT,
65 A17_DIV_SHIFT = 8,
66 A17_DIV_MASK = 0x1f << A17_DIV_SHIFT,
67 MP_DIV_SHIFT = 4,
68 MP_DIV_MASK = 0xf << MP_DIV_SHIFT,
69 M0_DIV_SHIFT = 0,
70 M0_DIV_MASK = 0xf << M0_DIV_SHIFT,
71
72 /* CLKSEL1: pd bus clk pll sel: codec or general */
73 PD_BUS_SEL_PLL_MASK = 15,
74 PD_BUS_SEL_CPLL = 0,
75 PD_BUS_SEL_GPLL,
76
77 /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
78 PD_BUS_PCLK_DIV_SHIFT = 12,
79 PD_BUS_PCLK_DIV_MASK = 7 << PD_BUS_PCLK_DIV_SHIFT,
80
81 /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
82 PD_BUS_HCLK_DIV_SHIFT = 8,
83 PD_BUS_HCLK_DIV_MASK = 3 << PD_BUS_HCLK_DIV_SHIFT,
84
85 /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
86 PD_BUS_ACLK_DIV0_SHIFT = 3,
87 PD_BUS_ACLK_DIV0_MASK = 0x1f << PD_BUS_ACLK_DIV0_SHIFT,
88 PD_BUS_ACLK_DIV1_SHIFT = 0,
89 PD_BUS_ACLK_DIV1_MASK = 0x7 << PD_BUS_ACLK_DIV1_SHIFT,
90
91 /*
92 * CLKSEL10
93 * peripheral bus pclk div:
94 * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
95 */
96 PERI_SEL_PLL_SHIFT = 15,
97 PERI_SEL_PLL_MASK = 1 << PERI_SEL_PLL_SHIFT,
98 PERI_SEL_CPLL = 0,
99 PERI_SEL_GPLL,
100
101 PERI_PCLK_DIV_SHIFT = 12,
102 PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT,
103
104 /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
105 PERI_HCLK_DIV_SHIFT = 8,
106 PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT,
107
108 /*
109 * peripheral bus aclk div:
110 * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
111 */
112 PERI_ACLK_DIV_SHIFT = 0,
113 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
114
115 /*
116 * CLKSEL24
117 * saradc_div_con:
118 * clk_saradc=24MHz/(saradc_div_con+1)
119 */
120 CLK_SARADC_DIV_CON_SHIFT = 8,
121 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
122 CLK_SARADC_DIV_CON_WIDTH = 8,
123
124 SOCSTS_DPLL_LOCK = 1 << 5,
125 SOCSTS_APLL_LOCK = 1 << 6,
126 SOCSTS_CPLL_LOCK = 1 << 7,
127 SOCSTS_GPLL_LOCK = 1 << 8,
128 SOCSTS_NPLL_LOCK = 1 << 9,
129 };
130
131 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
132
133 #define PLL_DIVISORS(hz, _nr, _no) {\
134 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
135 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
136 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
137 "divisors on line " __stringify(__LINE__));
138
139 /* Keep divisors as low as possible to reduce jitter and power usage */
140 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
141 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
142 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
143
144 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
145 const struct pll_div *div)
146 {
147 int pll_id = rk_pll_id(clk_id);
148 struct rk3288_pll *pll = &cru->pll[pll_id];
149 /* All PLLs have same VCO and output frequency range restrictions. */
150 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
151 uint output_hz = vco_hz / div->no;
152
153 debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
154 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
155 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
156 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
157 (div->no == 1 || !(div->no % 2)));
158
159 /* enter reset */
160 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
161
162 rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK,
163 ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
164 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
165 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
166
167 udelay(10);
168
169 /* return from reset */
170 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
171
172 return 0;
173 }
174
175 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
176 unsigned int hz)
177 {
178 static const struct pll_div dpll_cfg[] = {
179 {.nf = 25, .nr = 2, .no = 1},
180 {.nf = 400, .nr = 9, .no = 2},
181 {.nf = 500, .nr = 9, .no = 2},
182 {.nf = 100, .nr = 3, .no = 1},
183 };
184 int cfg;
185
186 switch (hz) {
187 case 300000000:
188 cfg = 0;
189 break;
190 case 533000000: /* actually 533.3P MHz */
191 cfg = 1;
192 break;
193 case 666000000: /* actually 666.6P MHz */
194 cfg = 2;
195 break;
196 case 800000000:
197 cfg = 3;
198 break;
199 default:
200 debug("Unsupported SDRAM frequency");
201 return -EINVAL;
202 }
203
204 /* pll enter slow-mode */
205 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
206 DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
207
208 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
209
210 /* wait for pll lock */
211 while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK))
212 udelay(1);
213
214 /* PLL enter normal-mode */
215 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
216 DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
217
218 return 0;
219 }
220
221 #ifndef CONFIG_SPL_BUILD
222 #define VCO_MAX_KHZ 2200000
223 #define VCO_MIN_KHZ 440000
224 #define FREF_MAX_KHZ 2200000
225 #define FREF_MIN_KHZ 269
226
227 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
228 {
229 uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
230 uint fref_khz;
231 uint diff_khz, best_diff_khz;
232 const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
233 uint vco_khz;
234 uint no = 1;
235 uint freq_khz = freq_hz / 1000;
236
237 if (!freq_hz) {
238 printf("%s: the frequency can not be 0 Hz\n", __func__);
239 return -EINVAL;
240 }
241
242 no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
243 if (ext_div) {
244 *ext_div = DIV_ROUND_UP(no, max_no);
245 no = DIV_ROUND_UP(no, *ext_div);
246 }
247
248 /* only even divisors (and 1) are supported */
249 if (no > 1)
250 no = DIV_ROUND_UP(no, 2) * 2;
251
252 vco_khz = freq_khz * no;
253 if (ext_div)
254 vco_khz *= *ext_div;
255
256 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
257 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
258 __func__, freq_hz);
259 return -1;
260 }
261
262 div->no = no;
263
264 best_diff_khz = vco_khz;
265 for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
266 fref_khz = ref_khz / nr;
267 if (fref_khz < FREF_MIN_KHZ)
268 break;
269 if (fref_khz > FREF_MAX_KHZ)
270 continue;
271
272 nf = vco_khz / fref_khz;
273 if (nf >= max_nf)
274 continue;
275 diff_khz = vco_khz - nf * fref_khz;
276 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
277 nf++;
278 diff_khz = fref_khz - diff_khz;
279 }
280
281 if (diff_khz >= best_diff_khz)
282 continue;
283
284 best_diff_khz = diff_khz;
285 div->nr = nr;
286 div->nf = nf;
287 }
288
289 if (best_diff_khz > 4 * 1000) {
290 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
291 __func__, freq_hz, best_diff_khz * 1000);
292 return -EINVAL;
293 }
294
295 return 0;
296 }
297
298 static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq)
299 {
300 ulong ret;
301
302 /*
303 * The gmac clock can be derived either from an external clock
304 * or can be generated from internally by a divider from SCLK_MAC.
305 */
306 if (readl(&cru->cru_clksel_con[21]) & RMII_EXTCLK_MASK) {
307 /* An external clock will always generate the right rate... */
308 ret = freq;
309 } else {
310 u32 con = readl(&cru->cru_clksel_con[21]);
311 ulong pll_rate;
312 u8 div;
313
314 if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==
315 EMAC_PLL_SELECT_GENERAL)
316 pll_rate = GPLL_HZ;
317 else if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==
318 EMAC_PLL_SELECT_CODEC)
319 pll_rate = CPLL_HZ;
320 else
321 pll_rate = NPLL_HZ;
322
323 div = DIV_ROUND_UP(pll_rate, freq) - 1;
324 if (div <= 0x1f)
325 rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK,
326 div << MAC_DIV_CON_SHIFT);
327 else
328 debug("Unsupported div for gmac:%d\n", div);
329
330 return DIV_TO_RATE(pll_rate, div);
331 }
332
333 return ret;
334 }
335
336 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
337 int periph, unsigned int rate_hz)
338 {
339 struct pll_div npll_config = {0};
340 u32 lcdc_div;
341 int ret;
342
343 ret = pll_para_config(rate_hz, &npll_config, &lcdc_div);
344 if (ret)
345 return ret;
346
347 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
348 NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
349 rkclk_set_pll(cru, CLK_NEW, &npll_config);
350
351 /* waiting for pll lock */
352 while (1) {
353 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
354 break;
355 udelay(1);
356 }
357
358 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
359 NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
360
361 /* vop dclk source clk: npll,dclk_div: 1 */
362 switch (periph) {
363 case DCLK_VOP0:
364 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,
365 (lcdc_div - 1) << 8 | 2 << 0);
366 break;
367 case DCLK_VOP1:
368 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,
369 (lcdc_div - 1) << 8 | 2 << 6);
370 break;
371 }
372
373 return 0;
374 }
375 #endif /* CONFIG_SPL_BUILD */
376
377 static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
378 {
379 u32 aclk_div;
380 u32 hclk_div;
381 u32 pclk_div;
382
383 /* pll enter slow-mode */
384 rk_clrsetreg(&cru->cru_mode_con,
385 GPLL_MODE_MASK | CPLL_MODE_MASK,
386 GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
387 CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
388
389 /* init pll */
390 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
391 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
392
393 /* waiting for pll lock */
394 while ((readl(&grf->soc_status[1]) &
395 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
396 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
397 udelay(1);
398
399 /*
400 * pd_bus clock pll source selection and
401 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
402 */
403 aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
404 assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
405 hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
406 assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
407 PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
408
409 pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
410 assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
411 PD_BUS_ACLK_HZ && pclk_div < 0x7);
412
413 rk_clrsetreg(&cru->cru_clksel_con[1],
414 PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK |
415 PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK,
416 pclk_div << PD_BUS_PCLK_DIV_SHIFT |
417 hclk_div << PD_BUS_HCLK_DIV_SHIFT |
418 aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
419 0 << 0);
420
421 /*
422 * peri clock pll source selection and
423 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
424 */
425 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
426 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
427
428 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
429 assert((1 << hclk_div) * PERI_HCLK_HZ ==
430 PERI_ACLK_HZ && (hclk_div < 0x4));
431
432 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
433 assert((1 << pclk_div) * PERI_PCLK_HZ ==
434 PERI_ACLK_HZ && (pclk_div < 0x4));
435
436 rk_clrsetreg(&cru->cru_clksel_con[10],
437 PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK |
438 PERI_ACLK_DIV_MASK,
439 PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
440 pclk_div << PERI_PCLK_DIV_SHIFT |
441 hclk_div << PERI_HCLK_DIV_SHIFT |
442 aclk_div << PERI_ACLK_DIV_SHIFT);
443
444 /* PLL enter normal-mode */
445 rk_clrsetreg(&cru->cru_mode_con,
446 GPLL_MODE_MASK | CPLL_MODE_MASK,
447 GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
448 CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
449 }
450
451 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
452 {
453 /* pll enter slow-mode */
454 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
455 APLL_MODE_SLOW << APLL_MODE_SHIFT);
456
457 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
458
459 /* waiting for pll lock */
460 while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK))
461 udelay(1);
462
463 /*
464 * core clock pll source selection and
465 * set up dependent divisors for MPAXI/M0AXI and ARM clocks.
466 * core clock select apll, apll clk = 1800MHz
467 * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
468 */
469 rk_clrsetreg(&cru->cru_clksel_con[0],
470 CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK |
471 M0_DIV_MASK,
472 0 << A17_DIV_SHIFT |
473 3 << MP_DIV_SHIFT |
474 1 << M0_DIV_SHIFT);
475
476 /*
477 * set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
478 * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
479 */
480 rk_clrsetreg(&cru->cru_clksel_con[37],
481 CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK |
482 PCLK_CORE_DBG_DIV_MASK,
483 1 << CLK_L2RAM_DIV_SHIFT |
484 3 << ATCLK_CORE_DIV_CON_SHIFT |
485 3 << PCLK_CORE_DBG_DIV_SHIFT);
486
487 /* PLL enter normal-mode */
488 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
489 APLL_MODE_NORMAL << APLL_MODE_SHIFT);
490 }
491
492 /* Get pll rate by id */
493 static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
494 enum rk_clk_id clk_id)
495 {
496 uint32_t nr, no, nf;
497 uint32_t con;
498 int pll_id = rk_pll_id(clk_id);
499 struct rk3288_pll *pll = &cru->pll[pll_id];
500 static u8 clk_shift[CLK_COUNT] = {
501 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
502 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
503 };
504 uint shift;
505
506 con = readl(&cru->cru_mode_con);
507 shift = clk_shift[clk_id];
508 switch ((con >> shift) & CRU_MODE_MASK) {
509 case APLL_MODE_SLOW:
510 return OSC_HZ;
511 case APLL_MODE_NORMAL:
512 /* normal mode */
513 con = readl(&pll->con0);
514 no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1;
515 nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1;
516 con = readl(&pll->con1);
517 nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1;
518
519 return (24 * nf / (nr * no)) * 1000000;
520 case APLL_MODE_DEEP:
521 default:
522 return 32768;
523 }
524 }
525
526 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
527 int periph)
528 {
529 uint src_rate;
530 uint div, mux;
531 u32 con;
532
533 switch (periph) {
534 case HCLK_EMMC:
535 case SCLK_EMMC:
536 con = readl(&cru->cru_clksel_con[12]);
537 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
538 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
539 break;
540 case HCLK_SDMMC:
541 case SCLK_SDMMC:
542 con = readl(&cru->cru_clksel_con[11]);
543 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
544 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
545 break;
546 case HCLK_SDIO0:
547 case SCLK_SDIO0:
548 con = readl(&cru->cru_clksel_con[12]);
549 mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT;
550 div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT;
551 break;
552 default:
553 return -EINVAL;
554 }
555
556 src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
557 return DIV_TO_RATE(src_rate, div);
558 }
559
560 static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
561 int periph, uint freq)
562 {
563 int src_clk_div;
564 int mux;
565
566 debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
567 /* mmc clock default div 2 internal, need provide double in cru */
568 src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq);
569
570 if (src_clk_div > 0x3f) {
571 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
572 assert(src_clk_div < 0x40);
573 mux = EMMC_PLL_SELECT_24MHZ;
574 assert((int)EMMC_PLL_SELECT_24MHZ ==
575 (int)MMC0_PLL_SELECT_24MHZ);
576 } else {
577 mux = EMMC_PLL_SELECT_GENERAL;
578 assert((int)EMMC_PLL_SELECT_GENERAL ==
579 (int)MMC0_PLL_SELECT_GENERAL);
580 }
581 switch (periph) {
582 case HCLK_EMMC:
583 case SCLK_EMMC:
584 rk_clrsetreg(&cru->cru_clksel_con[12],
585 EMMC_PLL_MASK | EMMC_DIV_MASK,
586 mux << EMMC_PLL_SHIFT |
587 (src_clk_div - 1) << EMMC_DIV_SHIFT);
588 break;
589 case HCLK_SDMMC:
590 case SCLK_SDMMC:
591 rk_clrsetreg(&cru->cru_clksel_con[11],
592 MMC0_PLL_MASK | MMC0_DIV_MASK,
593 mux << MMC0_PLL_SHIFT |
594 (src_clk_div - 1) << MMC0_DIV_SHIFT);
595 break;
596 case HCLK_SDIO0:
597 case SCLK_SDIO0:
598 rk_clrsetreg(&cru->cru_clksel_con[12],
599 SDIO0_PLL_MASK | SDIO0_DIV_MASK,
600 mux << SDIO0_PLL_SHIFT |
601 (src_clk_div - 1) << SDIO0_DIV_SHIFT);
602 break;
603 default:
604 return -EINVAL;
605 }
606
607 return rockchip_mmc_get_clk(cru, gclk_rate, periph);
608 }
609
610 static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
611 int periph)
612 {
613 uint div, mux;
614 u32 con;
615
616 switch (periph) {
617 case SCLK_SPI0:
618 con = readl(&cru->cru_clksel_con[25]);
619 mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT;
620 div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT;
621 break;
622 case SCLK_SPI1:
623 con = readl(&cru->cru_clksel_con[25]);
624 mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT;
625 div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT;
626 break;
627 case SCLK_SPI2:
628 con = readl(&cru->cru_clksel_con[39]);
629 mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT;
630 div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT;
631 break;
632 default:
633 return -EINVAL;
634 }
635 assert(mux == SPI0_PLL_SELECT_GENERAL);
636
637 return DIV_TO_RATE(gclk_rate, div);
638 }
639
640 static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
641 int periph, uint freq)
642 {
643 int src_clk_div;
644
645 debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
646 src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
647 assert(src_clk_div < 128);
648 switch (periph) {
649 case SCLK_SPI0:
650 rk_clrsetreg(&cru->cru_clksel_con[25],
651 SPI0_PLL_MASK | SPI0_DIV_MASK,
652 SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
653 src_clk_div << SPI0_DIV_SHIFT);
654 break;
655 case SCLK_SPI1:
656 rk_clrsetreg(&cru->cru_clksel_con[25],
657 SPI1_PLL_MASK | SPI1_DIV_MASK,
658 SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
659 src_clk_div << SPI1_DIV_SHIFT);
660 break;
661 case SCLK_SPI2:
662 rk_clrsetreg(&cru->cru_clksel_con[39],
663 SPI2_PLL_MASK | SPI2_DIV_MASK,
664 SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
665 src_clk_div << SPI2_DIV_SHIFT);
666 break;
667 default:
668 return -EINVAL;
669 }
670
671 return rockchip_spi_get_clk(cru, gclk_rate, periph);
672 }
673
674 static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)
675 {
676 u32 div, val;
677
678 val = readl(&cru->cru_clksel_con[24]);
679 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
680 CLK_SARADC_DIV_CON_WIDTH);
681
682 return DIV_TO_RATE(OSC_HZ, div);
683 }
684
685 static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz)
686 {
687 int src_clk_div;
688
689 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
690 assert(src_clk_div < 128);
691
692 rk_clrsetreg(&cru->cru_clksel_con[24],
693 CLK_SARADC_DIV_CON_MASK,
694 src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
695
696 return rockchip_saradc_get_clk(cru);
697 }
698
699 static ulong rk3288_clk_get_rate(struct clk *clk)
700 {
701 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
702 ulong new_rate, gclk_rate;
703
704 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
705 switch (clk->id) {
706 case 0 ... 63:
707 new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
708 break;
709 case HCLK_EMMC:
710 case HCLK_SDMMC:
711 case HCLK_SDIO0:
712 case SCLK_EMMC:
713 case SCLK_SDMMC:
714 case SCLK_SDIO0:
715 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
716 break;
717 case SCLK_SPI0:
718 case SCLK_SPI1:
719 case SCLK_SPI2:
720 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id);
721 break;
722 case PCLK_I2C0:
723 case PCLK_I2C1:
724 case PCLK_I2C2:
725 case PCLK_I2C3:
726 case PCLK_I2C4:
727 case PCLK_I2C5:
728 return gclk_rate;
729 case PCLK_PWM:
730 return PD_BUS_PCLK_HZ;
731 case SCLK_SARADC:
732 new_rate = rockchip_saradc_get_clk(priv->cru);
733 break;
734 default:
735 return -ENOENT;
736 }
737
738 return new_rate;
739 }
740
741 static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
742 {
743 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
744 struct rk3288_cru *cru = priv->cru;
745 ulong new_rate, gclk_rate;
746
747 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
748 switch (clk->id) {
749 case PLL_APLL:
750 /* We only support a fixed rate here */
751 if (rate != 1800000000)
752 return -EINVAL;
753 rk3288_clk_configure_cpu(priv->cru, priv->grf);
754 new_rate = rate;
755 break;
756 case CLK_DDR:
757 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
758 break;
759 case HCLK_EMMC:
760 case HCLK_SDMMC:
761 case HCLK_SDIO0:
762 case SCLK_EMMC:
763 case SCLK_SDMMC:
764 case SCLK_SDIO0:
765 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
766 break;
767 case SCLK_SPI0:
768 case SCLK_SPI1:
769 case SCLK_SPI2:
770 new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate);
771 break;
772 #ifndef CONFIG_SPL_BUILD
773 case SCLK_MAC:
774 new_rate = rockchip_mac_set_clk(priv->cru, rate);
775 break;
776 case DCLK_VOP0:
777 case DCLK_VOP1:
778 new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate);
779 break;
780 case SCLK_EDP_24M:
781 /* clk_edp_24M source: 24M */
782 rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
783
784 /* rst edp */
785 rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
786 udelay(1);
787 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
788 new_rate = rate;
789 break;
790 case ACLK_VOP0:
791 case ACLK_VOP1: {
792 u32 div;
793
794 /* vop aclk source clk: cpll */
795 div = CPLL_HZ / rate;
796 assert((div - 1 < 64) && (div * rate == CPLL_HZ));
797
798 switch (clk->id) {
799 case ACLK_VOP0:
800 rk_clrsetreg(&cru->cru_clksel_con[31],
801 3 << 6 | 0x1f << 0,
802 0 << 6 | (div - 1) << 0);
803 break;
804 case ACLK_VOP1:
805 rk_clrsetreg(&cru->cru_clksel_con[31],
806 3 << 14 | 0x1f << 8,
807 0 << 14 | (div - 1) << 8);
808 break;
809 }
810 new_rate = rate;
811 break;
812 }
813 case PCLK_HDMI_CTRL:
814 /* enable pclk hdmi ctrl */
815 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);
816
817 /* software reset hdmi */
818 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
819 udelay(1);
820 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);
821 new_rate = rate;
822 break;
823 #endif
824 case SCLK_SARADC:
825 new_rate = rockchip_saradc_set_clk(priv->cru, rate);
826 break;
827 case PLL_GPLL:
828 case PLL_CPLL:
829 case PLL_NPLL:
830 case ACLK_CPU:
831 case HCLK_CPU:
832 case PCLK_CPU:
833 case ACLK_PERI:
834 case HCLK_PERI:
835 case PCLK_PERI:
836 case SCLK_UART0:
837 return 0;
838 default:
839 return -ENOENT;
840 }
841
842 return new_rate;
843 }
844
845 static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *parent)
846 {
847 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
848 struct rk3288_cru *cru = priv->cru;
849 const char *clock_output_name;
850 int ret;
851
852 /*
853 * If the requested parent is in the same clock-controller and
854 * the id is SCLK_MAC_PLL ("mac_pll_src"), switch to the internal
855 * clock.
856 */
857 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) {
858 debug("%s: switching GAMC to SCLK_MAC_PLL\n", __func__);
859 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0);
860 return 0;
861 }
862
863 /*
864 * Otherwise, we need to check the clock-output-names of the
865 * requested parent to see if the requested id is "ext_gmac".
866 */
867 ret = dev_read_string_index(parent->dev, "clock-output-names",
868 parent->id, &clock_output_name);
869 if (ret < 0)
870 return -ENODATA;
871
872 /* If this is "ext_gmac", switch to the external clock input */
873 if (!strcmp(clock_output_name, "ext_gmac")) {
874 debug("%s: switching GMAC to external clock\n", __func__);
875 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK,
876 RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
877 return 0;
878 }
879
880 return -EINVAL;
881 }
882
883 static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *parent)
884 {
885 switch (clk->id) {
886 case SCLK_MAC:
887 return rk3288_gmac_set_parent(clk, parent);
888 case SCLK_USBPHY480M_SRC:
889 return 0;
890 }
891
892 debug("%s: unsupported clk %ld\n", __func__, clk->id);
893 return -ENOENT;
894 }
895
896 static struct clk_ops rk3288_clk_ops = {
897 .get_rate = rk3288_clk_get_rate,
898 .set_rate = rk3288_clk_set_rate,
899 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
900 .set_parent = rk3288_clk_set_parent,
901 #endif
902 };
903
904 static int rk3288_clk_ofdata_to_platdata(struct udevice *dev)
905 {
906 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
907 struct rk3288_clk_priv *priv = dev_get_priv(dev);
908
909 priv->cru = (struct rk3288_cru *)devfdt_get_addr(dev);
910 #endif
911
912 return 0;
913 }
914
915 static int rk3288_clk_probe(struct udevice *dev)
916 {
917 struct rk3288_clk_priv *priv = dev_get_priv(dev);
918 bool init_clocks = false;
919
920 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
921 if (IS_ERR(priv->grf))
922 return PTR_ERR(priv->grf);
923 #ifdef CONFIG_SPL_BUILD
924 #if CONFIG_IS_ENABLED(OF_PLATDATA)
925 struct rk3288_clk_plat *plat = dev_get_platdata(dev);
926
927 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
928 #endif
929 init_clocks = true;
930 #endif
931 if (!(gd->flags & GD_FLG_RELOC)) {
932 u32 reg;
933
934 /*
935 * Init clocks in U-Boot proper if the NPLL is runnning. This
936 * indicates that a previous boot loader set up the clocks, so
937 * we need to redo it. U-Boot's SPL does not set this clock.
938 */
939 reg = readl(&priv->cru->cru_mode_con);
940 if (((reg & NPLL_MODE_MASK) >> NPLL_MODE_SHIFT) ==
941 NPLL_MODE_NORMAL)
942 init_clocks = true;
943 }
944
945 if (init_clocks)
946 rkclk_init(priv->cru, priv->grf);
947
948 return 0;
949 }
950
951 static int rk3288_clk_bind(struct udevice *dev)
952 {
953 int ret;
954 struct udevice *sys_child;
955 struct sysreset_reg *priv;
956
957 /* The reset driver does not have a device node, so bind it here */
958 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
959 &sys_child);
960 if (ret) {
961 debug("Warning: No sysreset driver: ret=%d\n", ret);
962 } else {
963 priv = malloc(sizeof(struct sysreset_reg));
964 priv->glb_srst_fst_value = offsetof(struct rk3288_cru,
965 cru_glb_srst_fst_value);
966 priv->glb_srst_snd_value = offsetof(struct rk3288_cru,
967 cru_glb_srst_snd_value);
968 sys_child->priv = priv;
969 }
970
971 #if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
972 ret = offsetof(struct rk3288_cru, cru_softrst_con[0]);
973 ret = rockchip_reset_bind(dev, ret, 12);
974 if (ret)
975 debug("Warning: software reset driver bind faile\n");
976 #endif
977
978 return 0;
979 }
980
981 static const struct udevice_id rk3288_clk_ids[] = {
982 { .compatible = "rockchip,rk3288-cru" },
983 { }
984 };
985
986 U_BOOT_DRIVER(rockchip_rk3288_cru) = {
987 .name = "rockchip_rk3288_cru",
988 .id = UCLASS_CLK,
989 .of_match = rk3288_clk_ids,
990 .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
991 .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat),
992 .ops = &rk3288_clk_ops,
993 .bind = rk3288_clk_bind,
994 .ofdata_to_platdata = rk3288_clk_ofdata_to_platdata,
995 .probe = rk3288_clk_probe,
996 };
"Das U-Boot" Source Tree