2 * (C) Copyright 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
10 #include <dt-structs.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/cru_rk3288.h>
17 #include <asm/arch/grf_rk3288.h>
18 #include <asm/arch/hardware.h>
19 #include <dt-bindings/clock/rk3288-cru.h>
20 #include <dm/device-internal.h>
22 #include <dm/uclass-internal.h>
24 DECLARE_GLOBAL_DATA_PTR
;
26 struct rk3288_clk_plat
{
27 #if CONFIG_IS_ENABLED(OF_PLATDATA)
28 struct dtd_rockchip_rk3288_cru dtd
;
32 struct rk3288_clk_priv
{
33 struct rk3288_grf
*grf
;
34 struct rk3288_cru
*cru
;
45 VCO_MAX_HZ
= 2200U * 1000000,
46 VCO_MIN_HZ
= 440 * 1000000,
47 OUTPUT_MAX_HZ
= 2200U * 1000000,
48 OUTPUT_MIN_HZ
= 27500000,
49 FREF_MAX_HZ
= 2200U * 1000000,
50 FREF_MIN_HZ
= 269 * 1000,
61 PLL_BWADJ_MASK
= 0x0fff,
67 CORE_SEL_PLL_MASK
= 1,
68 CORE_SEL_PLL_SHIFT
= 15,
76 /* CLKSEL1: pd bus clk pll sel: codec or general */
77 PD_BUS_SEL_PLL_MASK
= 15,
81 /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
82 PD_BUS_PCLK_DIV_SHIFT
= 12,
83 PD_BUS_PCLK_DIV_MASK
= 7,
85 /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
86 PD_BUS_HCLK_DIV_SHIFT
= 8,
87 PD_BUS_HCLK_DIV_MASK
= 3,
89 /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
90 PD_BUS_ACLK_DIV0_SHIFT
= 3,
91 PD_BUS_ACLK_DIV0_MASK
= 0x1f,
92 PD_BUS_ACLK_DIV1_SHIFT
= 0,
93 PD_BUS_ACLK_DIV1_MASK
= 0x7,
97 * peripheral bus pclk div:
98 * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
100 PERI_SEL_PLL_MASK
= 1,
101 PERI_SEL_PLL_SHIFT
= 15,
105 PERI_PCLK_DIV_SHIFT
= 12,
106 PERI_PCLK_DIV_MASK
= 3,
108 /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
109 PERI_HCLK_DIV_SHIFT
= 8,
110 PERI_HCLK_DIV_MASK
= 3,
113 * peripheral bus aclk div:
114 * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
116 PERI_ACLK_DIV_SHIFT
= 0,
117 PERI_ACLK_DIV_MASK
= 0x1f,
119 SOCSTS_DPLL_LOCK
= 1 << 5,
120 SOCSTS_APLL_LOCK
= 1 << 6,
121 SOCSTS_CPLL_LOCK
= 1 << 7,
122 SOCSTS_GPLL_LOCK
= 1 << 8,
123 SOCSTS_NPLL_LOCK
= 1 << 9,
126 #define RATE_TO_DIV(input_rate, output_rate) \
127 ((input_rate) / (output_rate) - 1);
129 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
131 #define PLL_DIVISORS(hz, _nr, _no) {\
132 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
133 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
134 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
135 "divisors on line " __stringify(__LINE__));
137 /* Keep divisors as low as possible to reduce jitter and power usage */
138 static const struct pll_div apll_init_cfg
= PLL_DIVISORS(APLL_HZ
, 1, 1);
139 static const struct pll_div gpll_init_cfg
= PLL_DIVISORS(GPLL_HZ
, 2, 2);
140 static const struct pll_div cpll_init_cfg
= PLL_DIVISORS(CPLL_HZ
, 1, 2);
142 void *rockchip_get_cru(void)
144 struct rk3288_clk_priv
*priv
;
148 ret
= rockchip_get_clk(&dev
);
152 priv
= dev_get_priv(dev
);
157 static int rkclk_set_pll(struct rk3288_cru
*cru
, enum rk_clk_id clk_id
,
158 const struct pll_div
*div
)
160 int pll_id
= rk_pll_id(clk_id
);
161 struct rk3288_pll
*pll
= &cru
->pll
[pll_id
];
162 /* All PLLs have same VCO and output frequency range restrictions. */
163 uint vco_hz
= OSC_HZ
/ 1000 * div
->nf
/ div
->nr
* 1000;
164 uint output_hz
= vco_hz
/ div
->no
;
166 debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
167 (uint
)pll
, div
->nf
, div
->nr
, div
->no
, vco_hz
, output_hz
);
168 assert(vco_hz
>= VCO_MIN_HZ
&& vco_hz
<= VCO_MAX_HZ
&&
169 output_hz
>= OUTPUT_MIN_HZ
&& output_hz
<= OUTPUT_MAX_HZ
&&
170 (div
->no
== 1 || !(div
->no
% 2)));
173 rk_setreg(&pll
->con3
, 1 << PLL_RESET_SHIFT
);
175 rk_clrsetreg(&pll
->con0
,
176 CLKR_MASK
<< CLKR_SHIFT
| PLL_OD_MASK
,
177 ((div
->nr
- 1) << CLKR_SHIFT
) | (div
->no
- 1));
178 rk_clrsetreg(&pll
->con1
, CLKF_MASK
, div
->nf
- 1);
179 rk_clrsetreg(&pll
->con2
, PLL_BWADJ_MASK
, (div
->nf
>> 1) - 1);
183 /* return from reset */
184 rk_clrreg(&pll
->con3
, 1 << PLL_RESET_SHIFT
);
189 static inline unsigned int log2(unsigned int value
)
191 return fls(value
) - 1;
194 static int rkclk_configure_ddr(struct rk3288_cru
*cru
, struct rk3288_grf
*grf
,
197 static const struct pll_div dpll_cfg
[] = {
198 {.nf
= 25, .nr
= 2, .no
= 1},
199 {.nf
= 400, .nr
= 9, .no
= 2},
200 {.nf
= 500, .nr
= 9, .no
= 2},
201 {.nf
= 100, .nr
= 3, .no
= 1},
209 case 533000000: /* actually 533.3P MHz */
212 case 666000000: /* actually 666.6P MHz */
219 debug("Unsupported SDRAM frequency");
223 /* pll enter slow-mode */
224 rk_clrsetreg(&cru
->cru_mode_con
, DPLL_MODE_MASK
<< DPLL_MODE_SHIFT
,
225 DPLL_MODE_SLOW
<< DPLL_MODE_SHIFT
);
227 rkclk_set_pll(cru
, CLK_DDR
, &dpll_cfg
[cfg
]);
229 /* wait for pll lock */
230 while (!(readl(&grf
->soc_status
[1]) & SOCSTS_DPLL_LOCK
))
233 /* PLL enter normal-mode */
234 rk_clrsetreg(&cru
->cru_mode_con
, DPLL_MODE_MASK
<< DPLL_MODE_SHIFT
,
235 DPLL_MODE_NORMAL
<< DPLL_MODE_SHIFT
);
240 #ifndef CONFIG_SPL_BUILD
241 #define VCO_MAX_KHZ 2200000
242 #define VCO_MIN_KHZ 440000
243 #define FREF_MAX_KHZ 2200000
244 #define FREF_MIN_KHZ 269
246 static int pll_para_config(ulong freq_hz
, struct pll_div
*div
, uint
*ext_div
)
248 uint ref_khz
= OSC_HZ
/ 1000, nr
, nf
= 0;
250 uint diff_khz
, best_diff_khz
;
251 const uint max_nr
= 1 << 6, max_nf
= 1 << 12, max_no
= 1 << 4;
254 uint freq_khz
= freq_hz
/ 1000;
257 printf("%s: the frequency can not be 0 Hz\n", __func__
);
261 no
= DIV_ROUND_UP(VCO_MIN_KHZ
, freq_khz
);
263 *ext_div
= DIV_ROUND_UP(no
, max_no
);
264 no
= DIV_ROUND_UP(no
, *ext_div
);
267 /* only even divisors (and 1) are supported */
269 no
= DIV_ROUND_UP(no
, 2) * 2;
271 vco_khz
= freq_khz
* no
;
275 if (vco_khz
< VCO_MIN_KHZ
|| vco_khz
> VCO_MAX_KHZ
|| no
> max_no
) {
276 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
283 best_diff_khz
= vco_khz
;
284 for (nr
= 1; nr
< max_nr
&& best_diff_khz
; nr
++) {
285 fref_khz
= ref_khz
/ nr
;
286 if (fref_khz
< FREF_MIN_KHZ
)
288 if (fref_khz
> FREF_MAX_KHZ
)
291 nf
= vco_khz
/ fref_khz
;
294 diff_khz
= vco_khz
- nf
* fref_khz
;
295 if (nf
+ 1 < max_nf
&& diff_khz
> fref_khz
/ 2) {
297 diff_khz
= fref_khz
- diff_khz
;
300 if (diff_khz
>= best_diff_khz
)
303 best_diff_khz
= diff_khz
;
308 if (best_diff_khz
> 4 * 1000) {
309 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
310 __func__
, freq_hz
, best_diff_khz
* 1000);
317 static int rockchip_mac_set_clk(struct rk3288_cru
*cru
,
318 int periph
, uint freq
)
320 /* Assuming mac_clk is fed by an external clock */
321 rk_clrsetreg(&cru
->cru_clksel_con
[21],
322 RMII_EXTCLK_MASK
<< RMII_EXTCLK_SHIFT
,
323 RMII_EXTCLK_SELECT_EXT_CLK
<< RMII_EXTCLK_SHIFT
);
328 static int rockchip_vop_set_clk(struct rk3288_cru
*cru
, struct rk3288_grf
*grf
,
329 int periph
, unsigned int rate_hz
)
331 struct pll_div npll_config
= {0};
335 ret
= pll_para_config(rate_hz
, &npll_config
, &lcdc_div
);
339 rk_clrsetreg(&cru
->cru_mode_con
, NPLL_MODE_MASK
<< NPLL_MODE_SHIFT
,
340 NPLL_MODE_SLOW
<< NPLL_MODE_SHIFT
);
341 rkclk_set_pll(cru
, CLK_NEW
, &npll_config
);
343 /* waiting for pll lock */
345 if (readl(&grf
->soc_status
[1]) & SOCSTS_NPLL_LOCK
)
350 rk_clrsetreg(&cru
->cru_mode_con
, NPLL_MODE_MASK
<< NPLL_MODE_SHIFT
,
351 NPLL_MODE_NORMAL
<< NPLL_MODE_SHIFT
);
353 /* vop dclk source clk: npll,dclk_div: 1 */
356 rk_clrsetreg(&cru
->cru_clksel_con
[27], 0xff << 8 | 3 << 0,
357 (lcdc_div
- 1) << 8 | 2 << 0);
360 rk_clrsetreg(&cru
->cru_clksel_con
[29], 0xff << 8 | 3 << 6,
361 (lcdc_div
- 1) << 8 | 2 << 6);
369 #ifdef CONFIG_SPL_BUILD
370 static void rkclk_init(struct rk3288_cru
*cru
, struct rk3288_grf
*grf
)
376 /* pll enter slow-mode */
377 rk_clrsetreg(&cru
->cru_mode_con
,
378 GPLL_MODE_MASK
<< GPLL_MODE_SHIFT
|
379 CPLL_MODE_MASK
<< CPLL_MODE_SHIFT
,
380 GPLL_MODE_SLOW
<< GPLL_MODE_SHIFT
|
381 CPLL_MODE_SLOW
<< CPLL_MODE_SHIFT
);
384 rkclk_set_pll(cru
, CLK_GENERAL
, &gpll_init_cfg
);
385 rkclk_set_pll(cru
, CLK_CODEC
, &cpll_init_cfg
);
387 /* waiting for pll lock */
388 while ((readl(&grf
->soc_status
[1]) &
389 (SOCSTS_CPLL_LOCK
| SOCSTS_GPLL_LOCK
)) !=
390 (SOCSTS_CPLL_LOCK
| SOCSTS_GPLL_LOCK
))
394 * pd_bus clock pll source selection and
395 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
397 aclk_div
= GPLL_HZ
/ PD_BUS_ACLK_HZ
- 1;
398 assert((aclk_div
+ 1) * PD_BUS_ACLK_HZ
== GPLL_HZ
&& aclk_div
< 0x1f);
399 hclk_div
= PD_BUS_ACLK_HZ
/ PD_BUS_HCLK_HZ
- 1;
400 assert((hclk_div
+ 1) * PD_BUS_HCLK_HZ
==
401 PD_BUS_ACLK_HZ
&& (hclk_div
< 0x4) && (hclk_div
!= 0x2));
403 pclk_div
= PD_BUS_ACLK_HZ
/ PD_BUS_PCLK_HZ
- 1;
404 assert((pclk_div
+ 1) * PD_BUS_PCLK_HZ
==
405 PD_BUS_ACLK_HZ
&& pclk_div
< 0x7);
407 rk_clrsetreg(&cru
->cru_clksel_con
[1],
408 PD_BUS_PCLK_DIV_MASK
<< PD_BUS_PCLK_DIV_SHIFT
|
409 PD_BUS_HCLK_DIV_MASK
<< PD_BUS_HCLK_DIV_SHIFT
|
410 PD_BUS_ACLK_DIV0_MASK
<< PD_BUS_ACLK_DIV0_SHIFT
|
411 PD_BUS_ACLK_DIV1_MASK
<< PD_BUS_ACLK_DIV1_SHIFT
,
412 pclk_div
<< PD_BUS_PCLK_DIV_SHIFT
|
413 hclk_div
<< PD_BUS_HCLK_DIV_SHIFT
|
414 aclk_div
<< PD_BUS_ACLK_DIV0_SHIFT
|
418 * peri clock pll source selection and
419 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
421 aclk_div
= GPLL_HZ
/ PERI_ACLK_HZ
- 1;
422 assert((aclk_div
+ 1) * PERI_ACLK_HZ
== GPLL_HZ
&& aclk_div
< 0x1f);
424 hclk_div
= log2(PERI_ACLK_HZ
/ PERI_HCLK_HZ
);
425 assert((1 << hclk_div
) * PERI_HCLK_HZ
==
426 PERI_ACLK_HZ
&& (hclk_div
< 0x4));
428 pclk_div
= log2(PERI_ACLK_HZ
/ PERI_PCLK_HZ
);
429 assert((1 << pclk_div
) * PERI_PCLK_HZ
==
430 PERI_ACLK_HZ
&& (pclk_div
< 0x4));
432 rk_clrsetreg(&cru
->cru_clksel_con
[10],
433 PERI_PCLK_DIV_MASK
<< PERI_PCLK_DIV_SHIFT
|
434 PERI_HCLK_DIV_MASK
<< PERI_HCLK_DIV_SHIFT
|
435 PERI_ACLK_DIV_MASK
<< PERI_ACLK_DIV_SHIFT
,
436 PERI_SEL_GPLL
<< PERI_SEL_PLL_SHIFT
|
437 pclk_div
<< PERI_PCLK_DIV_SHIFT
|
438 hclk_div
<< PERI_HCLK_DIV_SHIFT
|
439 aclk_div
<< PERI_ACLK_DIV_SHIFT
);
441 /* PLL enter normal-mode */
442 rk_clrsetreg(&cru
->cru_mode_con
,
443 GPLL_MODE_MASK
<< GPLL_MODE_SHIFT
|
444 CPLL_MODE_MASK
<< CPLL_MODE_SHIFT
,
445 GPLL_MODE_NORMAL
<< GPLL_MODE_SHIFT
|
446 CPLL_MODE_NORMAL
<< CPLL_MODE_SHIFT
);
450 void rk3288_clk_configure_cpu(struct rk3288_cru
*cru
, struct rk3288_grf
*grf
)
452 /* pll enter slow-mode */
453 rk_clrsetreg(&cru
->cru_mode_con
,
454 APLL_MODE_MASK
<< APLL_MODE_SHIFT
,
455 APLL_MODE_SLOW
<< APLL_MODE_SHIFT
);
457 rkclk_set_pll(cru
, CLK_ARM
, &apll_init_cfg
);
459 /* waiting for pll lock */
460 while (!(readl(&grf
->soc_status
[1]) & SOCSTS_APLL_LOCK
))
464 * core clock pll source selection and
465 * set up dependent divisors for MPAXI/M0AXI and ARM clocks.
466 * core clock select apll, apll clk = 1800MHz
467 * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
469 rk_clrsetreg(&cru
->cru_clksel_con
[0],
470 CORE_SEL_PLL_MASK
<< CORE_SEL_PLL_SHIFT
|
471 A17_DIV_MASK
<< A17_DIV_SHIFT
|
472 MP_DIV_MASK
<< MP_DIV_SHIFT
|
473 M0_DIV_MASK
<< M0_DIV_SHIFT
,
479 * set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
480 * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
482 rk_clrsetreg(&cru
->cru_clksel_con
[37],
483 CLK_L2RAM_DIV_MASK
<< CLK_L2RAM_DIV_SHIFT
|
484 ATCLK_CORE_DIV_CON_MASK
<< ATCLK_CORE_DIV_CON_SHIFT
|
485 PCLK_CORE_DBG_DIV_MASK
>> PCLK_CORE_DBG_DIV_SHIFT
,
486 1 << CLK_L2RAM_DIV_SHIFT
|
487 3 << ATCLK_CORE_DIV_CON_SHIFT
|
488 3 << PCLK_CORE_DBG_DIV_SHIFT
);
490 /* PLL enter normal-mode */
491 rk_clrsetreg(&cru
->cru_mode_con
,
492 APLL_MODE_MASK
<< APLL_MODE_SHIFT
,
493 APLL_MODE_NORMAL
<< APLL_MODE_SHIFT
);
496 /* Get pll rate by id */
497 static uint32_t rkclk_pll_get_rate(struct rk3288_cru
*cru
,
498 enum rk_clk_id clk_id
)
502 int pll_id
= rk_pll_id(clk_id
);
503 struct rk3288_pll
*pll
= &cru
->pll
[pll_id
];
504 static u8 clk_shift
[CLK_COUNT
] = {
505 0xff, APLL_MODE_SHIFT
, DPLL_MODE_SHIFT
, CPLL_MODE_SHIFT
,
506 GPLL_MODE_SHIFT
, NPLL_MODE_SHIFT
510 con
= readl(&cru
->cru_mode_con
);
511 shift
= clk_shift
[clk_id
];
512 switch ((con
>> shift
) & APLL_MODE_MASK
) {
515 case APLL_MODE_NORMAL
:
517 con
= readl(&pll
->con0
);
518 no
= ((con
>> CLKOD_SHIFT
) & CLKOD_MASK
) + 1;
519 nr
= ((con
>> CLKR_SHIFT
) & CLKR_MASK
) + 1;
520 con
= readl(&pll
->con1
);
521 nf
= ((con
>> CLKF_SHIFT
) & CLKF_MASK
) + 1;
523 return (24 * nf
/ (nr
* no
)) * 1000000;
530 static ulong
rockchip_mmc_get_clk(struct rk3288_cru
*cru
, uint gclk_rate
,
539 con
= readl(&cru
->cru_clksel_con
[12]);
540 mux
= (con
>> EMMC_PLL_SHIFT
) & EMMC_PLL_MASK
;
541 div
= (con
>> EMMC_DIV_SHIFT
) & EMMC_DIV_MASK
;
544 con
= readl(&cru
->cru_clksel_con
[11]);
545 mux
= (con
>> MMC0_PLL_SHIFT
) & MMC0_PLL_MASK
;
546 div
= (con
>> MMC0_DIV_SHIFT
) & MMC0_DIV_MASK
;
549 con
= readl(&cru
->cru_clksel_con
[12]);
550 mux
= (con
>> SDIO0_PLL_SHIFT
) & SDIO0_PLL_MASK
;
551 div
= (con
>> SDIO0_DIV_SHIFT
) & SDIO0_DIV_MASK
;
557 src_rate
= mux
== EMMC_PLL_SELECT_24MHZ
? OSC_HZ
: gclk_rate
;
558 return DIV_TO_RATE(src_rate
, div
);
561 static ulong
rockchip_mmc_set_clk(struct rk3288_cru
*cru
, uint gclk_rate
,
562 int periph
, uint freq
)
567 debug("%s: gclk_rate=%u\n", __func__
, gclk_rate
);
568 src_clk_div
= RATE_TO_DIV(gclk_rate
, freq
);
570 if (src_clk_div
> 0x3f) {
571 src_clk_div
= RATE_TO_DIV(OSC_HZ
, freq
);
572 mux
= EMMC_PLL_SELECT_24MHZ
;
573 assert((int)EMMC_PLL_SELECT_24MHZ
==
574 (int)MMC0_PLL_SELECT_24MHZ
);
576 mux
= EMMC_PLL_SELECT_GENERAL
;
577 assert((int)EMMC_PLL_SELECT_GENERAL
==
578 (int)MMC0_PLL_SELECT_GENERAL
);
582 rk_clrsetreg(&cru
->cru_clksel_con
[12],
583 EMMC_PLL_MASK
<< EMMC_PLL_SHIFT
|
584 EMMC_DIV_MASK
<< EMMC_DIV_SHIFT
,
585 mux
<< EMMC_PLL_SHIFT
|
586 (src_clk_div
- 1) << EMMC_DIV_SHIFT
);
589 rk_clrsetreg(&cru
->cru_clksel_con
[11],
590 MMC0_PLL_MASK
<< MMC0_PLL_SHIFT
|
591 MMC0_DIV_MASK
<< MMC0_DIV_SHIFT
,
592 mux
<< MMC0_PLL_SHIFT
|
593 (src_clk_div
- 1) << MMC0_DIV_SHIFT
);
596 rk_clrsetreg(&cru
->cru_clksel_con
[12],
597 SDIO0_PLL_MASK
<< SDIO0_PLL_SHIFT
|
598 SDIO0_DIV_MASK
<< SDIO0_DIV_SHIFT
,
599 mux
<< SDIO0_PLL_SHIFT
|
600 (src_clk_div
- 1) << SDIO0_DIV_SHIFT
);
606 return rockchip_mmc_get_clk(cru
, gclk_rate
, periph
);
609 static ulong
rockchip_spi_get_clk(struct rk3288_cru
*cru
, uint gclk_rate
,
617 con
= readl(&cru
->cru_clksel_con
[25]);
618 mux
= (con
>> SPI0_PLL_SHIFT
) & SPI0_PLL_MASK
;
619 div
= (con
>> SPI0_DIV_SHIFT
) & SPI0_DIV_MASK
;
622 con
= readl(&cru
->cru_clksel_con
[25]);
623 mux
= (con
>> SPI1_PLL_SHIFT
) & SPI1_PLL_MASK
;
624 div
= (con
>> SPI1_DIV_SHIFT
) & SPI1_DIV_MASK
;
627 con
= readl(&cru
->cru_clksel_con
[39]);
628 mux
= (con
>> SPI2_PLL_SHIFT
) & SPI2_PLL_MASK
;
629 div
= (con
>> SPI2_DIV_SHIFT
) & SPI2_DIV_MASK
;
634 assert(mux
== SPI0_PLL_SELECT_GENERAL
);
636 return DIV_TO_RATE(gclk_rate
, div
);
639 static ulong
rockchip_spi_set_clk(struct rk3288_cru
*cru
, uint gclk_rate
,
640 int periph
, uint freq
)
644 debug("%s: clk_general_rate=%u\n", __func__
, gclk_rate
);
645 src_clk_div
= RATE_TO_DIV(gclk_rate
, freq
);
648 rk_clrsetreg(&cru
->cru_clksel_con
[25],
649 SPI0_PLL_MASK
<< SPI0_PLL_SHIFT
|
650 SPI0_DIV_MASK
<< SPI0_DIV_SHIFT
,
651 SPI0_PLL_SELECT_GENERAL
<< SPI0_PLL_SHIFT
|
652 src_clk_div
<< SPI0_DIV_SHIFT
);
655 rk_clrsetreg(&cru
->cru_clksel_con
[25],
656 SPI1_PLL_MASK
<< SPI1_PLL_SHIFT
|
657 SPI1_DIV_MASK
<< SPI1_DIV_SHIFT
,
658 SPI1_PLL_SELECT_GENERAL
<< SPI1_PLL_SHIFT
|
659 src_clk_div
<< SPI1_DIV_SHIFT
);
662 rk_clrsetreg(&cru
->cru_clksel_con
[39],
663 SPI2_PLL_MASK
<< SPI2_PLL_SHIFT
|
664 SPI2_DIV_MASK
<< SPI2_DIV_SHIFT
,
665 SPI2_PLL_SELECT_GENERAL
<< SPI2_PLL_SHIFT
|
666 src_clk_div
<< SPI2_DIV_SHIFT
);
672 return rockchip_spi_get_clk(cru
, gclk_rate
, periph
);
675 static ulong
rk3288_clk_get_rate(struct clk
*clk
)
677 struct rk3288_clk_priv
*priv
= dev_get_priv(clk
->dev
);
678 ulong new_rate
, gclk_rate
;
680 gclk_rate
= rkclk_pll_get_rate(priv
->cru
, CLK_GENERAL
);
683 new_rate
= rkclk_pll_get_rate(priv
->cru
, clk
->id
);
688 new_rate
= rockchip_mmc_get_clk(priv
->cru
, gclk_rate
, clk
->id
);
693 new_rate
= rockchip_spi_get_clk(priv
->cru
, gclk_rate
, clk
->id
);
709 static ulong
rk3288_clk_set_rate(struct clk
*clk
, ulong rate
)
711 struct rk3288_clk_priv
*priv
= dev_get_priv(clk
->dev
);
712 struct rk3288_cru
*cru
= priv
->cru
;
713 ulong new_rate
, gclk_rate
;
715 gclk_rate
= rkclk_pll_get_rate(priv
->cru
, CLK_GENERAL
);
718 new_rate
= rkclk_configure_ddr(priv
->cru
, priv
->grf
, rate
);
723 new_rate
= rockchip_mmc_set_clk(cru
, gclk_rate
, clk
->id
, rate
);
728 new_rate
= rockchip_spi_set_clk(cru
, gclk_rate
, clk
->id
, rate
);
730 #ifndef CONFIG_SPL_BUILD
732 new_rate
= rockchip_mac_set_clk(priv
->cru
, clk
->id
, rate
);
736 new_rate
= rockchip_vop_set_clk(cru
, priv
->grf
, clk
->id
, rate
);
739 /* clk_edp_24M source: 24M */
740 rk_setreg(&cru
->cru_clksel_con
[28], 1 << 15);
743 rk_setreg(&cru
->cru_clksel_con
[6], 1 << 15);
745 rk_clrreg(&cru
->cru_clksel_con
[6], 1 << 15);
752 /* vop aclk source clk: cpll */
753 div
= CPLL_HZ
/ rate
;
754 assert((div
- 1 < 64) && (div
* rate
== CPLL_HZ
));
758 rk_clrsetreg(&cru
->cru_clksel_con
[31],
760 0 << 6 | (div
- 1) << 0);
763 rk_clrsetreg(&cru
->cru_clksel_con
[31],
765 0 << 14 | (div
- 1) << 8);
772 /* enable pclk hdmi ctrl */
773 rk_clrreg(&cru
->cru_clkgate_con
[16], 1 << 9);
775 /* software reset hdmi */
776 rk_setreg(&cru
->cru_clkgate_con
[7], 1 << 9);
778 rk_clrreg(&cru
->cru_clkgate_con
[7], 1 << 9);
789 static struct clk_ops rk3288_clk_ops
= {
790 .get_rate
= rk3288_clk_get_rate
,
791 .set_rate
= rk3288_clk_set_rate
,
794 static int rk3288_clk_ofdata_to_platdata(struct udevice
*dev
)
796 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
797 struct rk3288_clk_priv
*priv
= dev_get_priv(dev
);
799 priv
->cru
= (struct rk3288_cru
*)dev_get_addr(dev
);
805 static int rk3288_clk_probe(struct udevice
*dev
)
807 struct rk3288_clk_priv
*priv
= dev_get_priv(dev
);
809 priv
->grf
= syscon_get_first_range(ROCKCHIP_SYSCON_GRF
);
810 if (IS_ERR(priv
->grf
))
811 return PTR_ERR(priv
->grf
);
812 #ifdef CONFIG_SPL_BUILD
813 #if CONFIG_IS_ENABLED(OF_PLATDATA)
814 struct rk3288_clk_plat
*plat
= dev_get_platdata(dev
);
816 priv
->cru
= map_sysmem(plat
->dtd
.reg
[0], plat
->dtd
.reg
[1]);
818 rkclk_init(priv
->cru
, priv
->grf
);
824 static int rk3288_clk_bind(struct udevice
*dev
)
828 /* The reset driver does not have a device node, so bind it here */
829 ret
= device_bind_driver(gd
->dm_root
, "rk3288_sysreset", "reset", &dev
);
831 debug("Warning: No RK3288 reset driver: ret=%d\n", ret
);
836 static const struct udevice_id rk3288_clk_ids
[] = {
837 { .compatible
= "rockchip,rk3288-cru" },
841 U_BOOT_DRIVER(rockchip_rk3288_cru
) = {
842 .name
= "rockchip_rk3288_cru",
844 .of_match
= rk3288_clk_ids
,
845 .priv_auto_alloc_size
= sizeof(struct rk3288_clk_priv
),
846 .platdata_auto_alloc_size
= sizeof(struct rk3288_clk_plat
),
847 .ops
= &rk3288_clk_ops
,
848 .bind
= rk3288_clk_bind
,
849 .ofdata_to_platdata
= rk3288_clk_ofdata_to_platdata
,
850 .probe
= rk3288_clk_probe
,