2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/cru_rk3328.h>
14 #include <asm/arch/hardware.h>
17 #include <dt-bindings/clock/rk3328-cru.h>
19 DECLARE_GLOBAL_DATA_PTR
;
29 #define RATE_TO_DIV(input_rate, output_rate) \
30 ((input_rate) / (output_rate) - 1);
31 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
33 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
35 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
36 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
38 static const struct pll_div gpll_init_cfg
= PLL_DIVISORS(GPLL_HZ
, 1, 4, 1);
39 static const struct pll_div cpll_init_cfg
= PLL_DIVISORS(CPLL_HZ
, 2, 2, 1);
41 static const struct pll_div apll_816_cfg
= PLL_DIVISORS(816 * MHz
, 1, 2, 1);
42 static const struct pll_div apll_600_cfg
= PLL_DIVISORS(600 * MHz
, 1, 3, 1);
44 static const struct pll_div
*apll_cfgs
[] = {
45 [APLL_816_MHZ
] = &apll_816_cfg
,
46 [APLL_600_MHZ
] = &apll_600_cfg
,
51 PLL_POSTDIV1_SHIFT
= 12,
52 PLL_POSTDIV1_MASK
= 0x7 << PLL_POSTDIV1_SHIFT
,
54 PLL_FBDIV_MASK
= 0xfff,
58 PLL_DSMPD_MASK
= 1 << PLL_DSMPD_SHIFT
,
60 PLL_LOCK_STATUS_SHIFT
= 10,
61 PLL_LOCK_STATUS_MASK
= 1 << PLL_LOCK_STATUS_SHIFT
,
62 PLL_POSTDIV2_SHIFT
= 6,
63 PLL_POSTDIV2_MASK
= 0x7 << PLL_POSTDIV2_SHIFT
,
65 PLL_REFDIV_MASK
= 0x3f,
68 PLL_FRACDIV_SHIFT
= 0,
69 PLL_FRACDIV_MASK
= 0xffffff,
81 CLK_CORE_PLL_SEL_APLL
= 0,
82 CLK_CORE_PLL_SEL_GPLL
,
83 CLK_CORE_PLL_SEL_DPLL
,
84 CLK_CORE_PLL_SEL_NPLL
,
85 CLK_CORE_PLL_SEL_SHIFT
= 6,
86 CLK_CORE_PLL_SEL_MASK
= 3 << CLK_CORE_PLL_SEL_SHIFT
,
87 CLK_CORE_DIV_SHIFT
= 0,
88 CLK_CORE_DIV_MASK
= 0x1f,
91 ACLKM_CORE_DIV_SHIFT
= 4,
92 ACLKM_CORE_DIV_MASK
= 0x7 << ACLKM_CORE_DIV_SHIFT
,
93 PCLK_DBG_DIV_SHIFT
= 0,
94 PCLK_DBG_DIV_MASK
= 0xF << PCLK_DBG_DIV_SHIFT
,
97 ACLK_PERIHP_PLL_SEL_CPLL
= 0,
98 ACLK_PERIHP_PLL_SEL_GPLL
,
99 ACLK_PERIHP_PLL_SEL_HDMIPHY
,
100 ACLK_PERIHP_PLL_SEL_SHIFT
= 6,
101 ACLK_PERIHP_PLL_SEL_MASK
= 3 << ACLK_PERIHP_PLL_SEL_SHIFT
,
102 ACLK_PERIHP_DIV_CON_SHIFT
= 0,
103 ACLK_PERIHP_DIV_CON_MASK
= 0x1f,
106 PCLK_PERIHP_DIV_CON_SHIFT
= 4,
107 PCLK_PERIHP_DIV_CON_MASK
= 0x7 << PCLK_PERIHP_DIV_CON_SHIFT
,
108 HCLK_PERIHP_DIV_CON_SHIFT
= 0,
109 HCLK_PERIHP_DIV_CON_MASK
= 3 << HCLK_PERIHP_DIV_CON_SHIFT
,
112 CLK_TSADC_DIV_CON_SHIFT
= 0,
113 CLK_TSADC_DIV_CON_MASK
= 0x3ff,
116 CLK_SARADC_DIV_CON_SHIFT
= 0,
117 CLK_SARADC_DIV_CON_MASK
= 0x3ff << CLK_SARADC_DIV_CON_SHIFT
,
120 CLK_PWM_PLL_SEL_CPLL
= 0,
121 CLK_PWM_PLL_SEL_GPLL
,
122 CLK_PWM_PLL_SEL_SHIFT
= 15,
123 CLK_PWM_PLL_SEL_MASK
= 1 << CLK_PWM_PLL_SEL_SHIFT
,
124 CLK_PWM_DIV_CON_SHIFT
= 8,
125 CLK_PWM_DIV_CON_MASK
= 0x7f << CLK_PWM_DIV_CON_SHIFT
,
127 CLK_SPI_PLL_SEL_CPLL
= 0,
128 CLK_SPI_PLL_SEL_GPLL
,
129 CLK_SPI_PLL_SEL_SHIFT
= 7,
130 CLK_SPI_PLL_SEL_MASK
= 1 << CLK_SPI_PLL_SEL_SHIFT
,
131 CLK_SPI_DIV_CON_SHIFT
= 0,
132 CLK_SPI_DIV_CON_MASK
= 0x7f << CLK_SPI_DIV_CON_SHIFT
,
135 CLK_SDMMC_PLL_SEL_CPLL
= 0,
136 CLK_SDMMC_PLL_SEL_GPLL
,
137 CLK_SDMMC_PLL_SEL_24M
,
138 CLK_SDMMC_PLL_SEL_USBPHY
,
139 CLK_SDMMC_PLL_SHIFT
= 8,
140 CLK_SDMMC_PLL_MASK
= 0x3 << CLK_SDMMC_PLL_SHIFT
,
141 CLK_SDMMC_DIV_CON_SHIFT
= 0,
142 CLK_SDMMC_DIV_CON_MASK
= 0xff << CLK_SDMMC_DIV_CON_SHIFT
,
145 CLK_EMMC_PLL_SEL_CPLL
= 0,
146 CLK_EMMC_PLL_SEL_GPLL
,
147 CLK_EMMC_PLL_SEL_24M
,
148 CLK_EMMC_PLL_SEL_USBPHY
,
149 CLK_EMMC_PLL_SHIFT
= 8,
150 CLK_EMMC_PLL_MASK
= 0x3 << CLK_EMMC_PLL_SHIFT
,
151 CLK_EMMC_DIV_CON_SHIFT
= 0,
152 CLK_EMMC_DIV_CON_MASK
= 0xff << CLK_EMMC_DIV_CON_SHIFT
,
155 CLK_I2C_PLL_SEL_CPLL
= 0,
156 CLK_I2C_PLL_SEL_GPLL
,
157 CLK_I2C_DIV_CON_MASK
= 0x7f,
158 CLK_I2C_PLL_SEL_MASK
= 1,
159 CLK_I2C1_PLL_SEL_SHIFT
= 15,
160 CLK_I2C1_DIV_CON_SHIFT
= 8,
161 CLK_I2C0_PLL_SEL_SHIFT
= 7,
162 CLK_I2C0_DIV_CON_SHIFT
= 0,
165 CLK_I2C3_PLL_SEL_SHIFT
= 15,
166 CLK_I2C3_DIV_CON_SHIFT
= 8,
167 CLK_I2C2_PLL_SEL_SHIFT
= 7,
168 CLK_I2C2_DIV_CON_SHIFT
= 0,
171 #define VCO_MAX_KHZ (3200 * (MHz / KHz))
172 #define VCO_MIN_KHZ (800 * (MHz / KHz))
173 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
174 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
177 * the div restructions of pll in integer mode, these are defined in
178 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
180 #define PLL_DIV_MIN 16
181 #define PLL_DIV_MAX 3200
184 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
185 * Formulas also embedded within the Fractional PLL Verilog model:
186 * If DSMPD = 1 (DSM is disabled, "integer mode")
187 * FOUTVCO = FREF / REFDIV * FBDIV
188 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
190 * FOUTVCO = Fractional PLL non-divided output frequency
191 * FOUTPOSTDIV = Fractional PLL divided output frequency
192 * (output of second post divider)
193 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
194 * REFDIV = Fractional PLL input reference clock divider
195 * FBDIV = Integer value programmed into feedback divide
198 static void rkclk_set_pll(struct rk3328_cru
*cru
, enum rk_clk_id clk_id
,
199 const struct pll_div
*div
)
202 u32 mode_shift
, mode_mask
;
208 pll_con
= cru
->apll_con
;
209 mode_shift
= APLL_MODE_SHIFT
;
212 pll_con
= cru
->dpll_con
;
213 mode_shift
= DPLL_MODE_SHIFT
;
216 pll_con
= cru
->cpll_con
;
217 mode_shift
= CPLL_MODE_SHIFT
;
220 pll_con
= cru
->gpll_con
;
221 mode_shift
= GPLL_MODE_SHIFT
;
224 pll_con
= cru
->npll_con
;
225 mode_shift
= NPLL_MODE_SHIFT
;
230 mode_mask
= 1 << mode_shift
;
232 /* All 8 PLLs have same VCO and output frequency range restrictions. */
233 u32 vco_khz
= OSC_HZ
/ 1000 * div
->fbdiv
/ div
->refdiv
;
234 u32 output_khz
= vco_khz
/ div
->postdiv1
/ div
->postdiv2
;
236 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, \
237 postdiv2=%d, vco=%u khz, output=%u khz\n",
238 pll_con
, div
->fbdiv
, div
->refdiv
, div
->postdiv1
,
239 div
->postdiv2
, vco_khz
, output_khz
);
240 assert(vco_khz
>= VCO_MIN_KHZ
&& vco_khz
<= VCO_MAX_KHZ
&&
241 output_khz
>= OUTPUT_MIN_KHZ
&& output_khz
<= OUTPUT_MAX_KHZ
&&
242 div
->fbdiv
>= PLL_DIV_MIN
&& div
->fbdiv
<= PLL_DIV_MAX
);
245 * When power on or changing PLL setting,
246 * we must force PLL into slow mode to ensure output stable clock.
248 rk_clrsetreg(&cru
->mode_con
, mode_mask
, PLL_MODE_SLOW
<< mode_shift
);
250 /* use integer mode */
251 rk_clrsetreg(&pll_con
[1], PLL_DSMPD_MASK
,
252 PLL_INTEGER_MODE
<< PLL_DSMPD_SHIFT
);
254 rk_clrsetreg(&pll_con
[0],
255 PLL_FBDIV_MASK
| PLL_POSTDIV1_MASK
,
256 (div
->fbdiv
<< PLL_FBDIV_SHIFT
) |
257 (div
->postdiv1
<< PLL_POSTDIV1_SHIFT
));
258 rk_clrsetreg(&pll_con
[1],
259 PLL_POSTDIV2_MASK
| PLL_REFDIV_MASK
,
260 (div
->postdiv2
<< PLL_POSTDIV2_SHIFT
) |
261 (div
->refdiv
<< PLL_REFDIV_SHIFT
));
263 /* waiting for pll lock */
264 while (!(readl(&pll_con
[1]) & (1 << PLL_LOCK_STATUS_SHIFT
)))
267 /* pll enter normal mode */
268 rk_clrsetreg(&cru
->mode_con
, mode_mask
, PLL_MODE_NORM
<< mode_shift
);
271 static void rkclk_init(struct rk3328_cru
*cru
)
277 /* configure gpll cpll */
278 rkclk_set_pll(cru
, CLK_GENERAL
, &gpll_init_cfg
);
279 rkclk_set_pll(cru
, CLK_CODEC
, &cpll_init_cfg
);
281 /* configure perihp aclk, hclk, pclk */
282 aclk_div
= GPLL_HZ
/ PERIHP_ACLK_HZ
- 1;
283 hclk_div
= PERIHP_ACLK_HZ
/ PERIHP_HCLK_HZ
- 1;
284 pclk_div
= PERIHP_ACLK_HZ
/ PERIHP_PCLK_HZ
- 1;
286 rk_clrsetreg(&cru
->clksel_con
[28],
287 ACLK_PERIHP_PLL_SEL_MASK
| ACLK_PERIHP_DIV_CON_MASK
,
288 ACLK_PERIHP_PLL_SEL_GPLL
<< ACLK_PERIHP_PLL_SEL_SHIFT
|
289 aclk_div
<< ACLK_PERIHP_DIV_CON_SHIFT
);
290 rk_clrsetreg(&cru
->clksel_con
[29],
291 PCLK_PERIHP_DIV_CON_MASK
| HCLK_PERIHP_DIV_CON_MASK
,
292 pclk_div
<< PCLK_PERIHP_DIV_CON_SHIFT
|
293 hclk_div
<< HCLK_PERIHP_DIV_CON_SHIFT
);
296 void rk3328_configure_cpu(struct rk3328_cru
*cru
,
297 enum apll_frequencies apll_freq
)
303 rkclk_set_pll(cru
, CLK_ARM
, apll_cfgs
[apll_freq
]);
305 clk_core_div
= APLL_HZ
/ CLK_CORE_HZ
- 1;
306 aclkm_div
= APLL_HZ
/ ACLKM_CORE_HZ
/ (clk_core_div
+ 1) - 1;
307 pclk_dbg_div
= APLL_HZ
/ PCLK_DBG_HZ
/ (clk_core_div
+ 1) - 1;
309 rk_clrsetreg(&cru
->clksel_con
[0],
310 CLK_CORE_PLL_SEL_MASK
| CLK_CORE_DIV_MASK
,
311 CLK_CORE_PLL_SEL_APLL
<< CLK_CORE_PLL_SEL_SHIFT
|
312 clk_core_div
<< CLK_CORE_DIV_SHIFT
);
314 rk_clrsetreg(&cru
->clksel_con
[1],
315 PCLK_DBG_DIV_MASK
| ACLKM_CORE_DIV_MASK
,
316 pclk_dbg_div
<< PCLK_DBG_DIV_SHIFT
|
317 aclkm_div
<< ACLKM_CORE_DIV_SHIFT
);
321 static ulong
rk3328_i2c_get_clk(struct rk3328_cru
*cru
, ulong clk_id
)
327 con
= readl(&cru
->clksel_con
[34]);
328 div
= con
>> CLK_I2C0_DIV_CON_SHIFT
& CLK_I2C_DIV_CON_MASK
;
331 con
= readl(&cru
->clksel_con
[34]);
332 div
= con
>> CLK_I2C1_DIV_CON_SHIFT
& CLK_I2C_DIV_CON_MASK
;
335 con
= readl(&cru
->clksel_con
[35]);
336 div
= con
>> CLK_I2C2_DIV_CON_SHIFT
& CLK_I2C_DIV_CON_MASK
;
339 con
= readl(&cru
->clksel_con
[35]);
340 div
= con
>> CLK_I2C3_DIV_CON_SHIFT
& CLK_I2C_DIV_CON_MASK
;
343 printf("do not support this i2c bus\n");
347 return DIV_TO_RATE(GPLL_HZ
, div
);
350 static ulong
rk3328_i2c_set_clk(struct rk3328_cru
*cru
, ulong clk_id
, uint hz
)
354 src_clk_div
= GPLL_HZ
/ hz
;
355 assert(src_clk_div
- 1 < 127);
359 rk_clrsetreg(&cru
->clksel_con
[34],
360 CLK_I2C_DIV_CON_MASK
<< CLK_I2C0_DIV_CON_SHIFT
|
361 CLK_I2C_PLL_SEL_MASK
<< CLK_I2C0_PLL_SEL_SHIFT
,
362 (src_clk_div
- 1) << CLK_I2C0_DIV_CON_SHIFT
|
363 CLK_I2C_PLL_SEL_GPLL
<< CLK_I2C0_PLL_SEL_SHIFT
);
366 rk_clrsetreg(&cru
->clksel_con
[34],
367 CLK_I2C_DIV_CON_MASK
<< CLK_I2C1_DIV_CON_SHIFT
|
368 CLK_I2C_PLL_SEL_MASK
<< CLK_I2C1_PLL_SEL_SHIFT
,
369 (src_clk_div
- 1) << CLK_I2C1_DIV_CON_SHIFT
|
370 CLK_I2C_PLL_SEL_GPLL
<< CLK_I2C1_PLL_SEL_SHIFT
);
373 rk_clrsetreg(&cru
->clksel_con
[35],
374 CLK_I2C_DIV_CON_MASK
<< CLK_I2C2_DIV_CON_SHIFT
|
375 CLK_I2C_PLL_SEL_MASK
<< CLK_I2C2_PLL_SEL_SHIFT
,
376 (src_clk_div
- 1) << CLK_I2C2_DIV_CON_SHIFT
|
377 CLK_I2C_PLL_SEL_GPLL
<< CLK_I2C2_PLL_SEL_SHIFT
);
380 rk_clrsetreg(&cru
->clksel_con
[35],
381 CLK_I2C_DIV_CON_MASK
<< CLK_I2C3_DIV_CON_SHIFT
|
382 CLK_I2C_PLL_SEL_MASK
<< CLK_I2C3_PLL_SEL_SHIFT
,
383 (src_clk_div
- 1) << CLK_I2C3_DIV_CON_SHIFT
|
384 CLK_I2C_PLL_SEL_GPLL
<< CLK_I2C3_PLL_SEL_SHIFT
);
387 printf("do not support this i2c bus\n");
391 return DIV_TO_RATE(GPLL_HZ
, src_clk_div
);
394 static ulong
rk3328_mmc_get_clk(struct rk3328_cru
*cru
, uint clk_id
)
396 u32 div
, con
, con_id
;
410 con
= readl(&cru
->clksel_con
[con_id
]);
411 div
= (con
& CLK_EMMC_DIV_CON_MASK
) >> CLK_EMMC_DIV_CON_SHIFT
;
413 if ((con
& CLK_EMMC_PLL_MASK
) >> CLK_EMMC_PLL_SHIFT
414 == CLK_EMMC_PLL_SEL_24M
)
415 return DIV_TO_RATE(OSC_HZ
, div
);
417 return DIV_TO_RATE(GPLL_HZ
, div
);
420 static ulong
rk3328_mmc_set_clk(struct rk3328_cru
*cru
,
421 ulong clk_id
, ulong set_rate
)
438 /* Select clk_sdmmc/emmc source from GPLL by default */
439 src_clk_div
= GPLL_HZ
/ set_rate
;
441 if (src_clk_div
> 127) {
442 /* use 24MHz source for 400KHz clock */
443 src_clk_div
= OSC_HZ
/ set_rate
;
444 rk_clrsetreg(&cru
->clksel_con
[con_id
],
445 CLK_EMMC_PLL_MASK
| CLK_EMMC_DIV_CON_MASK
,
446 CLK_EMMC_PLL_SEL_24M
<< CLK_EMMC_PLL_SHIFT
|
447 (src_clk_div
- 1) << CLK_EMMC_DIV_CON_SHIFT
);
449 rk_clrsetreg(&cru
->clksel_con
[con_id
],
450 CLK_EMMC_PLL_MASK
| CLK_EMMC_DIV_CON_MASK
,
451 CLK_EMMC_PLL_SEL_GPLL
<< CLK_EMMC_PLL_SHIFT
|
452 (src_clk_div
- 1) << CLK_EMMC_DIV_CON_SHIFT
);
455 return rk3328_mmc_get_clk(cru
, clk_id
);
458 static ulong
rk3328_pwm_get_clk(struct rk3328_cru
*cru
)
462 con
= readl(&cru
->clksel_con
[24]);
463 div
= (con
& CLK_PWM_DIV_CON_MASK
) >> CLK_PWM_DIV_CON_SHIFT
;
465 return DIV_TO_RATE(GPLL_HZ
, div
);
468 static ulong
rk3328_pwm_set_clk(struct rk3328_cru
*cru
, uint hz
)
470 u32 div
= GPLL_HZ
/ hz
;
472 rk_clrsetreg(&cru
->clksel_con
[24],
473 CLK_PWM_PLL_SEL_MASK
| CLK_PWM_DIV_CON_MASK
,
474 CLK_PWM_PLL_SEL_GPLL
<< CLK_PWM_PLL_SEL_SHIFT
|
475 (div
- 1) << CLK_PWM_DIV_CON_SHIFT
);
477 return DIV_TO_RATE(GPLL_HZ
, div
);
480 static ulong
rk3328_clk_get_rate(struct clk
*clk
)
482 struct rk3328_clk_priv
*priv
= dev_get_priv(clk
->dev
);
492 rate
= rk3328_mmc_get_clk(priv
->cru
, clk
->id
);
498 rate
= rk3328_i2c_get_clk(priv
->cru
, clk
->id
);
501 rate
= rk3328_pwm_get_clk(priv
->cru
);
510 static ulong
rk3328_clk_set_rate(struct clk
*clk
, ulong rate
)
512 struct rk3328_clk_priv
*priv
= dev_get_priv(clk
->dev
);
522 ret
= rk3328_mmc_set_clk(priv
->cru
, clk
->id
, rate
);
528 ret
= rk3328_i2c_set_clk(priv
->cru
, clk
->id
, rate
);
531 ret
= rk3328_pwm_set_clk(priv
->cru
, rate
);
540 static struct clk_ops rk3328_clk_ops
= {
541 .get_rate
= rk3328_clk_get_rate
,
542 .set_rate
= rk3328_clk_set_rate
,
545 static int rk3328_clk_probe(struct udevice
*dev
)
547 struct rk3328_clk_priv
*priv
= dev_get_priv(dev
);
549 rkclk_init(priv
->cru
);
554 static int rk3328_clk_ofdata_to_platdata(struct udevice
*dev
)
556 struct rk3328_clk_priv
*priv
= dev_get_priv(dev
);
558 priv
->cru
= (struct rk3328_cru
*)devfdt_get_addr(dev
);
563 static int rk3328_clk_bind(struct udevice
*dev
)
567 /* The reset driver does not have a device node, so bind it here */
568 ret
= device_bind_driver(gd
->dm_root
, "rk3328_sysreset", "reset", &dev
);
570 printf("Warning: No RK3328 reset driver: ret=%d\n", ret
);
575 static const struct udevice_id rk3328_clk_ids
[] = {
576 { .compatible
= "rockchip,rk3328-cru" },
580 U_BOOT_DRIVER(rockchip_rk3328_cru
) = {
581 .name
= "rockchip_rk3328_cru",
583 .of_match
= rk3328_clk_ids
,
584 .priv_auto_alloc_size
= sizeof(struct rk3328_clk_priv
),
585 .ofdata_to_platdata
= rk3328_clk_ofdata_to_platdata
,
586 .ops
= &rk3328_clk_ops
,
587 .bind
= rk3328_clk_bind
,
588 .probe
= rk3328_clk_probe
,