2 * (C) Copyright 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/cru_rk3399.h>
15 #include <asm/arch/hardware.h>
17 #include <dt-bindings/clock/rk3399-cru.h>
19 DECLARE_GLOBAL_DATA_PTR
;
21 struct rk3399_clk_priv
{
22 struct rk3399_cru
*cru
;
26 struct rk3399_pmuclk_priv
{
27 struct rk3399_pmucru
*pmucru
;
38 #define RATE_TO_DIV(input_rate, output_rate) \
39 ((input_rate) / (output_rate) - 1);
40 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
42 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
44 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
45 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
47 static const struct pll_div gpll_init_cfg
= PLL_DIVISORS(GPLL_HZ
, 2, 2, 1);
48 static const struct pll_div cpll_init_cfg
= PLL_DIVISORS(CPLL_HZ
, 1, 2, 2);
49 static const struct pll_div ppll_init_cfg
= PLL_DIVISORS(PPLL_HZ
, 2, 2, 1);
51 static const struct pll_div apll_l_1600_cfg
= PLL_DIVISORS(1600*MHz
, 3, 1, 1);
52 static const struct pll_div apll_l_600_cfg
= PLL_DIVISORS(600*MHz
, 1, 2, 1);
54 static const struct pll_div
*apll_l_cfgs
[] = {
55 [APLL_L_1600_MHZ
] = &apll_l_1600_cfg
,
56 [APLL_L_600_MHZ
] = &apll_l_600_cfg
,
61 PLL_FBDIV_MASK
= 0xfff,
65 PLL_POSTDIV2_SHIFT
= 12,
66 PLL_POSTDIV2_MASK
= 0x7 << PLL_POSTDIV2_SHIFT
,
67 PLL_POSTDIV1_SHIFT
= 8,
68 PLL_POSTDIV1_MASK
= 0x7 << PLL_POSTDIV1_SHIFT
,
69 PLL_REFDIV_MASK
= 0x3f,
73 PLL_LOCK_STATUS_SHIFT
= 31,
74 PLL_LOCK_STATUS_MASK
= 1 << PLL_LOCK_STATUS_SHIFT
,
75 PLL_FRACDIV_MASK
= 0xffffff,
76 PLL_FRACDIV_SHIFT
= 0,
80 PLL_MODE_MASK
= 3 << PLL_MODE_SHIFT
,
85 PLL_DSMPD_MASK
= 1 << PLL_DSMPD_SHIFT
,
88 /* PMUCRU_CLKSEL_CON0 */
89 PMU_PCLK_DIV_CON_MASK
= 0x1f,
90 PMU_PCLK_DIV_CON_SHIFT
= 0,
92 /* PMUCRU_CLKSEL_CON1 */
93 SPI3_PLL_SEL_SHIFT
= 7,
94 SPI3_PLL_SEL_MASK
= 1 << SPI3_PLL_SEL_SHIFT
,
96 SPI3_PLL_SEL_PPLL
= 1,
97 SPI3_DIV_CON_SHIFT
= 0x0,
98 SPI3_DIV_CON_MASK
= 0x7f,
100 /* PMUCRU_CLKSEL_CON2 */
101 I2C_DIV_CON_MASK
= 0x7f,
102 CLK_I2C8_DIV_CON_SHIFT
= 8,
103 CLK_I2C0_DIV_CON_SHIFT
= 0,
105 /* PMUCRU_CLKSEL_CON3 */
106 CLK_I2C4_DIV_CON_SHIFT
= 0,
109 ACLKM_CORE_L_DIV_CON_SHIFT
= 8,
110 ACLKM_CORE_L_DIV_CON_MASK
= 0x1f << ACLKM_CORE_L_DIV_CON_SHIFT
,
111 CLK_CORE_L_PLL_SEL_SHIFT
= 6,
112 CLK_CORE_L_PLL_SEL_MASK
= 3 << CLK_CORE_L_PLL_SEL_SHIFT
,
113 CLK_CORE_L_PLL_SEL_ALPLL
= 0x0,
114 CLK_CORE_L_PLL_SEL_ABPLL
= 0x1,
115 CLK_CORE_L_PLL_SEL_DPLL
= 0x10,
116 CLK_CORE_L_PLL_SEL_GPLL
= 0x11,
117 CLK_CORE_L_DIV_MASK
= 0x1f,
118 CLK_CORE_L_DIV_SHIFT
= 0,
121 PCLK_DBG_L_DIV_SHIFT
= 0x8,
122 PCLK_DBG_L_DIV_MASK
= 0x1f << PCLK_DBG_L_DIV_SHIFT
,
123 ATCLK_CORE_L_DIV_SHIFT
= 0,
124 ATCLK_CORE_L_DIV_MASK
= 0x1f << ATCLK_CORE_L_DIV_SHIFT
,
127 PCLK_PERIHP_DIV_CON_SHIFT
= 12,
128 PCLK_PERIHP_DIV_CON_MASK
= 0x7 << PCLK_PERIHP_DIV_CON_SHIFT
,
129 HCLK_PERIHP_DIV_CON_SHIFT
= 8,
130 HCLK_PERIHP_DIV_CON_MASK
= 3 << HCLK_PERIHP_DIV_CON_SHIFT
,
131 ACLK_PERIHP_PLL_SEL_SHIFT
= 7,
132 ACLK_PERIHP_PLL_SEL_MASK
= 1 << ACLK_PERIHP_PLL_SEL_SHIFT
,
133 ACLK_PERIHP_PLL_SEL_CPLL
= 0,
134 ACLK_PERIHP_PLL_SEL_GPLL
= 1,
135 ACLK_PERIHP_DIV_CON_SHIFT
= 0,
136 ACLK_PERIHP_DIV_CON_MASK
= 0x1f,
139 ACLK_EMMC_PLL_SEL_SHIFT
= 7,
140 ACLK_EMMC_PLL_SEL_MASK
= 0x1 << ACLK_EMMC_PLL_SEL_SHIFT
,
141 ACLK_EMMC_PLL_SEL_GPLL
= 0x1,
142 ACLK_EMMC_DIV_CON_SHIFT
= 0,
143 ACLK_EMMC_DIV_CON_MASK
= 0x1f,
146 CLK_EMMC_PLL_SHIFT
= 8,
147 CLK_EMMC_PLL_MASK
= 0x7 << CLK_EMMC_PLL_SHIFT
,
148 CLK_EMMC_PLL_SEL_GPLL
= 0x1,
149 CLK_EMMC_PLL_SEL_24M
= 0x5,
150 CLK_EMMC_DIV_CON_SHIFT
= 0,
151 CLK_EMMC_DIV_CON_MASK
= 0x7f << CLK_EMMC_DIV_CON_SHIFT
,
154 PCLK_PERILP0_DIV_CON_SHIFT
= 12,
155 PCLK_PERILP0_DIV_CON_MASK
= 0x7 << PCLK_PERILP0_DIV_CON_SHIFT
,
156 HCLK_PERILP0_DIV_CON_SHIFT
= 8,
157 HCLK_PERILP0_DIV_CON_MASK
= 3 << HCLK_PERILP0_DIV_CON_SHIFT
,
158 ACLK_PERILP0_PLL_SEL_SHIFT
= 7,
159 ACLK_PERILP0_PLL_SEL_MASK
= 1 << ACLK_PERILP0_PLL_SEL_SHIFT
,
160 ACLK_PERILP0_PLL_SEL_CPLL
= 0,
161 ACLK_PERILP0_PLL_SEL_GPLL
= 1,
162 ACLK_PERILP0_DIV_CON_SHIFT
= 0,
163 ACLK_PERILP0_DIV_CON_MASK
= 0x1f,
166 PCLK_PERILP1_DIV_CON_SHIFT
= 8,
167 PCLK_PERILP1_DIV_CON_MASK
= 0x7 << PCLK_PERILP1_DIV_CON_SHIFT
,
168 HCLK_PERILP1_PLL_SEL_SHIFT
= 7,
169 HCLK_PERILP1_PLL_SEL_MASK
= 1 << HCLK_PERILP1_PLL_SEL_SHIFT
,
170 HCLK_PERILP1_PLL_SEL_CPLL
= 0,
171 HCLK_PERILP1_PLL_SEL_GPLL
= 1,
172 HCLK_PERILP1_DIV_CON_SHIFT
= 0,
173 HCLK_PERILP1_DIV_CON_MASK
= 0x1f,
176 CLK_SARADC_DIV_CON_SHIFT
= 8,
177 CLK_SARADC_DIV_CON_MASK
= 0xff << CLK_SARADC_DIV_CON_SHIFT
,
180 CLK_TSADC_SEL_X24M
= 0x0,
181 CLK_TSADC_SEL_SHIFT
= 15,
182 CLK_TSADC_SEL_MASK
= 1 << CLK_TSADC_SEL_SHIFT
,
183 CLK_TSADC_DIV_CON_SHIFT
= 0,
184 CLK_TSADC_DIV_CON_MASK
= 0x3ff,
186 /* CLKSEL_CON47 & CLKSEL_CON48 */
187 ACLK_VOP_PLL_SEL_SHIFT
= 6,
188 ACLK_VOP_PLL_SEL_MASK
= 0x3 << ACLK_VOP_PLL_SEL_SHIFT
,
189 ACLK_VOP_PLL_SEL_CPLL
= 0x1,
190 ACLK_VOP_DIV_CON_SHIFT
= 0,
191 ACLK_VOP_DIV_CON_MASK
= 0x1f << ACLK_VOP_DIV_CON_SHIFT
,
193 /* CLKSEL_CON49 & CLKSEL_CON50 */
194 DCLK_VOP_DCLK_SEL_SHIFT
= 11,
195 DCLK_VOP_DCLK_SEL_MASK
= 1 << DCLK_VOP_DCLK_SEL_SHIFT
,
196 DCLK_VOP_DCLK_SEL_DIVOUT
= 0,
197 DCLK_VOP_PLL_SEL_SHIFT
= 8,
198 DCLK_VOP_PLL_SEL_MASK
= 3 << DCLK_VOP_PLL_SEL_SHIFT
,
199 DCLK_VOP_PLL_SEL_VPLL
= 0,
200 DCLK_VOP_DIV_CON_MASK
= 0xff,
201 DCLK_VOP_DIV_CON_SHIFT
= 0,
204 CLK_SPI_PLL_SEL_MASK
= 1,
205 CLK_SPI_PLL_SEL_CPLL
= 0,
206 CLK_SPI_PLL_SEL_GPLL
= 1,
207 CLK_SPI_PLL_DIV_CON_MASK
= 0x7f,
208 CLK_SPI5_PLL_DIV_CON_SHIFT
= 8,
209 CLK_SPI5_PLL_SEL_SHIFT
= 15,
212 CLK_SPI1_PLL_SEL_SHIFT
= 15,
213 CLK_SPI1_PLL_DIV_CON_SHIFT
= 8,
214 CLK_SPI0_PLL_SEL_SHIFT
= 7,
215 CLK_SPI0_PLL_DIV_CON_SHIFT
= 0,
218 CLK_SPI4_PLL_SEL_SHIFT
= 15,
219 CLK_SPI4_PLL_DIV_CON_SHIFT
= 8,
220 CLK_SPI2_PLL_SEL_SHIFT
= 7,
221 CLK_SPI2_PLL_DIV_CON_SHIFT
= 0,
224 CLK_I2C_PLL_SEL_MASK
= 1,
225 CLK_I2C_PLL_SEL_CPLL
= 0,
226 CLK_I2C_PLL_SEL_GPLL
= 1,
227 CLK_I2C5_PLL_SEL_SHIFT
= 15,
228 CLK_I2C5_DIV_CON_SHIFT
= 8,
229 CLK_I2C1_PLL_SEL_SHIFT
= 7,
230 CLK_I2C1_DIV_CON_SHIFT
= 0,
233 CLK_I2C6_PLL_SEL_SHIFT
= 15,
234 CLK_I2C6_DIV_CON_SHIFT
= 8,
235 CLK_I2C2_PLL_SEL_SHIFT
= 7,
236 CLK_I2C2_DIV_CON_SHIFT
= 0,
239 CLK_I2C7_PLL_SEL_SHIFT
= 15,
240 CLK_I2C7_DIV_CON_SHIFT
= 8,
241 CLK_I2C3_PLL_SEL_SHIFT
= 7,
242 CLK_I2C3_DIV_CON_SHIFT
= 0,
244 /* CRU_SOFTRST_CON4 */
245 RESETN_DDR0_REQ_SHIFT
= 8,
246 RESETN_DDR0_REQ_MASK
= 1 << RESETN_DDR0_REQ_SHIFT
,
247 RESETN_DDRPHY0_REQ_SHIFT
= 9,
248 RESETN_DDRPHY0_REQ_MASK
= 1 << RESETN_DDRPHY0_REQ_SHIFT
,
249 RESETN_DDR1_REQ_SHIFT
= 12,
250 RESETN_DDR1_REQ_MASK
= 1 << RESETN_DDR1_REQ_SHIFT
,
251 RESETN_DDRPHY1_REQ_SHIFT
= 13,
252 RESETN_DDRPHY1_REQ_MASK
= 1 << RESETN_DDRPHY1_REQ_SHIFT
,
255 #define VCO_MAX_KHZ (3200 * (MHz / KHz))
256 #define VCO_MIN_KHZ (800 * (MHz / KHz))
257 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
258 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
261 * the div restructions of pll in integer mode, these are defined in
262 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
264 #define PLL_DIV_MIN 16
265 #define PLL_DIV_MAX 3200
268 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
269 * Formulas also embedded within the Fractional PLL Verilog model:
270 * If DSMPD = 1 (DSM is disabled, "integer mode")
271 * FOUTVCO = FREF / REFDIV * FBDIV
272 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
274 * FOUTVCO = Fractional PLL non-divided output frequency
275 * FOUTPOSTDIV = Fractional PLL divided output frequency
276 * (output of second post divider)
277 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
278 * REFDIV = Fractional PLL input reference clock divider
279 * FBDIV = Integer value programmed into feedback divide
282 static void rkclk_set_pll(u32
*pll_con
, const struct pll_div
*div
)
284 /* All 8 PLLs have same VCO and output frequency range restrictions. */
285 u32 vco_khz
= OSC_HZ
/ 1000 * div
->fbdiv
/ div
->refdiv
;
286 u32 output_khz
= vco_khz
/ div
->postdiv1
/ div
->postdiv2
;
288 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, "
289 "postdiv2=%d, vco=%u khz, output=%u khz\n",
290 pll_con
, div
->fbdiv
, div
->refdiv
, div
->postdiv1
,
291 div
->postdiv2
, vco_khz
, output_khz
);
292 assert(vco_khz
>= VCO_MIN_KHZ
&& vco_khz
<= VCO_MAX_KHZ
&&
293 output_khz
>= OUTPUT_MIN_KHZ
&& output_khz
<= OUTPUT_MAX_KHZ
&&
294 div
->fbdiv
>= PLL_DIV_MIN
&& div
->fbdiv
<= PLL_DIV_MAX
);
297 * When power on or changing PLL setting,
298 * we must force PLL into slow mode to ensure output stable clock.
300 rk_clrsetreg(&pll_con
[3], PLL_MODE_MASK
,
301 PLL_MODE_SLOW
<< PLL_MODE_SHIFT
);
303 /* use integer mode */
304 rk_clrsetreg(&pll_con
[3], PLL_DSMPD_MASK
,
305 PLL_INTEGER_MODE
<< PLL_DSMPD_SHIFT
);
307 rk_clrsetreg(&pll_con
[0], PLL_FBDIV_MASK
,
308 div
->fbdiv
<< PLL_FBDIV_SHIFT
);
309 rk_clrsetreg(&pll_con
[1],
310 PLL_POSTDIV2_MASK
| PLL_POSTDIV1_MASK
|
311 PLL_REFDIV_MASK
| PLL_REFDIV_SHIFT
,
312 (div
->postdiv2
<< PLL_POSTDIV2_SHIFT
) |
313 (div
->postdiv1
<< PLL_POSTDIV1_SHIFT
) |
314 (div
->refdiv
<< PLL_REFDIV_SHIFT
));
316 /* waiting for pll lock */
317 while (!(readl(&pll_con
[2]) & (1 << PLL_LOCK_STATUS_SHIFT
)))
320 /* pll enter normal mode */
321 rk_clrsetreg(&pll_con
[3], PLL_MODE_MASK
,
322 PLL_MODE_NORM
<< PLL_MODE_SHIFT
);
325 static int pll_para_config(u32 freq_hz
, struct pll_div
*div
)
327 u32 ref_khz
= OSC_HZ
/ KHz
, refdiv
, fbdiv
= 0;
328 u32 postdiv1
, postdiv2
= 1;
330 u32 diff_khz
, best_diff_khz
;
331 const u32 max_refdiv
= 63, max_fbdiv
= 3200, min_fbdiv
= 16;
332 const u32 max_postdiv1
= 7, max_postdiv2
= 7;
334 u32 freq_khz
= freq_hz
/ KHz
;
337 printf("%s: the frequency can't be 0 Hz\n", __func__
);
341 postdiv1
= DIV_ROUND_UP(VCO_MIN_KHZ
, freq_khz
);
342 if (postdiv1
> max_postdiv1
) {
343 postdiv2
= DIV_ROUND_UP(postdiv1
, max_postdiv1
);
344 postdiv1
= DIV_ROUND_UP(postdiv1
, postdiv2
);
347 vco_khz
= freq_khz
* postdiv1
* postdiv2
;
349 if (vco_khz
< VCO_MIN_KHZ
|| vco_khz
> VCO_MAX_KHZ
||
350 postdiv2
> max_postdiv2
) {
351 printf("%s: Cannot find out a supported VCO"
352 " for Frequency (%uHz).\n", __func__
, freq_hz
);
356 div
->postdiv1
= postdiv1
;
357 div
->postdiv2
= postdiv2
;
359 best_diff_khz
= vco_khz
;
360 for (refdiv
= 1; refdiv
< max_refdiv
&& best_diff_khz
; refdiv
++) {
361 fref_khz
= ref_khz
/ refdiv
;
363 fbdiv
= vco_khz
/ fref_khz
;
364 if ((fbdiv
>= max_fbdiv
) || (fbdiv
<= min_fbdiv
))
366 diff_khz
= vco_khz
- fbdiv
* fref_khz
;
367 if (fbdiv
+ 1 < max_fbdiv
&& diff_khz
> fref_khz
/ 2) {
369 diff_khz
= fref_khz
- diff_khz
;
372 if (diff_khz
>= best_diff_khz
)
375 best_diff_khz
= diff_khz
;
376 div
->refdiv
= refdiv
;
380 if (best_diff_khz
> 4 * (MHz
/KHz
)) {
381 printf("%s: Failed to match output frequency %u, "
382 "difference is %u Hz,exceed 4MHZ\n", __func__
, freq_hz
,
383 best_diff_khz
* KHz
);
389 static void rkclk_init(struct rk3399_cru
*cru
)
396 * some cru registers changed by bootrom, we'd better reset them to
397 * reset/default values described in TRM to avoid confusion in kernel.
398 * Please consider these three lines as a fix of bootrom bug.
400 rk_clrsetreg(&cru
->clksel_con
[12], 0xffff, 0x4101);
401 rk_clrsetreg(&cru
->clksel_con
[19], 0xffff, 0x033f);
402 rk_clrsetreg(&cru
->clksel_con
[56], 0x0003, 0x0003);
404 /* configure gpll cpll */
405 rkclk_set_pll(&cru
->gpll_con
[0], &gpll_init_cfg
);
406 rkclk_set_pll(&cru
->cpll_con
[0], &cpll_init_cfg
);
408 /* configure perihp aclk, hclk, pclk */
409 aclk_div
= GPLL_HZ
/ PERIHP_ACLK_HZ
- 1;
410 assert((aclk_div
+ 1) * PERIHP_ACLK_HZ
== GPLL_HZ
&& aclk_div
< 0x1f);
412 hclk_div
= PERIHP_ACLK_HZ
/ PERIHP_HCLK_HZ
- 1;
413 assert((hclk_div
+ 1) * PERIHP_HCLK_HZ
==
414 PERIHP_ACLK_HZ
&& (hclk_div
< 0x4));
416 pclk_div
= PERIHP_ACLK_HZ
/ PERIHP_PCLK_HZ
- 1;
417 assert((pclk_div
+ 1) * PERIHP_PCLK_HZ
==
418 PERIHP_ACLK_HZ
&& (pclk_div
< 0x7));
420 rk_clrsetreg(&cru
->clksel_con
[14],
421 PCLK_PERIHP_DIV_CON_MASK
| HCLK_PERIHP_DIV_CON_MASK
|
422 ACLK_PERIHP_PLL_SEL_MASK
| ACLK_PERIHP_DIV_CON_MASK
,
423 pclk_div
<< PCLK_PERIHP_DIV_CON_SHIFT
|
424 hclk_div
<< HCLK_PERIHP_DIV_CON_SHIFT
|
425 ACLK_PERIHP_PLL_SEL_GPLL
<< ACLK_PERIHP_PLL_SEL_SHIFT
|
426 aclk_div
<< ACLK_PERIHP_DIV_CON_SHIFT
);
428 /* configure perilp0 aclk, hclk, pclk */
429 aclk_div
= GPLL_HZ
/ PERILP0_ACLK_HZ
- 1;
430 assert((aclk_div
+ 1) * PERILP0_ACLK_HZ
== GPLL_HZ
&& aclk_div
< 0x1f);
432 hclk_div
= PERILP0_ACLK_HZ
/ PERILP0_HCLK_HZ
- 1;
433 assert((hclk_div
+ 1) * PERILP0_HCLK_HZ
==
434 PERILP0_ACLK_HZ
&& (hclk_div
< 0x4));
436 pclk_div
= PERILP0_ACLK_HZ
/ PERILP0_PCLK_HZ
- 1;
437 assert((pclk_div
+ 1) * PERILP0_PCLK_HZ
==
438 PERILP0_ACLK_HZ
&& (pclk_div
< 0x7));
440 rk_clrsetreg(&cru
->clksel_con
[23],
441 PCLK_PERILP0_DIV_CON_MASK
| HCLK_PERILP0_DIV_CON_MASK
|
442 ACLK_PERILP0_PLL_SEL_MASK
| ACLK_PERILP0_DIV_CON_MASK
,
443 pclk_div
<< PCLK_PERILP0_DIV_CON_SHIFT
|
444 hclk_div
<< HCLK_PERILP0_DIV_CON_SHIFT
|
445 ACLK_PERILP0_PLL_SEL_GPLL
<< ACLK_PERILP0_PLL_SEL_SHIFT
|
446 aclk_div
<< ACLK_PERILP0_DIV_CON_SHIFT
);
448 /* perilp1 hclk select gpll as source */
449 hclk_div
= GPLL_HZ
/ PERILP1_HCLK_HZ
- 1;
450 assert((hclk_div
+ 1) * PERILP1_HCLK_HZ
==
451 GPLL_HZ
&& (hclk_div
< 0x1f));
453 pclk_div
= PERILP1_HCLK_HZ
/ PERILP1_HCLK_HZ
- 1;
454 assert((pclk_div
+ 1) * PERILP1_HCLK_HZ
==
455 PERILP1_HCLK_HZ
&& (hclk_div
< 0x7));
457 rk_clrsetreg(&cru
->clksel_con
[25],
458 PCLK_PERILP1_DIV_CON_MASK
| HCLK_PERILP1_DIV_CON_MASK
|
459 HCLK_PERILP1_PLL_SEL_MASK
,
460 pclk_div
<< PCLK_PERILP1_DIV_CON_SHIFT
|
461 hclk_div
<< HCLK_PERILP1_DIV_CON_SHIFT
|
462 HCLK_PERILP1_PLL_SEL_GPLL
<< HCLK_PERILP1_PLL_SEL_SHIFT
);
465 void rk3399_configure_cpu(struct rk3399_cru
*cru
,
466 enum apll_l_frequencies apll_l_freq
)
472 rkclk_set_pll(&cru
->apll_l_con
[0], apll_l_cfgs
[apll_l_freq
]);
474 aclkm_div
= APLL_HZ
/ ACLKM_CORE_HZ
- 1;
475 assert((aclkm_div
+ 1) * ACLKM_CORE_HZ
== APLL_HZ
&&
478 pclk_dbg_div
= APLL_HZ
/ PCLK_DBG_HZ
- 1;
479 assert((pclk_dbg_div
+ 1) * PCLK_DBG_HZ
== APLL_HZ
&&
480 pclk_dbg_div
< 0x1f);
482 atclk_div
= APLL_HZ
/ ATCLK_CORE_HZ
- 1;
483 assert((atclk_div
+ 1) * ATCLK_CORE_HZ
== APLL_HZ
&&
486 rk_clrsetreg(&cru
->clksel_con
[0],
487 ACLKM_CORE_L_DIV_CON_MASK
| CLK_CORE_L_PLL_SEL_MASK
|
489 aclkm_div
<< ACLKM_CORE_L_DIV_CON_SHIFT
|
490 CLK_CORE_L_PLL_SEL_ALPLL
<< CLK_CORE_L_PLL_SEL_SHIFT
|
491 0 << CLK_CORE_L_DIV_SHIFT
);
493 rk_clrsetreg(&cru
->clksel_con
[1],
494 PCLK_DBG_L_DIV_MASK
| ATCLK_CORE_L_DIV_MASK
,
495 pclk_dbg_div
<< PCLK_DBG_L_DIV_SHIFT
|
496 atclk_div
<< ATCLK_CORE_L_DIV_SHIFT
);
498 #define I2C_CLK_REG_MASK(bus) \
499 (I2C_DIV_CON_MASK << \
500 CLK_I2C ##bus## _DIV_CON_SHIFT | \
501 CLK_I2C_PLL_SEL_MASK << \
502 CLK_I2C ##bus## _PLL_SEL_SHIFT)
504 #define I2C_CLK_REG_VALUE(bus, clk_div) \
506 CLK_I2C ##bus## _DIV_CON_SHIFT | \
507 CLK_I2C_PLL_SEL_GPLL << \
508 CLK_I2C ##bus## _PLL_SEL_SHIFT)
510 #define I2C_CLK_DIV_VALUE(con, bus) \
511 (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \
514 #define I2C_PMUCLK_REG_MASK(bus) \
515 (I2C_DIV_CON_MASK << \
516 CLK_I2C ##bus## _DIV_CON_SHIFT)
518 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
520 CLK_I2C ##bus## _DIV_CON_SHIFT)
522 static ulong
rk3399_i2c_get_clk(struct rk3399_cru
*cru
, ulong clk_id
)
528 con
= readl(&cru
->clksel_con
[61]);
529 div
= I2C_CLK_DIV_VALUE(con
, 1);
532 con
= readl(&cru
->clksel_con
[62]);
533 div
= I2C_CLK_DIV_VALUE(con
, 2);
536 con
= readl(&cru
->clksel_con
[63]);
537 div
= I2C_CLK_DIV_VALUE(con
, 3);
540 con
= readl(&cru
->clksel_con
[61]);
541 div
= I2C_CLK_DIV_VALUE(con
, 5);
544 con
= readl(&cru
->clksel_con
[62]);
545 div
= I2C_CLK_DIV_VALUE(con
, 6);
548 con
= readl(&cru
->clksel_con
[63]);
549 div
= I2C_CLK_DIV_VALUE(con
, 7);
552 printf("do not support this i2c bus\n");
556 return DIV_TO_RATE(GPLL_HZ
, div
);
559 static ulong
rk3399_i2c_set_clk(struct rk3399_cru
*cru
, ulong clk_id
, uint hz
)
563 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/
564 src_clk_div
= GPLL_HZ
/ hz
;
565 assert(src_clk_div
- 1 < 127);
569 rk_clrsetreg(&cru
->clksel_con
[61], I2C_CLK_REG_MASK(1),
570 I2C_CLK_REG_VALUE(1, src_clk_div
));
573 rk_clrsetreg(&cru
->clksel_con
[62], I2C_CLK_REG_MASK(2),
574 I2C_CLK_REG_VALUE(2, src_clk_div
));
577 rk_clrsetreg(&cru
->clksel_con
[63], I2C_CLK_REG_MASK(3),
578 I2C_CLK_REG_VALUE(3, src_clk_div
));
581 rk_clrsetreg(&cru
->clksel_con
[61], I2C_CLK_REG_MASK(5),
582 I2C_CLK_REG_VALUE(5, src_clk_div
));
585 rk_clrsetreg(&cru
->clksel_con
[62], I2C_CLK_REG_MASK(6),
586 I2C_CLK_REG_VALUE(6, src_clk_div
));
589 rk_clrsetreg(&cru
->clksel_con
[63], I2C_CLK_REG_MASK(7),
590 I2C_CLK_REG_VALUE(7, src_clk_div
));
593 printf("do not support this i2c bus\n");
597 return DIV_TO_RATE(GPLL_HZ
, src_clk_div
);
600 static ulong
rk3399_vop_set_clk(struct rk3399_cru
*cru
, ulong clk_id
, u32 hz
)
602 struct pll_div vpll_config
= {0};
603 int aclk_vop
= 198*MHz
;
604 void *aclkreg_addr
, *dclkreg_addr
;
609 aclkreg_addr
= &cru
->clksel_con
[47];
610 dclkreg_addr
= &cru
->clksel_con
[49];
613 aclkreg_addr
= &cru
->clksel_con
[48];
614 dclkreg_addr
= &cru
->clksel_con
[50];
619 /* vop aclk source clk: cpll */
620 div
= CPLL_HZ
/ aclk_vop
;
621 assert(div
- 1 < 32);
623 rk_clrsetreg(aclkreg_addr
,
624 ACLK_VOP_PLL_SEL_MASK
| ACLK_VOP_DIV_CON_MASK
,
625 ACLK_VOP_PLL_SEL_CPLL
<< ACLK_VOP_PLL_SEL_SHIFT
|
626 (div
- 1) << ACLK_VOP_DIV_CON_SHIFT
);
628 /* vop dclk source from vpll, and equals to vpll(means div == 1) */
629 if (pll_para_config(hz
, &vpll_config
))
632 rkclk_set_pll(&cru
->vpll_con
[0], &vpll_config
);
634 rk_clrsetreg(dclkreg_addr
,
635 DCLK_VOP_DCLK_SEL_MASK
| DCLK_VOP_PLL_SEL_MASK
|
636 DCLK_VOP_DIV_CON_MASK
,
637 DCLK_VOP_DCLK_SEL_DIVOUT
<< DCLK_VOP_DCLK_SEL_SHIFT
|
638 DCLK_VOP_PLL_SEL_VPLL
<< DCLK_VOP_PLL_SEL_SHIFT
|
639 (1 - 1) << DCLK_VOP_DIV_CON_SHIFT
);
644 static ulong
rk3399_mmc_get_clk(struct rk3399_cru
*cru
, uint clk_id
)
650 con
= readl(&cru
->clksel_con
[16]);
653 con
= readl(&cru
->clksel_con
[21]);
658 div
= (con
& CLK_EMMC_DIV_CON_MASK
) >> CLK_EMMC_DIV_CON_SHIFT
;
660 if ((con
& CLK_EMMC_PLL_MASK
) >> CLK_EMMC_PLL_SHIFT
661 == CLK_EMMC_PLL_SEL_24M
)
662 return DIV_TO_RATE(24*1024*1024, div
);
664 return DIV_TO_RATE(GPLL_HZ
, div
);
667 static ulong
rk3399_mmc_set_clk(struct rk3399_cru
*cru
,
668 ulong clk_id
, ulong set_rate
)
671 int aclk_emmc
= 198*MHz
;
675 /* Select clk_sdmmc source from GPLL by default */
676 src_clk_div
= GPLL_HZ
/ set_rate
;
678 if (src_clk_div
> 127) {
679 /* use 24MHz source for 400KHz clock */
680 src_clk_div
= 24*1024*1024 / set_rate
;
681 rk_clrsetreg(&cru
->clksel_con
[16],
682 CLK_EMMC_PLL_MASK
| CLK_EMMC_DIV_CON_MASK
,
683 CLK_EMMC_PLL_SEL_24M
<< CLK_EMMC_PLL_SHIFT
|
684 (src_clk_div
- 1) << CLK_EMMC_DIV_CON_SHIFT
);
686 rk_clrsetreg(&cru
->clksel_con
[16],
687 CLK_EMMC_PLL_MASK
| CLK_EMMC_DIV_CON_MASK
,
688 CLK_EMMC_PLL_SEL_GPLL
<< CLK_EMMC_PLL_SHIFT
|
689 (src_clk_div
- 1) << CLK_EMMC_DIV_CON_SHIFT
);
693 /* Select aclk_emmc source from GPLL */
694 src_clk_div
= GPLL_HZ
/ aclk_emmc
;
695 assert(src_clk_div
- 1 < 31);
697 rk_clrsetreg(&cru
->clksel_con
[21],
698 ACLK_EMMC_PLL_SEL_MASK
| ACLK_EMMC_DIV_CON_MASK
,
699 ACLK_EMMC_PLL_SEL_GPLL
<< ACLK_EMMC_PLL_SEL_SHIFT
|
700 (src_clk_div
- 1) << ACLK_EMMC_DIV_CON_SHIFT
);
702 /* Select clk_emmc source from GPLL too */
703 src_clk_div
= GPLL_HZ
/ set_rate
;
704 assert(src_clk_div
- 1 < 127);
706 rk_clrsetreg(&cru
->clksel_con
[22],
707 CLK_EMMC_PLL_MASK
| CLK_EMMC_DIV_CON_MASK
,
708 CLK_EMMC_PLL_SEL_GPLL
<< CLK_EMMC_PLL_SHIFT
|
709 (src_clk_div
- 1) << CLK_EMMC_DIV_CON_SHIFT
);
714 return rk3399_mmc_get_clk(cru
, clk_id
);
717 static ulong
rk3399_clk_get_rate(struct clk
*clk
)
719 struct rk3399_clk_priv
*priv
= dev_get_priv(clk
->dev
);
727 rate
= rk3399_mmc_get_clk(priv
->cru
, clk
->id
);
735 rate
= rk3399_i2c_get_clk(priv
->cru
, clk
->id
);
747 static ulong
rk3399_clk_set_rate(struct clk
*clk
, ulong rate
)
749 struct rk3399_clk_priv
*priv
= dev_get_priv(clk
->dev
);
757 ret
= rk3399_mmc_set_clk(priv
->cru
, clk
->id
, rate
);
765 ret
= rk3399_i2c_set_clk(priv
->cru
, clk
->id
, rate
);
769 ret
= rk3399_vop_set_clk(priv
->cru
, clk
->id
, rate
);
778 static struct clk_ops rk3399_clk_ops
= {
779 .get_rate
= rk3399_clk_get_rate
,
780 .set_rate
= rk3399_clk_set_rate
,
783 void *rockchip_get_cru(void)
789 ret
= uclass_get_device_by_name(UCLASS_CLK
, "clk_rk3399", &dev
);
793 addr
= dev_get_addr_ptr(dev
);
794 if ((fdt_addr_t
)addr
== FDT_ADDR_T_NONE
)
795 return ERR_PTR(-EINVAL
);
800 static int rk3399_clk_probe(struct udevice
*dev
)
802 struct rk3399_clk_priv
*priv
= dev_get_priv(dev
);
804 rkclk_init(priv
->cru
);
809 static int rk3399_clk_ofdata_to_platdata(struct udevice
*dev
)
811 struct rk3399_clk_priv
*priv
= dev_get_priv(dev
);
813 priv
->cru
= (struct rk3399_cru
*)dev_get_addr(dev
);
818 static int rk3399_clk_bind(struct udevice
*dev
)
822 /* The reset driver does not have a device node, so bind it here */
823 ret
= device_bind_driver(gd
->dm_root
, "rk3399_sysreset", "reset", &dev
);
825 printf("Warning: No RK3399 reset driver: ret=%d\n", ret
);
830 static const struct udevice_id rk3399_clk_ids
[] = {
831 { .compatible
= "rockchip,rk3399-cru" },
835 U_BOOT_DRIVER(clk_rk3399
) = {
836 .name
= "clk_rk3399",
838 .of_match
= rk3399_clk_ids
,
839 .priv_auto_alloc_size
= sizeof(struct rk3399_clk_priv
),
840 .ofdata_to_platdata
= rk3399_clk_ofdata_to_platdata
,
841 .ops
= &rk3399_clk_ops
,
842 .bind
= rk3399_clk_bind
,
843 .probe
= rk3399_clk_probe
,
846 static ulong
rk3399_i2c_get_pmuclk(struct rk3399_pmucru
*pmucru
, ulong clk_id
)
852 con
= readl(&pmucru
->pmucru_clksel
[2]);
853 div
= I2C_CLK_DIV_VALUE(con
, 0);
856 con
= readl(&pmucru
->pmucru_clksel
[3]);
857 div
= I2C_CLK_DIV_VALUE(con
, 4);
860 con
= readl(&pmucru
->pmucru_clksel
[2]);
861 div
= I2C_CLK_DIV_VALUE(con
, 8);
864 printf("do not support this i2c bus\n");
868 return DIV_TO_RATE(PPLL_HZ
, div
);
871 static ulong
rk3399_i2c_set_pmuclk(struct rk3399_pmucru
*pmucru
, ulong clk_id
,
876 src_clk_div
= PPLL_HZ
/ hz
;
877 assert(src_clk_div
- 1 < 127);
881 rk_clrsetreg(&pmucru
->pmucru_clksel
[2], I2C_PMUCLK_REG_MASK(0),
882 I2C_PMUCLK_REG_VALUE(0, src_clk_div
));
885 rk_clrsetreg(&pmucru
->pmucru_clksel
[3], I2C_PMUCLK_REG_MASK(4),
886 I2C_PMUCLK_REG_VALUE(4, src_clk_div
));
889 rk_clrsetreg(&pmucru
->pmucru_clksel
[2], I2C_PMUCLK_REG_MASK(8),
890 I2C_PMUCLK_REG_VALUE(8, src_clk_div
));
893 printf("do not support this i2c bus\n");
897 return DIV_TO_RATE(PPLL_HZ
, src_clk_div
);
900 static ulong
rk3399_pwm_get_clk(struct rk3399_pmucru
*pmucru
)
904 /* PWM closk rate is same as pclk_pmu */
905 con
= readl(&pmucru
->pmucru_clksel
[0]);
906 div
= con
& PMU_PCLK_DIV_CON_MASK
;
908 return DIV_TO_RATE(PPLL_HZ
, div
);
911 static ulong
rk3399_pmuclk_get_rate(struct clk
*clk
)
913 struct rk3399_pmuclk_priv
*priv
= dev_get_priv(clk
->dev
);
918 rate
= rk3399_pwm_get_clk(priv
->pmucru
);
923 rate
= rk3399_i2c_get_pmuclk(priv
->pmucru
, clk
->id
);
932 static ulong
rk3399_pmuclk_set_rate(struct clk
*clk
, ulong rate
)
934 struct rk3399_pmuclk_priv
*priv
= dev_get_priv(clk
->dev
);
941 ret
= rk3399_i2c_set_pmuclk(priv
->pmucru
, clk
->id
, rate
);
950 static struct clk_ops rk3399_pmuclk_ops
= {
951 .get_rate
= rk3399_pmuclk_get_rate
,
952 .set_rate
= rk3399_pmuclk_set_rate
,
955 static void pmuclk_init(struct rk3399_pmucru
*pmucru
)
959 /* configure pmu pll(ppll) */
960 rkclk_set_pll(&pmucru
->ppll_con
[0], &ppll_init_cfg
);
962 /* configure pmu pclk */
963 pclk_div
= PPLL_HZ
/ PMU_PCLK_HZ
- 1;
964 assert((pclk_div
+ 1) * PMU_PCLK_HZ
== PPLL_HZ
&& pclk_div
< 0x1f);
965 rk_clrsetreg(&pmucru
->pmucru_clksel
[0],
966 PMU_PCLK_DIV_CON_MASK
,
967 pclk_div
<< PMU_PCLK_DIV_CON_SHIFT
);
970 static int rk3399_pmuclk_probe(struct udevice
*dev
)
972 struct rk3399_pmuclk_priv
*priv
= dev_get_priv(dev
);
974 pmuclk_init(priv
->pmucru
);
979 static int rk3399_pmuclk_ofdata_to_platdata(struct udevice
*dev
)
981 struct rk3399_pmuclk_priv
*priv
= dev_get_priv(dev
);
983 priv
->pmucru
= (struct rk3399_pmucru
*)dev_get_addr(dev
);
988 static const struct udevice_id rk3399_pmuclk_ids
[] = {
989 { .compatible
= "rockchip,rk3399-pmucru" },
993 U_BOOT_DRIVER(pmuclk_rk3399
) = {
994 .name
= "pmuclk_rk3399",
996 .of_match
= rk3399_pmuclk_ids
,
997 .priv_auto_alloc_size
= sizeof(struct rk3399_pmuclk_priv
),
998 .ofdata_to_platdata
= rk3399_pmuclk_ofdata_to_platdata
,
999 .ops
= &rk3399_pmuclk_ops
,
1000 .probe
= rk3399_pmuclk_probe
,