2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
6 * Based on CAAM driver in drivers/crypto/caam in Linux
14 #include "desc_constr.h"
15 #ifdef CONFIG_FSL_CORENET
16 #include <asm/fsl_pamu.h>
19 #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
20 #define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
22 uint32_t sec_offset
[CONFIG_SYS_FSL_MAX_NUM_OF_SEC
] = {
24 #if defined(CONFIG_ARCH_C29X)
25 CONFIG_SYS_FSL_SEC_IDX_OFFSET
,
26 2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET
30 #define SEC_ADDR(idx) \
31 ((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
33 #define SEC_JR0_ADDR(idx) \
35 (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
37 struct jobring jr0
[CONFIG_SYS_FSL_MAX_NUM_OF_SEC
];
39 static inline void start_jr0(uint8_t sec_idx
)
41 ccsr_sec_t
*sec
= (void *)SEC_ADDR(sec_idx
);
42 u32 ctpr_ms
= sec_in32(&sec
->ctpr_ms
);
43 u32 scfgr
= sec_in32(&sec
->scfgr
);
45 if (ctpr_ms
& SEC_CTPR_MS_VIRT_EN_INCL
) {
46 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
47 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SEC_SCFGR_VIRT_EN = 1
49 if ((ctpr_ms
& SEC_CTPR_MS_VIRT_EN_POR
) ||
50 (scfgr
& SEC_SCFGR_VIRT_EN
))
51 sec_out32(&sec
->jrstartr
, CONFIG_JRSTARTR_JR0
);
53 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
54 if (ctpr_ms
& SEC_CTPR_MS_VIRT_EN_POR
)
55 sec_out32(&sec
->jrstartr
, CONFIG_JRSTARTR_JR0
);
59 static inline void jr_reset_liodn(uint8_t sec_idx
)
61 ccsr_sec_t
*sec
= (void *)SEC_ADDR(sec_idx
);
62 sec_out32(&sec
->jrliodnr
[0].ls
, 0);
65 static inline void jr_disable_irq(uint8_t sec_idx
)
67 struct jr_regs
*regs
= (struct jr_regs
*)SEC_JR0_ADDR(sec_idx
);
68 uint32_t jrcfg
= sec_in32(®s
->jrcfg1
);
70 jrcfg
= jrcfg
| JR_INTMASK
;
72 sec_out32(®s
->jrcfg1
, jrcfg
);
75 static void jr_initregs(uint8_t sec_idx
)
77 struct jr_regs
*regs
= (struct jr_regs
*)SEC_JR0_ADDR(sec_idx
);
78 struct jobring
*jr
= &jr0
[sec_idx
];
79 phys_addr_t ip_base
= virt_to_phys((void *)jr
->input_ring
);
80 phys_addr_t op_base
= virt_to_phys((void *)jr
->output_ring
);
82 #ifdef CONFIG_PHYS_64BIT
83 sec_out32(®s
->irba_h
, ip_base
>> 32);
85 sec_out32(®s
->irba_h
, 0x0);
87 sec_out32(®s
->irba_l
, (uint32_t)ip_base
);
88 #ifdef CONFIG_PHYS_64BIT
89 sec_out32(®s
->orba_h
, op_base
>> 32);
91 sec_out32(®s
->orba_h
, 0x0);
93 sec_out32(®s
->orba_l
, (uint32_t)op_base
);
94 sec_out32(®s
->ors
, JR_SIZE
);
95 sec_out32(®s
->irs
, JR_SIZE
);
98 jr_disable_irq(sec_idx
);
101 static int jr_init(uint8_t sec_idx
)
103 struct jobring
*jr
= &jr0
[sec_idx
];
105 memset(jr
, 0, sizeof(struct jobring
));
107 jr
->jq_id
= DEFAULT_JR_ID
;
108 jr
->irq
= DEFAULT_IRQ
;
110 #ifdef CONFIG_FSL_CORENET
111 jr
->liodn
= DEFAULT_JR_LIODN
;
114 jr
->input_ring
= (dma_addr_t
*)memalign(ARCH_DMA_MINALIGN
,
115 JR_SIZE
* sizeof(dma_addr_t
));
119 jr
->op_size
= roundup(JR_SIZE
* sizeof(struct op_ring
),
122 (struct op_ring
*)memalign(ARCH_DMA_MINALIGN
, jr
->op_size
);
123 if (!jr
->output_ring
)
126 memset(jr
->input_ring
, 0, JR_SIZE
* sizeof(dma_addr_t
));
127 memset(jr
->output_ring
, 0, jr
->op_size
);
131 jr_initregs(sec_idx
);
136 static int jr_sw_cleanup(uint8_t sec_idx
)
138 struct jobring
*jr
= &jr0
[sec_idx
];
144 memset(jr
->info
, 0, sizeof(jr
->info
));
145 memset(jr
->input_ring
, 0, jr
->size
* sizeof(dma_addr_t
));
146 memset(jr
->output_ring
, 0, jr
->size
* sizeof(struct op_ring
));
151 static int jr_hw_reset(uint8_t sec_idx
)
153 struct jr_regs
*regs
= (struct jr_regs
*)SEC_JR0_ADDR(sec_idx
);
154 uint32_t timeout
= 100000;
155 uint32_t jrint
, jrcr
;
157 sec_out32(®s
->jrcr
, JRCR_RESET
);
159 jrint
= sec_in32(®s
->jrint
);
160 } while (((jrint
& JRINT_ERR_HALT_MASK
) ==
161 JRINT_ERR_HALT_INPROGRESS
) && --timeout
);
163 jrint
= sec_in32(®s
->jrint
);
164 if (((jrint
& JRINT_ERR_HALT_MASK
) !=
165 JRINT_ERR_HALT_INPROGRESS
) && timeout
== 0)
169 sec_out32(®s
->jrcr
, JRCR_RESET
);
171 jrcr
= sec_in32(®s
->jrcr
);
172 } while ((jrcr
& JRCR_RESET
) && --timeout
);
180 /* -1 --- error, can't enqueue -- no space available */
181 static int jr_enqueue(uint32_t *desc_addr
,
182 void (*callback
)(uint32_t status
, void *arg
),
183 void *arg
, uint8_t sec_idx
)
185 struct jr_regs
*regs
= (struct jr_regs
*)SEC_JR0_ADDR(sec_idx
);
186 struct jobring
*jr
= &jr0
[sec_idx
];
189 int length
= desc_len(desc_addr
);
191 #ifdef CONFIG_PHYS_64BIT
192 uint32_t *addr_hi
, *addr_lo
;
195 /* The descriptor must be submitted to SEC block as per endianness
197 * So, if the endianness of Core and SEC block is different, each word
198 * of the descriptor will be byte-swapped.
200 for (i
= 0; i
< length
; i
++) {
201 desc_word
= desc_addr
[i
];
202 sec_out32((uint32_t *)&desc_addr
[i
], desc_word
);
205 phys_addr_t desc_phys_addr
= virt_to_phys(desc_addr
);
207 jr
->info
[head
].desc_phys_addr
= desc_phys_addr
;
208 jr
->info
[head
].callback
= (void *)callback
;
209 jr
->info
[head
].arg
= arg
;
210 jr
->info
[head
].op_done
= 0;
212 unsigned long start
= (unsigned long)&jr
->info
[head
] &
213 ~(ARCH_DMA_MINALIGN
- 1);
214 unsigned long end
= ALIGN((unsigned long)&jr
->info
[head
] +
215 sizeof(struct jr_info
), ARCH_DMA_MINALIGN
);
216 flush_dcache_range(start
, end
);
218 #ifdef CONFIG_PHYS_64BIT
219 /* Write the 64 bit Descriptor address on Input Ring.
220 * The 32 bit hign and low part of the address will
221 * depend on endianness of SEC block.
223 #ifdef CONFIG_SYS_FSL_SEC_LE
224 addr_lo
= (uint32_t *)(&jr
->input_ring
[head
]);
225 addr_hi
= (uint32_t *)(&jr
->input_ring
[head
]) + 1;
226 #elif defined(CONFIG_SYS_FSL_SEC_BE)
227 addr_hi
= (uint32_t *)(&jr
->input_ring
[head
]);
228 addr_lo
= (uint32_t *)(&jr
->input_ring
[head
]) + 1;
229 #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
231 sec_out32(addr_hi
, (uint32_t)(desc_phys_addr
>> 32));
232 sec_out32(addr_lo
, (uint32_t)(desc_phys_addr
));
235 /* Write the 32 bit Descriptor address on Input Ring. */
236 sec_out32(&jr
->input_ring
[head
], desc_phys_addr
);
237 #endif /* ifdef CONFIG_PHYS_64BIT */
239 start
= (unsigned long)&jr
->input_ring
[head
] & ~(ARCH_DMA_MINALIGN
- 1);
240 end
= ALIGN((unsigned long)&jr
->input_ring
[head
] +
241 sizeof(dma_addr_t
), ARCH_DMA_MINALIGN
);
242 flush_dcache_range(start
, end
);
244 jr
->head
= (head
+ 1) & (jr
->size
- 1);
246 /* Invalidate output ring */
247 start
= (unsigned long)jr
->output_ring
&
248 ~(ARCH_DMA_MINALIGN
- 1);
249 end
= ALIGN((unsigned long)jr
->output_ring
+ jr
->op_size
,
251 invalidate_dcache_range(start
, end
);
253 sec_out32(®s
->irja
, 1);
258 static int jr_dequeue(int sec_idx
)
260 struct jr_regs
*regs
= (struct jr_regs
*)SEC_JR0_ADDR(sec_idx
);
261 struct jobring
*jr
= &jr0
[sec_idx
];
265 void (*callback
)(uint32_t status
, void *arg
);
267 #ifdef CONFIG_PHYS_64BIT
268 uint32_t *addr_hi
, *addr_lo
;
273 while (sec_in32(®s
->orsf
) && CIRC_CNT(jr
->head
, jr
->tail
,
279 #ifdef CONFIG_PHYS_64BIT
280 /* Read the 64 bit Descriptor address from Output Ring.
281 * The 32 bit hign and low part of the address will
282 * depend on endianness of SEC block.
284 #ifdef CONFIG_SYS_FSL_SEC_LE
285 addr_lo
= (uint32_t *)(&jr
->output_ring
[jr
->tail
].desc
);
286 addr_hi
= (uint32_t *)(&jr
->output_ring
[jr
->tail
].desc
) + 1;
287 #elif defined(CONFIG_SYS_FSL_SEC_BE)
288 addr_hi
= (uint32_t *)(&jr
->output_ring
[jr
->tail
].desc
);
289 addr_lo
= (uint32_t *)(&jr
->output_ring
[jr
->tail
].desc
) + 1;
290 #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
292 op_desc
= ((u64
)sec_in32(addr_hi
) << 32) |
293 ((u64
)sec_in32(addr_lo
));
296 /* Read the 32 bit Descriptor address from Output Ring. */
297 addr
= (uint32_t *)&jr
->output_ring
[jr
->tail
].desc
;
298 op_desc
= sec_in32(addr
);
299 #endif /* ifdef CONFIG_PHYS_64BIT */
301 uint32_t status
= sec_in32(&jr
->output_ring
[jr
->tail
].status
);
303 for (i
= 0; CIRC_CNT(head
, tail
+ i
, jr
->size
) >= 1; i
++) {
304 idx
= (tail
+ i
) & (jr
->size
- 1);
305 if (op_desc
== jr
->info
[idx
].desc_phys_addr
) {
311 /* Error condition if match not found */
315 jr
->info
[idx
].op_done
= 1;
316 callback
= (void *)jr
->info
[idx
].callback
;
317 arg
= jr
->info
[idx
].arg
;
319 /* When the job on tail idx gets done, increment
320 * tail till the point where job completed out of oredr has
321 * been taken into account
325 tail
= (tail
+ 1) & (jr
->size
- 1);
326 } while (jr
->info
[tail
].op_done
);
329 jr
->read_idx
= (jr
->read_idx
+ 1) & (jr
->size
- 1);
331 sec_out32(®s
->orjr
, 1);
332 jr
->info
[idx
].op_done
= 0;
334 callback(status
, arg
);
340 static void desc_done(uint32_t status
, void *arg
)
342 struct result
*x
= arg
;
344 #ifndef CONFIG_SPL_BUILD
345 caam_jr_strstatus(status
);
350 static inline int run_descriptor_jr_idx(uint32_t *desc
, uint8_t sec_idx
)
352 unsigned long long timeval
= get_ticks();
353 unsigned long long timeout
= usec2ticks(CONFIG_SEC_DEQ_TIMEOUT
);
357 memset(&op
, 0, sizeof(op
));
359 ret
= jr_enqueue(desc
, desc_done
, &op
, sec_idx
);
361 debug("Error in SEC enq\n");
366 timeval
= get_ticks();
367 timeout
= usec2ticks(CONFIG_SEC_DEQ_TIMEOUT
);
368 while (op
.done
!= 1) {
369 ret
= jr_dequeue(sec_idx
);
371 debug("Error in SEC deq\n");
376 if ((get_ticks() - timeval
) > timeout
) {
377 debug("SEC Dequeue timed out\n");
384 debug("Error %x\n", op
.status
);
391 int run_descriptor_jr(uint32_t *desc
)
393 return run_descriptor_jr_idx(desc
, 0);
396 static inline int jr_reset_sec(uint8_t sec_idx
)
398 if (jr_hw_reset(sec_idx
) < 0)
401 /* Clean up the jobring structure maintained by software */
402 jr_sw_cleanup(sec_idx
);
409 return jr_reset_sec(0);
412 static inline int sec_reset_idx(uint8_t sec_idx
)
414 ccsr_sec_t
*sec
= (void *)SEC_ADDR(sec_idx
);
415 uint32_t mcfgr
= sec_in32(&sec
->mcfgr
);
416 uint32_t timeout
= 100000;
418 mcfgr
|= MCFGR_SWRST
;
419 sec_out32(&sec
->mcfgr
, mcfgr
);
421 mcfgr
|= MCFGR_DMA_RST
;
422 sec_out32(&sec
->mcfgr
, mcfgr
);
424 mcfgr
= sec_in32(&sec
->mcfgr
);
425 } while ((mcfgr
& MCFGR_DMA_RST
) == MCFGR_DMA_RST
&& --timeout
);
432 mcfgr
= sec_in32(&sec
->mcfgr
);
433 } while ((mcfgr
& MCFGR_SWRST
) == MCFGR_SWRST
&& --timeout
);
442 return sec_reset_idx(0);
444 #ifndef CONFIG_SPL_BUILD
445 static int instantiate_rng(uint8_t sec_idx
)
449 int ret
= 0, sh_idx
, size
;
450 ccsr_sec_t __iomem
*sec
= (ccsr_sec_t __iomem
*)SEC_ADDR(sec_idx
);
451 struct rng4tst __iomem
*rng
=
452 (struct rng4tst __iomem
*)&sec
->rng
;
454 desc
= memalign(ARCH_DMA_MINALIGN
, sizeof(uint32_t) * 6);
456 printf("cannot allocate RNG init descriptor memory\n");
460 for (sh_idx
= 0; sh_idx
< RNG4_MAX_HANDLES
; sh_idx
++) {
462 * If the corresponding bit is set, this state handle
463 * was initialized by somebody else, so it's left alone.
465 rdsta_val
= sec_in32(&rng
->rdsta
) & RNG_STATE_HANDLE_MASK
;
466 if (rdsta_val
& (1 << sh_idx
))
469 inline_cnstr_jobdesc_rng_instantiation(desc
, sh_idx
);
470 size
= roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN
);
471 flush_dcache_range((unsigned long)desc
,
472 (unsigned long)desc
+ size
);
474 ret
= run_descriptor_jr_idx(desc
, sec_idx
);
477 printf("RNG: Instantiation failed with error 0x%x\n",
480 rdsta_val
= sec_in32(&rng
->rdsta
) & RNG_STATE_HANDLE_MASK
;
481 if (!(rdsta_val
& (1 << sh_idx
))) {
486 memset(desc
, 0, sizeof(uint32_t) * 6);
494 static u8
get_rng_vid(uint8_t sec_idx
)
496 ccsr_sec_t
*sec
= (void *)SEC_ADDR(sec_idx
);
497 u32 cha_vid
= sec_in32(&sec
->chavid_ls
);
499 return (cha_vid
& SEC_CHAVID_RNG_LS_MASK
) >> SEC_CHAVID_LS_RNG_SHIFT
;
503 * By default, the TRNG runs for 200 clocks per sample;
504 * 1200 clocks per sample generates better entropy.
506 static void kick_trng(int ent_delay
, uint8_t sec_idx
)
508 ccsr_sec_t __iomem
*sec
= (ccsr_sec_t __iomem
*)SEC_ADDR(sec_idx
);
509 struct rng4tst __iomem
*rng
=
510 (struct rng4tst __iomem
*)&sec
->rng
;
513 /* put RNG4 into program mode */
514 sec_setbits32(&rng
->rtmctl
, RTMCTL_PRGM
);
515 /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
516 * length (in system clocks) of each Entropy sample taken
518 val
= sec_in32(&rng
->rtsdctl
);
519 val
= (val
& ~RTSDCTL_ENT_DLY_MASK
) |
520 (ent_delay
<< RTSDCTL_ENT_DLY_SHIFT
);
521 sec_out32(&rng
->rtsdctl
, val
);
522 /* min. freq. count, equal to 1/4 of the entropy sample length */
523 sec_out32(&rng
->rtfreqmin
, ent_delay
>> 2);
524 /* disable maximum frequency count */
525 sec_out32(&rng
->rtfreqmax
, RTFRQMAX_DISABLE
);
527 * select raw sampling in both entropy shifter
528 * and statistical checker
530 sec_setbits32(&rng
->rtmctl
, RTMCTL_SAMP_MODE_RAW_ES_SC
);
531 /* put RNG4 into run mode */
532 sec_clrbits32(&rng
->rtmctl
, RTMCTL_PRGM
);
535 static int rng_init(uint8_t sec_idx
)
537 int ret
, ent_delay
= RTSDCTL_ENT_DLY_MIN
;
538 ccsr_sec_t __iomem
*sec
= (ccsr_sec_t __iomem
*)SEC_ADDR(sec_idx
);
539 struct rng4tst __iomem
*rng
=
540 (struct rng4tst __iomem
*)&sec
->rng
;
544 inst_handles
= sec_in32(&rng
->rdsta
) & RNG_STATE_HANDLE_MASK
;
547 * If either of the SH's were instantiated by somebody else
548 * then it is assumed that the entropy
549 * parameters are properly set and thus the function
550 * setting these (kick_trng(...)) is skipped.
551 * Also, if a handle was instantiated, do not change
552 * the TRNG parameters.
555 kick_trng(ent_delay
, sec_idx
);
559 * if instantiate_rng(...) fails, the loop will rerun
560 * and the kick_trng(...) function will modfiy the
561 * upper and lower limits of the entropy sampling
562 * interval, leading to a sucessful initialization of
565 ret
= instantiate_rng(sec_idx
);
566 } while ((ret
== -1) && (ent_delay
< RTSDCTL_ENT_DLY_MAX
));
568 printf("RNG: Failed to instantiate RNG\n");
572 /* Enable RDB bit so that RNG works faster */
573 sec_setbits32(&sec
->scfgr
, SEC_SCFGR_RDBENABLE
);
578 int sec_init_idx(uint8_t sec_idx
)
580 ccsr_sec_t
*sec
= (void *)SEC_ADDR(sec_idx
);
581 uint32_t mcr
= sec_in32(&sec
->mcfgr
);
586 #ifdef CONFIG_FSL_CORENET
592 if (!(sec_idx
< CONFIG_SYS_FSL_MAX_NUM_OF_SEC
)) {
593 printf("SEC initialization failed\n");
598 * Modifying CAAM Read/Write Attributes
600 * For AXI Write - Cacheable, Write Back, Write allocate
601 * For AXI Read - Cacheable, Read allocate
602 * Only For LS2080a, to solve CAAM coherency issues
604 #ifdef CONFIG_ARCH_LS2080A
605 mcr
= (mcr
& ~MCFGR_AWCACHE_MASK
) | (0xb << MCFGR_AWCACHE_SHIFT
);
606 mcr
= (mcr
& ~MCFGR_ARCACHE_MASK
) | (0x6 << MCFGR_ARCACHE_SHIFT
);
608 mcr
= (mcr
& ~MCFGR_AWCACHE_MASK
) | (0x2 << MCFGR_AWCACHE_SHIFT
);
611 #ifdef CONFIG_PHYS_64BIT
612 mcr
|= (1 << MCFGR_PS_SHIFT
);
614 sec_out32(&sec
->mcfgr
, mcr
);
616 #ifdef CONFIG_FSL_CORENET
617 #ifdef CONFIG_SPL_BUILD
619 * For SPL Build, Set the Liodns in SEC JR0 for
620 * creating PAMU entries corresponding to these.
621 * For normal build, these are set in set_liodns().
623 liodn_ns
= CONFIG_SPL_JR0_LIODN_NS
& JRNSLIODN_MASK
;
624 liodn_s
= CONFIG_SPL_JR0_LIODN_S
& JRSLIODN_MASK
;
626 liodnr
= sec_in32(&sec
->jrliodnr
[0].ls
) &
627 ~(JRNSLIODN_MASK
| JRSLIODN_MASK
);
629 (liodn_ns
<< JRNSLIODN_SHIFT
) |
630 (liodn_s
<< JRSLIODN_SHIFT
);
631 sec_out32(&sec
->jrliodnr
[0].ls
, liodnr
);
633 liodnr
= sec_in32(&sec
->jrliodnr
[0].ls
);
634 liodn_ns
= (liodnr
& JRNSLIODN_MASK
) >> JRNSLIODN_SHIFT
;
635 liodn_s
= (liodnr
& JRSLIODN_MASK
) >> JRSLIODN_SHIFT
;
639 /* Set ownership of job rings to non-TrustZone mode by default */
640 for (i
= 0; i
< ARRAY_SIZE(sec
->jrliodnr
); i
++) {
641 jrown_ns
= sec_in32(&sec
->jrliodnr
[i
].ms
);
642 jrown_ns
|= JROWN_NS
| JRMID_NS
;
643 sec_out32(&sec
->jrliodnr
[i
].ms
, jrown_ns
);
646 ret
= jr_init(sec_idx
);
648 printf("SEC initialization failed\n");
652 #ifdef CONFIG_FSL_CORENET
653 ret
= sec_config_pamu_table(liodn_ns
, liodn_s
);
659 #ifndef CONFIG_SPL_BUILD
660 if (get_rng_vid(sec_idx
) >= 4) {
661 if (rng_init(sec_idx
) < 0) {
662 printf("SEC%u: RNG instantiation failed\n", sec_idx
);
665 printf("SEC%u: RNG instantiated\n", sec_idx
);
673 return sec_init_idx(0);