2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
9 #include <asm/arch/sdram.h>
11 #include "sequencer.h"
14 * FIXME: This path is temporary until the SDRAM driver gets
15 * a proper thorough cleanup.
17 #include "../../../board/altera/socfpga/qts/sequencer_auto.h"
18 #include "../../../board/altera/socfpga/qts/sequencer_defines.h"
20 static struct socfpga_sdr_rw_load_manager
*sdr_rw_load_mgr_regs
=
21 (struct socfpga_sdr_rw_load_manager
*)(SDR_PHYGRP_RWMGRGRP_ADDRESS
| 0x800);
23 static struct socfpga_sdr_rw_load_jump_manager
*sdr_rw_load_jump_mgr_regs
=
24 (struct socfpga_sdr_rw_load_jump_manager
*)(SDR_PHYGRP_RWMGRGRP_ADDRESS
| 0xC00);
26 static struct socfpga_sdr_reg_file
*sdr_reg_file
=
27 (struct socfpga_sdr_reg_file
*)SDR_PHYGRP_REGFILEGRP_ADDRESS
;
29 static struct socfpga_sdr_scc_mgr
*sdr_scc_mgr
=
30 (struct socfpga_sdr_scc_mgr
*)(SDR_PHYGRP_SCCGRP_ADDRESS
| 0xe00);
32 static struct socfpga_phy_mgr_cmd
*phy_mgr_cmd
=
33 (struct socfpga_phy_mgr_cmd
*)SDR_PHYGRP_PHYMGRGRP_ADDRESS
;
35 static struct socfpga_phy_mgr_cfg
*phy_mgr_cfg
=
36 (struct socfpga_phy_mgr_cfg
*)(SDR_PHYGRP_PHYMGRGRP_ADDRESS
| 0x40);
38 static struct socfpga_data_mgr
*data_mgr
=
39 (struct socfpga_data_mgr
*)SDR_PHYGRP_DATAMGRGRP_ADDRESS
;
41 static struct socfpga_sdr_ctrl
*sdr_ctrl
=
42 (struct socfpga_sdr_ctrl
*)SDR_CTRLGRP_ADDRESS
;
44 const struct socfpga_sdram_rw_mgr_config
*rwcfg
;
45 const struct socfpga_sdram_io_config
*iocfg
;
50 * In order to reduce ROM size, most of the selectable calibration steps are
51 * decided at compile time based on the user's calibration mode selection,
52 * as captured by the STATIC_CALIB_STEPS selection below.
54 * However, to support simulation-time selection of fast simulation mode, where
55 * we skip everything except the bare minimum, we need a few of the steps to
56 * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
57 * check, which is based on the rtl-supplied value, or we dynamically compute
58 * the value to use based on the dynamically-chosen calibration mode
62 #define STATIC_IN_RTL_SIM 0
63 #define STATIC_SKIP_DELAY_LOOPS 0
65 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
66 STATIC_SKIP_DELAY_LOOPS)
68 /* calibration steps requested by the rtl */
69 uint16_t dyn_calib_steps
;
72 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
73 * instead of static, we use boolean logic to select between
74 * non-skip and skip values
76 * The mask is set to include all bits when not-skipping, but is
80 uint16_t skip_delay_mask
; /* mask off bits when skipping/not-skipping */
82 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
83 ((non_skip_value) & skip_delay_mask)
86 struct param_type
*param
;
88 static void set_failing_group_stage(uint32_t group
, uint32_t stage
,
92 * Only set the global stage if there was not been any other
95 if (gbl
->error_stage
== CAL_STAGE_NIL
) {
96 gbl
->error_substage
= substage
;
97 gbl
->error_stage
= stage
;
98 gbl
->error_group
= group
;
102 static void reg_file_set_group(u16 set_group
)
104 clrsetbits_le32(&sdr_reg_file
->cur_stage
, 0xffff0000, set_group
<< 16);
107 static void reg_file_set_stage(u8 set_stage
)
109 clrsetbits_le32(&sdr_reg_file
->cur_stage
, 0xffff, set_stage
& 0xff);
112 static void reg_file_set_sub_stage(u8 set_sub_stage
)
114 set_sub_stage
&= 0xff;
115 clrsetbits_le32(&sdr_reg_file
->cur_stage
, 0xff00, set_sub_stage
<< 8);
119 * phy_mgr_initialize() - Initialize PHY Manager
121 * Initialize PHY Manager.
123 static void phy_mgr_initialize(void)
127 debug("%s:%d\n", __func__
, __LINE__
);
128 /* Calibration has control over path to memory */
130 * In Hard PHY this is a 2-bit control:
134 writel(0x3, &phy_mgr_cfg
->mux_sel
);
136 /* USER memory clock is not stable we begin initialization */
137 writel(0, &phy_mgr_cfg
->reset_mem_stbl
);
139 /* USER calibration status all set to zero */
140 writel(0, &phy_mgr_cfg
->cal_status
);
142 writel(0, &phy_mgr_cfg
->cal_debug_info
);
144 /* Init params only if we do NOT skip calibration. */
145 if ((dyn_calib_steps
& CALIB_SKIP_ALL
) == CALIB_SKIP_ALL
)
148 ratio
= rwcfg
->mem_dq_per_read_dqs
/
149 rwcfg
->mem_virtual_groups_per_read_dqs
;
150 param
->read_correct_mask_vg
= (1 << ratio
) - 1;
151 param
->write_correct_mask_vg
= (1 << ratio
) - 1;
152 param
->read_correct_mask
= (1 << rwcfg
->mem_dq_per_read_dqs
) - 1;
153 param
->write_correct_mask
= (1 << rwcfg
->mem_dq_per_write_dqs
) - 1;
157 * set_rank_and_odt_mask() - Set Rank and ODT mask
159 * @odt_mode: ODT mode, OFF or READ_WRITE
161 * Set Rank and ODT mask (On-Die Termination).
163 static void set_rank_and_odt_mask(const u32 rank
, const u32 odt_mode
)
169 if (odt_mode
== RW_MGR_ODT_MODE_OFF
) {
172 } else { /* RW_MGR_ODT_MODE_READ_WRITE */
173 switch (rwcfg
->mem_number_of_ranks
) {
175 /* Read: ODT = 0 ; Write: ODT = 1 */
179 case 2: /* 2 Ranks */
180 if (rwcfg
->mem_number_of_cs_per_dimm
== 1) {
182 * - Dual-Slot , Single-Rank (1 CS per DIMM)
184 * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
186 * Since MEM_NUMBER_OF_RANKS is 2, they
187 * are both single rank with 2 CS each
188 * (special for RDIMM).
190 * Read: Turn on ODT on the opposite rank
191 * Write: Turn on ODT on all ranks
193 odt_mask_0
= 0x3 & ~(1 << rank
);
197 * - Single-Slot , Dual-Rank (2 CS per DIMM)
199 * Read: Turn on ODT off on all ranks
200 * Write: Turn on ODT on active rank
203 odt_mask_1
= 0x3 & (1 << rank
);
206 case 4: /* 4 Ranks */
208 * ----------+-----------------------+
210 * Read From +-----------------------+
211 * Rank | 3 | 2 | 1 | 0 |
212 * ----------+-----+-----+-----+-----+
213 * 0 | 0 | 1 | 0 | 0 |
214 * 1 | 1 | 0 | 0 | 0 |
215 * 2 | 0 | 0 | 0 | 1 |
216 * 3 | 0 | 0 | 1 | 0 |
217 * ----------+-----+-----+-----+-----+
220 * ----------+-----------------------+
222 * Write To +-----------------------+
223 * Rank | 3 | 2 | 1 | 0 |
224 * ----------+-----+-----+-----+-----+
225 * 0 | 0 | 1 | 0 | 1 |
226 * 1 | 1 | 0 | 1 | 0 |
227 * 2 | 0 | 1 | 0 | 1 |
228 * 3 | 1 | 0 | 1 | 0 |
229 * ----------+-----+-----+-----+-----+
253 cs_and_odt_mask
= (0xFF & ~(1 << rank
)) |
254 ((0xFF & odt_mask_0
) << 8) |
255 ((0xFF & odt_mask_1
) << 16);
256 writel(cs_and_odt_mask
, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
257 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET
);
261 * scc_mgr_set() - Set SCC Manager register
262 * @off: Base offset in SCC Manager space
263 * @grp: Read/Write group
264 * @val: Value to be set
266 * This function sets the SCC Manager (Scan Chain Control Manager) register.
268 static void scc_mgr_set(u32 off
, u32 grp
, u32 val
)
270 writel(val
, SDR_PHYGRP_SCCGRP_ADDRESS
| off
| (grp
<< 2));
274 * scc_mgr_initialize() - Initialize SCC Manager registers
276 * Initialize SCC Manager registers.
278 static void scc_mgr_initialize(void)
281 * Clear register file for HPS. 16 (2^4) is the size of the
282 * full register file in the scc mgr:
283 * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
284 * MEM_IF_READ_DQS_WIDTH - 1);
288 for (i
= 0; i
< 16; i
++) {
289 debug_cond(DLEVEL
== 1, "%s:%d: Clearing SCC RFILE index %u\n",
290 __func__
, __LINE__
, i
);
291 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET
, 0, i
);
295 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group
, uint32_t phase
)
297 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET
, write_group
, phase
);
300 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group
, uint32_t delay
)
302 scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET
, read_group
, delay
);
305 static void scc_mgr_set_dqs_en_phase(uint32_t read_group
, uint32_t phase
)
307 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET
, read_group
, phase
);
310 static void scc_mgr_set_dqs_en_delay(uint32_t read_group
, uint32_t delay
)
312 scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET
, read_group
, delay
);
315 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay
)
317 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET
, rwcfg
->mem_dq_per_write_dqs
,
321 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group
, uint32_t delay
)
323 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET
, dq_in_group
, delay
);
326 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group
, uint32_t delay
)
328 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET
, dq_in_group
, delay
);
331 static void scc_mgr_set_dqs_out1_delay(uint32_t delay
)
333 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET
, rwcfg
->mem_dq_per_write_dqs
,
337 static void scc_mgr_set_dm_out1_delay(uint32_t dm
, uint32_t delay
)
339 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET
,
340 rwcfg
->mem_dq_per_write_dqs
+ 1 + dm
,
344 /* load up dqs config settings */
345 static void scc_mgr_load_dqs(uint32_t dqs
)
347 writel(dqs
, &sdr_scc_mgr
->dqs_ena
);
350 /* load up dqs io config settings */
351 static void scc_mgr_load_dqs_io(void)
353 writel(0, &sdr_scc_mgr
->dqs_io_ena
);
356 /* load up dq config settings */
357 static void scc_mgr_load_dq(uint32_t dq_in_group
)
359 writel(dq_in_group
, &sdr_scc_mgr
->dq_ena
);
362 /* load up dm config settings */
363 static void scc_mgr_load_dm(uint32_t dm
)
365 writel(dm
, &sdr_scc_mgr
->dm_ena
);
369 * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
370 * @off: Base offset in SCC Manager space
371 * @grp: Read/Write group
372 * @val: Value to be set
373 * @update: If non-zero, trigger SCC Manager update for all ranks
375 * This function sets the SCC Manager (Scan Chain Control Manager) register
376 * and optionally triggers the SCC update for all ranks.
378 static void scc_mgr_set_all_ranks(const u32 off
, const u32 grp
, const u32 val
,
383 for (r
= 0; r
< rwcfg
->mem_number_of_ranks
;
384 r
+= NUM_RANKS_PER_SHADOW_REG
) {
385 scc_mgr_set(off
, grp
, val
);
387 if (update
|| (r
== 0)) {
388 writel(grp
, &sdr_scc_mgr
->dqs_ena
);
389 writel(0, &sdr_scc_mgr
->update
);
394 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group
, u32 phase
)
397 * USER although the h/w doesn't support different phases per
398 * shadow register, for simplicity our scc manager modeling
399 * keeps different phase settings per shadow reg, and it's
400 * important for us to keep them in sync to match h/w.
401 * for efficiency, the scan chain update should occur only
404 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET
,
405 read_group
, phase
, 0);
408 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group
,
412 * USER although the h/w doesn't support different phases per
413 * shadow register, for simplicity our scc manager modeling
414 * keeps different phase settings per shadow reg, and it's
415 * important for us to keep them in sync to match h/w.
416 * for efficiency, the scan chain update should occur only
419 scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET
,
420 write_group
, phase
, 0);
423 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group
,
427 * In shadow register mode, the T11 settings are stored in
428 * registers in the core, which are updated by the DQS_ENA
429 * signals. Not issuing the SCC_MGR_UPD command allows us to
430 * save lots of rank switching overhead, by calling
431 * select_shadow_regs_for_update with update_scan_chains
434 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET
,
435 read_group
, delay
, 1);
436 writel(0, &sdr_scc_mgr
->update
);
440 * scc_mgr_set_oct_out1_delay() - Set OCT output delay
441 * @write_group: Write group
442 * @delay: Delay value
444 * This function sets the OCT output delay in SCC manager.
446 static void scc_mgr_set_oct_out1_delay(const u32 write_group
, const u32 delay
)
448 const int ratio
= rwcfg
->mem_if_read_dqs_width
/
449 rwcfg
->mem_if_write_dqs_width
;
450 const int base
= write_group
* ratio
;
453 * Load the setting in the SCC manager
454 * Although OCT affects only write data, the OCT delay is controlled
455 * by the DQS logic block which is instantiated once per read group.
456 * For protocols where a write group consists of multiple read groups,
457 * the setting must be set multiple times.
459 for (i
= 0; i
< ratio
; i
++)
460 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET
, base
+ i
, delay
);
464 * scc_mgr_set_hhp_extras() - Set HHP extras.
466 * Load the fixed setting in the SCC manager HHP extras.
468 static void scc_mgr_set_hhp_extras(void)
471 * Load the fixed setting in the SCC manager
472 * bits: 0:0 = 1'b1 - DQS bypass
473 * bits: 1:1 = 1'b1 - DQ bypass
474 * bits: 4:2 = 3'b001 - rfifo_mode
475 * bits: 6:5 = 2'b01 - rfifo clock_select
476 * bits: 7:7 = 1'b0 - separate gating from ungating setting
477 * bits: 8:8 = 1'b0 - separate OE from Output delay setting
479 const u32 value
= (0 << 8) | (0 << 7) | (1 << 5) |
480 (1 << 2) | (1 << 1) | (1 << 0);
481 const u32 addr
= SDR_PHYGRP_SCCGRP_ADDRESS
|
482 SCC_MGR_HHP_GLOBALS_OFFSET
|
483 SCC_MGR_HHP_EXTRAS_OFFSET
;
485 debug_cond(DLEVEL
== 1, "%s:%d Setting HHP Extras\n",
488 debug_cond(DLEVEL
== 1, "%s:%d Done Setting HHP Extras\n",
493 * scc_mgr_zero_all() - Zero all DQS config
495 * Zero all DQS config.
497 static void scc_mgr_zero_all(void)
502 * USER Zero all DQS config settings, across all groups and all
505 for (r
= 0; r
< rwcfg
->mem_number_of_ranks
;
506 r
+= NUM_RANKS_PER_SHADOW_REG
) {
507 for (i
= 0; i
< rwcfg
->mem_if_read_dqs_width
; i
++) {
509 * The phases actually don't exist on a per-rank basis,
510 * but there's no harm updating them several times, so
511 * let's keep the code simple.
513 scc_mgr_set_dqs_bus_in_delay(i
, iocfg
->dqs_in_reserve
);
514 scc_mgr_set_dqs_en_phase(i
, 0);
515 scc_mgr_set_dqs_en_delay(i
, 0);
518 for (i
= 0; i
< rwcfg
->mem_if_write_dqs_width
; i
++) {
519 scc_mgr_set_dqdqs_output_phase(i
, 0);
520 /* Arria V/Cyclone V don't have out2. */
521 scc_mgr_set_oct_out1_delay(i
, iocfg
->dqs_out_reserve
);
525 /* Multicast to all DQS group enables. */
526 writel(0xff, &sdr_scc_mgr
->dqs_ena
);
527 writel(0, &sdr_scc_mgr
->update
);
531 * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
532 * @write_group: Write group
534 * Set bypass mode and trigger SCC update.
536 static void scc_set_bypass_mode(const u32 write_group
)
538 /* Multicast to all DQ enables. */
539 writel(0xff, &sdr_scc_mgr
->dq_ena
);
540 writel(0xff, &sdr_scc_mgr
->dm_ena
);
542 /* Update current DQS IO enable. */
543 writel(0, &sdr_scc_mgr
->dqs_io_ena
);
545 /* Update the DQS logic. */
546 writel(write_group
, &sdr_scc_mgr
->dqs_ena
);
549 writel(0, &sdr_scc_mgr
->update
);
553 * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
554 * @write_group: Write group
556 * Load DQS settings for Write Group, do not trigger SCC update.
558 static void scc_mgr_load_dqs_for_write_group(const u32 write_group
)
560 const int ratio
= rwcfg
->mem_if_read_dqs_width
/
561 rwcfg
->mem_if_write_dqs_width
;
562 const int base
= write_group
* ratio
;
565 * Load the setting in the SCC manager
566 * Although OCT affects only write data, the OCT delay is controlled
567 * by the DQS logic block which is instantiated once per read group.
568 * For protocols where a write group consists of multiple read groups,
569 * the setting must be set multiple times.
571 for (i
= 0; i
< ratio
; i
++)
572 writel(base
+ i
, &sdr_scc_mgr
->dqs_ena
);
576 * scc_mgr_zero_group() - Zero all configs for a group
578 * Zero DQ, DM, DQS and OCT configs for a group.
580 static void scc_mgr_zero_group(const u32 write_group
, const int out_only
)
584 for (r
= 0; r
< rwcfg
->mem_number_of_ranks
;
585 r
+= NUM_RANKS_PER_SHADOW_REG
) {
586 /* Zero all DQ config settings. */
587 for (i
= 0; i
< rwcfg
->mem_dq_per_write_dqs
; i
++) {
588 scc_mgr_set_dq_out1_delay(i
, 0);
590 scc_mgr_set_dq_in_delay(i
, 0);
593 /* Multicast to all DQ enables. */
594 writel(0xff, &sdr_scc_mgr
->dq_ena
);
596 /* Zero all DM config settings. */
597 for (i
= 0; i
< RW_MGR_NUM_DM_PER_WRITE_GROUP
; i
++)
598 scc_mgr_set_dm_out1_delay(i
, 0);
600 /* Multicast to all DM enables. */
601 writel(0xff, &sdr_scc_mgr
->dm_ena
);
603 /* Zero all DQS IO settings. */
605 scc_mgr_set_dqs_io_in_delay(0);
607 /* Arria V/Cyclone V don't have out2. */
608 scc_mgr_set_dqs_out1_delay(iocfg
->dqs_out_reserve
);
609 scc_mgr_set_oct_out1_delay(write_group
, iocfg
->dqs_out_reserve
);
610 scc_mgr_load_dqs_for_write_group(write_group
);
612 /* Multicast to all DQS IO enables (only 1 in total). */
613 writel(0, &sdr_scc_mgr
->dqs_io_ena
);
615 /* Hit update to zero everything. */
616 writel(0, &sdr_scc_mgr
->update
);
621 * apply and load a particular input delay for the DQ pins in a group
622 * group_bgn is the index of the first dq pin (in the write group)
624 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn
, uint32_t delay
)
628 for (i
= 0, p
= group_bgn
; i
< rwcfg
->mem_dq_per_read_dqs
; i
++, p
++) {
629 scc_mgr_set_dq_in_delay(p
, delay
);
635 * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
636 * @delay: Delay value
638 * Apply and load a particular output delay for the DQ pins in a group.
640 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay
)
644 for (i
= 0; i
< rwcfg
->mem_dq_per_write_dqs
; i
++) {
645 scc_mgr_set_dq_out1_delay(i
, delay
);
650 /* apply and load a particular output delay for the DM pins in a group */
651 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1
)
655 for (i
= 0; i
< RW_MGR_NUM_DM_PER_WRITE_GROUP
; i
++) {
656 scc_mgr_set_dm_out1_delay(i
, delay1
);
662 /* apply and load delay on both DQS and OCT out1 */
663 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group
,
666 scc_mgr_set_dqs_out1_delay(delay
);
667 scc_mgr_load_dqs_io();
669 scc_mgr_set_oct_out1_delay(write_group
, delay
);
670 scc_mgr_load_dqs_for_write_group(write_group
);
674 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
675 * @write_group: Write group
676 * @delay: Delay value
678 * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
680 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group
,
686 for (i
= 0; i
< rwcfg
->mem_dq_per_write_dqs
; i
++)
690 for (i
= 0; i
< RW_MGR_NUM_DM_PER_WRITE_GROUP
; i
++)
694 new_delay
= READ_SCC_DQS_IO_OUT2_DELAY
+ delay
;
695 if (new_delay
> iocfg
->io_out2_delay_max
) {
696 debug_cond(DLEVEL
== 1,
697 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
698 __func__
, __LINE__
, write_group
, delay
, new_delay
,
699 iocfg
->io_out2_delay_max
,
700 new_delay
- iocfg
->io_out2_delay_max
);
701 new_delay
-= iocfg
->io_out2_delay_max
;
702 scc_mgr_set_dqs_out1_delay(new_delay
);
705 scc_mgr_load_dqs_io();
708 new_delay
= READ_SCC_OCT_OUT2_DELAY
+ delay
;
709 if (new_delay
> iocfg
->io_out2_delay_max
) {
710 debug_cond(DLEVEL
== 1,
711 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
712 __func__
, __LINE__
, write_group
, delay
,
713 new_delay
, iocfg
->io_out2_delay_max
,
714 new_delay
- iocfg
->io_out2_delay_max
);
715 new_delay
-= iocfg
->io_out2_delay_max
;
716 scc_mgr_set_oct_out1_delay(write_group
, new_delay
);
719 scc_mgr_load_dqs_for_write_group(write_group
);
723 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
724 * @write_group: Write group
725 * @delay: Delay value
727 * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
730 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group
,
735 for (r
= 0; r
< rwcfg
->mem_number_of_ranks
;
736 r
+= NUM_RANKS_PER_SHADOW_REG
) {
737 scc_mgr_apply_group_all_out_delay_add(write_group
, delay
);
738 writel(0, &sdr_scc_mgr
->update
);
743 * set_jump_as_return() - Return instruction optimization
745 * Optimization used to recover some slots in ddr3 inst_rom could be
746 * applied to other protocols if we wanted to
748 static void set_jump_as_return(void)
751 * To save space, we replace return with jump to special shared
752 * RETURN instruction so we set the counter to large value so that
755 writel(0xff, &sdr_rw_load_mgr_regs
->load_cntr0
);
756 writel(rwcfg
->rreturn
, &sdr_rw_load_jump_mgr_regs
->load_jump_add0
);
760 * delay_for_n_mem_clocks() - Delay for N memory clocks
761 * @clocks: Length of the delay
763 * Delay for N memory clocks.
765 static void delay_for_n_mem_clocks(const u32 clocks
)
772 debug("%s:%d: clocks=%u ... start\n", __func__
, __LINE__
, clocks
);
774 /* Scale (rounding up) to get afi clocks. */
775 afi_clocks
= DIV_ROUND_UP(clocks
, AFI_RATE_RATIO
);
776 if (afi_clocks
) /* Temporary underflow protection */
780 * Note, we don't bother accounting for being off a little
781 * bit because of a few extra instructions in outer loops.
782 * Note, the loops have a test at the end, and do the test
783 * before the decrement, and so always perform the loop
784 * 1 time more than the counter value
786 c_loop
= afi_clocks
>> 16;
787 outer
= c_loop
? 0xff : (afi_clocks
>> 8);
788 inner
= outer
? 0xff : afi_clocks
;
791 * rom instructions are structured as follows:
793 * IDLE_LOOP2: jnz cntr0, TARGET_A
794 * IDLE_LOOP1: jnz cntr1, TARGET_B
797 * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
798 * TARGET_B is set to IDLE_LOOP2 as well
800 * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
801 * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
803 * a little confusing, but it helps save precious space in the inst_rom
804 * and sequencer rom and keeps the delays more accurate and reduces
807 if (afi_clocks
< 0x100) {
808 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner
),
809 &sdr_rw_load_mgr_regs
->load_cntr1
);
811 writel(rwcfg
->idle_loop1
,
812 &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
814 writel(rwcfg
->idle_loop1
, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
815 RW_MGR_RUN_SINGLE_GROUP_OFFSET
);
817 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner
),
818 &sdr_rw_load_mgr_regs
->load_cntr0
);
820 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer
),
821 &sdr_rw_load_mgr_regs
->load_cntr1
);
823 writel(rwcfg
->idle_loop2
,
824 &sdr_rw_load_jump_mgr_regs
->load_jump_add0
);
826 writel(rwcfg
->idle_loop2
,
827 &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
830 writel(rwcfg
->idle_loop2
,
831 SDR_PHYGRP_RWMGRGRP_ADDRESS
|
832 RW_MGR_RUN_SINGLE_GROUP_OFFSET
);
833 } while (c_loop
-- != 0);
835 debug("%s:%d clocks=%u ... end\n", __func__
, __LINE__
, clocks
);
839 * rw_mgr_mem_init_load_regs() - Load instruction registers
840 * @cntr0: Counter 0 value
841 * @cntr1: Counter 1 value
842 * @cntr2: Counter 2 value
843 * @jump: Jump instruction value
845 * Load instruction registers.
847 static void rw_mgr_mem_init_load_regs(u32 cntr0
, u32 cntr1
, u32 cntr2
, u32 jump
)
849 uint32_t grpaddr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
|
850 RW_MGR_RUN_SINGLE_GROUP_OFFSET
;
853 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0
),
854 &sdr_rw_load_mgr_regs
->load_cntr0
);
855 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1
),
856 &sdr_rw_load_mgr_regs
->load_cntr1
);
857 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2
),
858 &sdr_rw_load_mgr_regs
->load_cntr2
);
860 /* Load jump address */
861 writel(jump
, &sdr_rw_load_jump_mgr_regs
->load_jump_add0
);
862 writel(jump
, &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
863 writel(jump
, &sdr_rw_load_jump_mgr_regs
->load_jump_add2
);
865 /* Execute count instruction */
866 writel(jump
, grpaddr
);
870 * rw_mgr_mem_load_user() - Load user calibration values
871 * @fin1: Final instruction 1
872 * @fin2: Final instruction 2
873 * @precharge: If 1, precharge the banks at the end
875 * Load user calibration values and optionally precharge the banks.
877 static void rw_mgr_mem_load_user(const u32 fin1
, const u32 fin2
,
880 u32 grpaddr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
|
881 RW_MGR_RUN_SINGLE_GROUP_OFFSET
;
884 for (r
= 0; r
< rwcfg
->mem_number_of_ranks
; r
++) {
886 set_rank_and_odt_mask(r
, RW_MGR_ODT_MODE_OFF
);
888 /* precharge all banks ... */
890 writel(rwcfg
->precharge_all
, grpaddr
);
893 * USER Use Mirror-ed commands for odd ranks if address
896 if ((rwcfg
->mem_address_mirroring
>> r
) & 0x1) {
897 set_jump_as_return();
898 writel(rwcfg
->mrs2_mirr
, grpaddr
);
899 delay_for_n_mem_clocks(4);
900 set_jump_as_return();
901 writel(rwcfg
->mrs3_mirr
, grpaddr
);
902 delay_for_n_mem_clocks(4);
903 set_jump_as_return();
904 writel(rwcfg
->mrs1_mirr
, grpaddr
);
905 delay_for_n_mem_clocks(4);
906 set_jump_as_return();
907 writel(fin1
, grpaddr
);
909 set_jump_as_return();
910 writel(rwcfg
->mrs2
, grpaddr
);
911 delay_for_n_mem_clocks(4);
912 set_jump_as_return();
913 writel(rwcfg
->mrs3
, grpaddr
);
914 delay_for_n_mem_clocks(4);
915 set_jump_as_return();
916 writel(rwcfg
->mrs1
, grpaddr
);
917 set_jump_as_return();
918 writel(fin2
, grpaddr
);
924 set_jump_as_return();
925 writel(rwcfg
->zqcl
, grpaddr
);
927 /* tZQinit = tDLLK = 512 ck cycles */
928 delay_for_n_mem_clocks(512);
933 * rw_mgr_mem_initialize() - Initialize RW Manager
935 * Initialize RW Manager.
937 static void rw_mgr_mem_initialize(void)
939 debug("%s:%d\n", __func__
, __LINE__
);
941 /* The reset / cke part of initialization is broadcasted to all ranks */
942 writel(RW_MGR_RANK_ALL
, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
943 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET
);
946 * Here's how you load register for a loop
947 * Counters are located @ 0x800
948 * Jump address are located @ 0xC00
949 * For both, registers 0 to 3 are selected using bits 3 and 2, like
950 * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
951 * I know this ain't pretty, but Avalon bus throws away the 2 least
955 /* Start with memory RESET activated */
960 * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
961 * If a and b are the number of iteration in 2 nested loops
962 * it takes the following number of cycles to complete the operation:
963 * number_of_cycles = ((2 + n) * a + 2) * b
964 * where n is the number of instruction in the inner loop
965 * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
968 rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL
, SEQ_TINIT_CNTR1_VAL
,
970 rwcfg
->init_reset_0_cke_0
);
972 /* Indicate that memory is stable. */
973 writel(1, &phy_mgr_cfg
->reset_mem_stbl
);
976 * transition the RESET to high
981 * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
982 * If a and b are the number of iteration in 2 nested loops
983 * it takes the following number of cycles to complete the operation
984 * number_of_cycles = ((2 + n) * a + 2) * b
985 * where n is the number of instruction in the inner loop
986 * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
989 rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL
, SEQ_TRESET_CNTR1_VAL
,
990 SEQ_TRESET_CNTR2_VAL
,
991 rwcfg
->init_reset_1_cke_0
);
993 /* Bring up clock enable. */
995 /* tXRP < 250 ck cycles */
996 delay_for_n_mem_clocks(250);
998 rw_mgr_mem_load_user(rwcfg
->mrs0_dll_reset_mirr
, rwcfg
->mrs0_dll_reset
,
1003 * rw_mgr_mem_handoff() - Hand off the memory to user
1005 * At the end of calibration we have to program the user settings in
1006 * and hand off the memory to the user.
1008 static void rw_mgr_mem_handoff(void)
1010 rw_mgr_mem_load_user(rwcfg
->mrs0_user_mirr
, rwcfg
->mrs0_user
, 1);
1012 * Need to wait tMOD (12CK or 15ns) time before issuing other
1013 * commands, but we will have plenty of NIOS cycles before actual
1014 * handoff so its okay.
1019 * rw_mgr_mem_calibrate_write_test_issue() - Issue write test command
1020 * @group: Write Group
1023 * Issue write test command. Two variants are provided, one that just tests
1024 * a write pattern and another that tests datamask functionality.
1026 static void rw_mgr_mem_calibrate_write_test_issue(u32 group
,
1029 const u32 quick_write_mode
=
1030 (STATIC_CALIB_STEPS
& CALIB_SKIP_WRITES
) &&
1031 ENABLE_SUPER_QUICK_CALIBRATION
;
1032 u32 mcc_instruction
;
1033 u32 rw_wl_nop_cycles
;
1036 * Set counter and jump addresses for the right
1037 * number of NOP cycles.
1038 * The number of supported NOP cycles can range from -1 to infinity
1039 * Three different cases are handled:
1041 * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
1042 * mechanism will be used to insert the right number of NOPs
1044 * 2. For a number of NOP cycles equals to 0, the micro-instruction
1045 * issuing the write command will jump straight to the
1046 * micro-instruction that turns on DQS (for DDRx), or outputs write
1047 * data (for RLD), skipping
1048 * the NOP micro-instruction all together
1050 * 3. A number of NOP cycles equal to -1 indicates that DQS must be
1051 * turned on in the same micro-instruction that issues the write
1052 * command. Then we need
1053 * to directly jump to the micro-instruction that sends out the data
1055 * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
1056 * (2 and 3). One jump-counter (0) is used to perform multiple
1057 * write-read operations.
1058 * one counter left to issue this command in "multiple-group" mode
1061 rw_wl_nop_cycles
= gbl
->rw_wl_nop_cycles
;
1063 if (rw_wl_nop_cycles
== -1) {
1065 * CNTR 2 - We want to execute the special write operation that
1066 * turns on DQS right away and then skip directly to the
1067 * instruction that sends out the data. We set the counter to a
1068 * large number so that the jump is always taken.
1070 writel(0xFF, &sdr_rw_load_mgr_regs
->load_cntr2
);
1072 /* CNTR 3 - Not used */
1074 mcc_instruction
= rwcfg
->lfsr_wr_rd_dm_bank_0_wl_1
;
1075 writel(rwcfg
->lfsr_wr_rd_dm_bank_0_data
,
1076 &sdr_rw_load_jump_mgr_regs
->load_jump_add2
);
1077 writel(rwcfg
->lfsr_wr_rd_dm_bank_0_nop
,
1078 &sdr_rw_load_jump_mgr_regs
->load_jump_add3
);
1080 mcc_instruction
= rwcfg
->lfsr_wr_rd_bank_0_wl_1
;
1081 writel(rwcfg
->lfsr_wr_rd_bank_0_data
,
1082 &sdr_rw_load_jump_mgr_regs
->load_jump_add2
);
1083 writel(rwcfg
->lfsr_wr_rd_bank_0_nop
,
1084 &sdr_rw_load_jump_mgr_regs
->load_jump_add3
);
1086 } else if (rw_wl_nop_cycles
== 0) {
1088 * CNTR 2 - We want to skip the NOP operation and go straight
1089 * to the DQS enable instruction. We set the counter to a large
1090 * number so that the jump is always taken.
1092 writel(0xFF, &sdr_rw_load_mgr_regs
->load_cntr2
);
1094 /* CNTR 3 - Not used */
1096 mcc_instruction
= rwcfg
->lfsr_wr_rd_dm_bank_0
;
1097 writel(rwcfg
->lfsr_wr_rd_dm_bank_0_dqs
,
1098 &sdr_rw_load_jump_mgr_regs
->load_jump_add2
);
1100 mcc_instruction
= rwcfg
->lfsr_wr_rd_bank_0
;
1101 writel(rwcfg
->lfsr_wr_rd_bank_0_dqs
,
1102 &sdr_rw_load_jump_mgr_regs
->load_jump_add2
);
1106 * CNTR 2 - In this case we want to execute the next instruction
1107 * and NOT take the jump. So we set the counter to 0. The jump
1108 * address doesn't count.
1110 writel(0x0, &sdr_rw_load_mgr_regs
->load_cntr2
);
1111 writel(0x0, &sdr_rw_load_jump_mgr_regs
->load_jump_add2
);
1114 * CNTR 3 - Set the nop counter to the number of cycles we
1115 * need to loop for, minus 1.
1117 writel(rw_wl_nop_cycles
- 1, &sdr_rw_load_mgr_regs
->load_cntr3
);
1119 mcc_instruction
= rwcfg
->lfsr_wr_rd_dm_bank_0
;
1120 writel(rwcfg
->lfsr_wr_rd_dm_bank_0_nop
,
1121 &sdr_rw_load_jump_mgr_regs
->load_jump_add3
);
1123 mcc_instruction
= rwcfg
->lfsr_wr_rd_bank_0
;
1124 writel(rwcfg
->lfsr_wr_rd_bank_0_nop
,
1125 &sdr_rw_load_jump_mgr_regs
->load_jump_add3
);
1129 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
1130 RW_MGR_RESET_READ_DATAPATH_OFFSET
);
1132 if (quick_write_mode
)
1133 writel(0x08, &sdr_rw_load_mgr_regs
->load_cntr0
);
1135 writel(0x40, &sdr_rw_load_mgr_regs
->load_cntr0
);
1137 writel(mcc_instruction
, &sdr_rw_load_jump_mgr_regs
->load_jump_add0
);
1140 * CNTR 1 - This is used to ensure enough time elapses
1141 * for read data to come back.
1143 writel(0x30, &sdr_rw_load_mgr_regs
->load_cntr1
);
1146 writel(rwcfg
->lfsr_wr_rd_dm_bank_0_wait
,
1147 &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
1149 writel(rwcfg
->lfsr_wr_rd_bank_0_wait
,
1150 &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
1153 writel(mcc_instruction
, (SDR_PHYGRP_RWMGRGRP_ADDRESS
|
1154 RW_MGR_RUN_SINGLE_GROUP_OFFSET
) +
1159 * rw_mgr_mem_calibrate_write_test() - Test writes, check for single/multiple pass
1160 * @rank_bgn: Rank number
1161 * @write_group: Write Group
1163 * @all_correct: All bits must be correct in the mask
1164 * @bit_chk: Resulting bit mask after the test
1165 * @all_ranks: Test all ranks
1167 * Test writes, can check for a single bit pass or multiple bit pass.
1170 rw_mgr_mem_calibrate_write_test(const u32 rank_bgn
, const u32 write_group
,
1171 const u32 use_dm
, const u32 all_correct
,
1172 u32
*bit_chk
, const u32 all_ranks
)
1174 const u32 rank_end
= all_ranks
?
1175 rwcfg
->mem_number_of_ranks
:
1176 (rank_bgn
+ NUM_RANKS_PER_SHADOW_REG
);
1177 const u32 shift_ratio
= rwcfg
->mem_dq_per_write_dqs
/
1178 rwcfg
->mem_virtual_groups_per_write_dqs
;
1179 const u32 correct_mask_vg
= param
->write_correct_mask_vg
;
1181 u32 tmp_bit_chk
, base_rw_mgr
;
1184 *bit_chk
= param
->write_correct_mask
;
1186 for (r
= rank_bgn
; r
< rank_end
; r
++) {
1188 set_rank_and_odt_mask(r
, RW_MGR_ODT_MODE_READ_WRITE
);
1191 for (vg
= rwcfg
->mem_virtual_groups_per_write_dqs
- 1;
1193 /* Reset the FIFOs to get pointers to known state. */
1194 writel(0, &phy_mgr_cmd
->fifo_reset
);
1196 rw_mgr_mem_calibrate_write_test_issue(
1198 rwcfg
->mem_virtual_groups_per_write_dqs
+ vg
,
1201 base_rw_mgr
= readl(SDR_PHYGRP_RWMGRGRP_ADDRESS
);
1202 tmp_bit_chk
<<= shift_ratio
;
1203 tmp_bit_chk
|= (correct_mask_vg
& ~(base_rw_mgr
));
1206 *bit_chk
&= tmp_bit_chk
;
1209 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF
);
1211 debug_cond(DLEVEL
== 2,
1212 "write_test(%u,%u,ALL) : %u == %u => %i\n",
1213 write_group
, use_dm
, *bit_chk
,
1214 param
->write_correct_mask
,
1215 *bit_chk
== param
->write_correct_mask
);
1216 return *bit_chk
== param
->write_correct_mask
;
1218 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF
);
1219 debug_cond(DLEVEL
== 2,
1220 "write_test(%u,%u,ONE) : %u != %i => %i\n",
1221 write_group
, use_dm
, *bit_chk
, 0, *bit_chk
!= 0);
1222 return *bit_chk
!= 0x00;
1227 * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
1228 * @rank_bgn: Rank number
1229 * @group: Read/Write Group
1230 * @all_ranks: Test all ranks
1232 * Performs a guaranteed read on the patterns we are going to use during a
1233 * read test to ensure memory works.
1236 rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn
, const u32 group
,
1237 const u32 all_ranks
)
1239 const u32 addr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
|
1240 RW_MGR_RUN_SINGLE_GROUP_OFFSET
;
1241 const u32 addr_offset
=
1242 (group
* rwcfg
->mem_virtual_groups_per_read_dqs
) << 2;
1243 const u32 rank_end
= all_ranks
?
1244 rwcfg
->mem_number_of_ranks
:
1245 (rank_bgn
+ NUM_RANKS_PER_SHADOW_REG
);
1246 const u32 shift_ratio
= rwcfg
->mem_dq_per_read_dqs
/
1247 rwcfg
->mem_virtual_groups_per_read_dqs
;
1248 const u32 correct_mask_vg
= param
->read_correct_mask_vg
;
1250 u32 tmp_bit_chk
, base_rw_mgr
, bit_chk
;
1254 bit_chk
= param
->read_correct_mask
;
1256 for (r
= rank_bgn
; r
< rank_end
; r
++) {
1258 set_rank_and_odt_mask(r
, RW_MGR_ODT_MODE_READ_WRITE
);
1260 /* Load up a constant bursts of read commands */
1261 writel(0x20, &sdr_rw_load_mgr_regs
->load_cntr0
);
1262 writel(rwcfg
->guaranteed_read
,
1263 &sdr_rw_load_jump_mgr_regs
->load_jump_add0
);
1265 writel(0x20, &sdr_rw_load_mgr_regs
->load_cntr1
);
1266 writel(rwcfg
->guaranteed_read_cont
,
1267 &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
1270 for (vg
= rwcfg
->mem_virtual_groups_per_read_dqs
- 1;
1272 /* Reset the FIFOs to get pointers to known state. */
1273 writel(0, &phy_mgr_cmd
->fifo_reset
);
1274 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
1275 RW_MGR_RESET_READ_DATAPATH_OFFSET
);
1276 writel(rwcfg
->guaranteed_read
,
1277 addr
+ addr_offset
+ (vg
<< 2));
1279 base_rw_mgr
= readl(SDR_PHYGRP_RWMGRGRP_ADDRESS
);
1280 tmp_bit_chk
<<= shift_ratio
;
1281 tmp_bit_chk
|= correct_mask_vg
& ~base_rw_mgr
;
1284 bit_chk
&= tmp_bit_chk
;
1287 writel(rwcfg
->clear_dqs_enable
, addr
+ (group
<< 2));
1289 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF
);
1291 if (bit_chk
!= param
->read_correct_mask
)
1294 debug_cond(DLEVEL
== 1,
1295 "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
1296 __func__
, __LINE__
, group
, bit_chk
,
1297 param
->read_correct_mask
, ret
);
1303 * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
1304 * @rank_bgn: Rank number
1305 * @all_ranks: Test all ranks
1307 * Load up the patterns we are going to use during a read test.
1309 static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn
,
1310 const int all_ranks
)
1312 const u32 rank_end
= all_ranks
?
1313 rwcfg
->mem_number_of_ranks
:
1314 (rank_bgn
+ NUM_RANKS_PER_SHADOW_REG
);
1317 debug("%s:%d\n", __func__
, __LINE__
);
1319 for (r
= rank_bgn
; r
< rank_end
; r
++) {
1321 set_rank_and_odt_mask(r
, RW_MGR_ODT_MODE_READ_WRITE
);
1323 /* Load up a constant bursts */
1324 writel(0x20, &sdr_rw_load_mgr_regs
->load_cntr0
);
1326 writel(rwcfg
->guaranteed_write_wait0
,
1327 &sdr_rw_load_jump_mgr_regs
->load_jump_add0
);
1329 writel(0x20, &sdr_rw_load_mgr_regs
->load_cntr1
);
1331 writel(rwcfg
->guaranteed_write_wait1
,
1332 &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
1334 writel(0x04, &sdr_rw_load_mgr_regs
->load_cntr2
);
1336 writel(rwcfg
->guaranteed_write_wait2
,
1337 &sdr_rw_load_jump_mgr_regs
->load_jump_add2
);
1339 writel(0x04, &sdr_rw_load_mgr_regs
->load_cntr3
);
1341 writel(rwcfg
->guaranteed_write_wait3
,
1342 &sdr_rw_load_jump_mgr_regs
->load_jump_add3
);
1344 writel(rwcfg
->guaranteed_write
, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
1345 RW_MGR_RUN_SINGLE_GROUP_OFFSET
);
1348 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF
);
1352 * rw_mgr_mem_calibrate_read_test() - Perform READ test on single rank
1353 * @rank_bgn: Rank number
1354 * @group: Read/Write group
1355 * @num_tries: Number of retries of the test
1356 * @all_correct: All bits must be correct in the mask
1357 * @bit_chk: Resulting bit mask after the test
1358 * @all_groups: Test all R/W groups
1359 * @all_ranks: Test all ranks
1361 * Try a read and see if it returns correct data back. Test has dummy reads
1362 * inserted into the mix used to align DQS enable. Test has more thorough
1363 * checks than the regular read test.
1366 rw_mgr_mem_calibrate_read_test(const u32 rank_bgn
, const u32 group
,
1367 const u32 num_tries
, const u32 all_correct
,
1369 const u32 all_groups
, const u32 all_ranks
)
1371 const u32 rank_end
= all_ranks
? rwcfg
->mem_number_of_ranks
:
1372 (rank_bgn
+ NUM_RANKS_PER_SHADOW_REG
);
1373 const u32 quick_read_mode
=
1374 ((STATIC_CALIB_STEPS
& CALIB_SKIP_DELAY_SWEEPS
) &&
1375 ENABLE_SUPER_QUICK_CALIBRATION
);
1376 u32 correct_mask_vg
= param
->read_correct_mask_vg
;
1383 *bit_chk
= param
->read_correct_mask
;
1385 for (r
= rank_bgn
; r
< rank_end
; r
++) {
1387 set_rank_and_odt_mask(r
, RW_MGR_ODT_MODE_READ_WRITE
);
1389 writel(0x10, &sdr_rw_load_mgr_regs
->load_cntr1
);
1391 writel(rwcfg
->read_b2b_wait1
,
1392 &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
1394 writel(0x10, &sdr_rw_load_mgr_regs
->load_cntr2
);
1395 writel(rwcfg
->read_b2b_wait2
,
1396 &sdr_rw_load_jump_mgr_regs
->load_jump_add2
);
1398 if (quick_read_mode
)
1399 writel(0x1, &sdr_rw_load_mgr_regs
->load_cntr0
);
1400 /* need at least two (1+1) reads to capture failures */
1401 else if (all_groups
)
1402 writel(0x06, &sdr_rw_load_mgr_regs
->load_cntr0
);
1404 writel(0x32, &sdr_rw_load_mgr_regs
->load_cntr0
);
1406 writel(rwcfg
->read_b2b
,
1407 &sdr_rw_load_jump_mgr_regs
->load_jump_add0
);
1409 writel(rwcfg
->mem_if_read_dqs_width
*
1410 rwcfg
->mem_virtual_groups_per_read_dqs
- 1,
1411 &sdr_rw_load_mgr_regs
->load_cntr3
);
1413 writel(0x0, &sdr_rw_load_mgr_regs
->load_cntr3
);
1415 writel(rwcfg
->read_b2b
,
1416 &sdr_rw_load_jump_mgr_regs
->load_jump_add3
);
1419 for (vg
= rwcfg
->mem_virtual_groups_per_read_dqs
- 1; vg
>= 0;
1421 /* Reset the FIFOs to get pointers to known state. */
1422 writel(0, &phy_mgr_cmd
->fifo_reset
);
1423 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
1424 RW_MGR_RESET_READ_DATAPATH_OFFSET
);
1427 addr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
|
1428 RW_MGR_RUN_ALL_GROUPS_OFFSET
;
1430 addr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
|
1431 RW_MGR_RUN_SINGLE_GROUP_OFFSET
;
1434 writel(rwcfg
->read_b2b
, addr
+
1435 ((group
* rwcfg
->mem_virtual_groups_per_read_dqs
+
1438 base_rw_mgr
= readl(SDR_PHYGRP_RWMGRGRP_ADDRESS
);
1439 tmp_bit_chk
<<= rwcfg
->mem_dq_per_read_dqs
/
1440 rwcfg
->mem_virtual_groups_per_read_dqs
;
1441 tmp_bit_chk
|= correct_mask_vg
& ~(base_rw_mgr
);
1444 *bit_chk
&= tmp_bit_chk
;
1447 addr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
| RW_MGR_RUN_SINGLE_GROUP_OFFSET
;
1448 writel(rwcfg
->clear_dqs_enable
, addr
+ (group
<< 2));
1450 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF
);
1453 ret
= (*bit_chk
== param
->read_correct_mask
);
1454 debug_cond(DLEVEL
== 2,
1455 "%s:%d read_test(%u,ALL,%u) => (%u == %u) => %i\n",
1456 __func__
, __LINE__
, group
, all_groups
, *bit_chk
,
1457 param
->read_correct_mask
, ret
);
1459 ret
= (*bit_chk
!= 0x00);
1460 debug_cond(DLEVEL
== 2,
1461 "%s:%d read_test(%u,ONE,%u) => (%u != %u) => %i\n",
1462 __func__
, __LINE__
, group
, all_groups
, *bit_chk
,
1470 * rw_mgr_mem_calibrate_read_test_all_ranks() - Perform READ test on all ranks
1471 * @grp: Read/Write group
1472 * @num_tries: Number of retries of the test
1473 * @all_correct: All bits must be correct in the mask
1474 * @all_groups: Test all R/W groups
1476 * Perform a READ test across all memory ranks.
1479 rw_mgr_mem_calibrate_read_test_all_ranks(const u32 grp
, const u32 num_tries
,
1480 const u32 all_correct
,
1481 const u32 all_groups
)
1484 return rw_mgr_mem_calibrate_read_test(0, grp
, num_tries
, all_correct
,
1485 &bit_chk
, all_groups
, 1);
1489 * rw_mgr_incr_vfifo() - Increase VFIFO value
1490 * @grp: Read/Write group
1492 * Increase VFIFO value.
1494 static void rw_mgr_incr_vfifo(const u32 grp
)
1496 writel(grp
, &phy_mgr_cmd
->inc_vfifo_hard_phy
);
1500 * rw_mgr_decr_vfifo() - Decrease VFIFO value
1501 * @grp: Read/Write group
1503 * Decrease VFIFO value.
1505 static void rw_mgr_decr_vfifo(const u32 grp
)
1509 for (i
= 0; i
< VFIFO_SIZE
- 1; i
++)
1510 rw_mgr_incr_vfifo(grp
);
1514 * find_vfifo_failing_read() - Push VFIFO to get a failing read
1515 * @grp: Read/Write group
1517 * Push VFIFO until a failing read happens.
1519 static int find_vfifo_failing_read(const u32 grp
)
1521 u32 v
, ret
, fail_cnt
= 0;
1523 for (v
= 0; v
< VFIFO_SIZE
; v
++) {
1524 debug_cond(DLEVEL
== 2, "%s:%d: vfifo %u\n",
1525 __func__
, __LINE__
, v
);
1526 ret
= rw_mgr_mem_calibrate_read_test_all_ranks(grp
, 1,
1535 /* Fiddle with FIFO. */
1536 rw_mgr_incr_vfifo(grp
);
1539 /* No failing read found! Something must have gone wrong. */
1540 debug_cond(DLEVEL
== 2, "%s:%d: vfifo failed\n", __func__
, __LINE__
);
1545 * sdr_find_phase_delay() - Find DQS enable phase or delay
1546 * @working: If 1, look for working phase/delay, if 0, look for non-working
1547 * @delay: If 1, look for delay, if 0, look for phase
1548 * @grp: Read/Write group
1549 * @work: Working window position
1550 * @work_inc: Working window increment
1551 * @pd: DQS Phase/Delay Iterator
1553 * Find working or non-working DQS enable phase setting.
1555 static int sdr_find_phase_delay(int working
, int delay
, const u32 grp
,
1556 u32
*work
, const u32 work_inc
, u32
*pd
)
1558 const u32 max
= delay
? iocfg
->dqs_en_delay_max
: iocfg
->dqs_en_phase_max
;
1561 for (; *pd
<= max
; (*pd
)++) {
1563 scc_mgr_set_dqs_en_delay_all_ranks(grp
, *pd
);
1565 scc_mgr_set_dqs_en_phase_all_ranks(grp
, *pd
);
1567 ret
= rw_mgr_mem_calibrate_read_test_all_ranks(grp
, 1,
1582 * sdr_find_phase() - Find DQS enable phase
1583 * @working: If 1, look for working phase, if 0, look for non-working phase
1584 * @grp: Read/Write group
1585 * @work: Working window position
1587 * @p: DQS Phase Iterator
1589 * Find working or non-working DQS enable phase setting.
1591 static int sdr_find_phase(int working
, const u32 grp
, u32
*work
,
1594 const u32 end
= VFIFO_SIZE
+ (working
? 0 : 1);
1597 for (; *i
< end
; (*i
)++) {
1601 ret
= sdr_find_phase_delay(working
, 0, grp
, work
,
1602 iocfg
->delay_per_opa_tap
, p
);
1606 if (*p
> iocfg
->dqs_en_phase_max
) {
1607 /* Fiddle with FIFO. */
1608 rw_mgr_incr_vfifo(grp
);
1618 * sdr_working_phase() - Find working DQS enable phase
1619 * @grp: Read/Write group
1620 * @work_bgn: Working window start position
1621 * @d: dtaps output value
1622 * @p: DQS Phase Iterator
1625 * Find working DQS enable phase setting.
1627 static int sdr_working_phase(const u32 grp
, u32
*work_bgn
, u32
*d
,
1630 const u32 dtaps_per_ptap
= iocfg
->delay_per_opa_tap
/
1631 iocfg
->delay_per_dqs_en_dchain_tap
;
1636 for (*d
= 0; *d
<= dtaps_per_ptap
; (*d
)++) {
1638 scc_mgr_set_dqs_en_delay_all_ranks(grp
, *d
);
1639 ret
= sdr_find_phase(1, grp
, work_bgn
, i
, p
);
1642 *work_bgn
+= iocfg
->delay_per_dqs_en_dchain_tap
;
1645 /* Cannot find working solution */
1646 debug_cond(DLEVEL
== 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
1647 __func__
, __LINE__
);
1652 * sdr_backup_phase() - Find DQS enable backup phase
1653 * @grp: Read/Write group
1654 * @work_bgn: Working window start position
1655 * @p: DQS Phase Iterator
1657 * Find DQS enable backup phase setting.
1659 static void sdr_backup_phase(const u32 grp
, u32
*work_bgn
, u32
*p
)
1664 /* Special case code for backing up a phase */
1666 *p
= iocfg
->dqs_en_phase_max
;
1667 rw_mgr_decr_vfifo(grp
);
1671 tmp_delay
= *work_bgn
- iocfg
->delay_per_opa_tap
;
1672 scc_mgr_set_dqs_en_phase_all_ranks(grp
, *p
);
1674 for (d
= 0; d
<= iocfg
->dqs_en_delay_max
&& tmp_delay
< *work_bgn
; d
++) {
1675 scc_mgr_set_dqs_en_delay_all_ranks(grp
, d
);
1677 ret
= rw_mgr_mem_calibrate_read_test_all_ranks(grp
, 1,
1680 *work_bgn
= tmp_delay
;
1684 tmp_delay
+= iocfg
->delay_per_dqs_en_dchain_tap
;
1687 /* Restore VFIFO to old state before we decremented it (if needed). */
1689 if (*p
> iocfg
->dqs_en_phase_max
) {
1691 rw_mgr_incr_vfifo(grp
);
1694 scc_mgr_set_dqs_en_delay_all_ranks(grp
, 0);
1698 * sdr_nonworking_phase() - Find non-working DQS enable phase
1699 * @grp: Read/Write group
1700 * @work_end: Working window end position
1701 * @p: DQS Phase Iterator
1704 * Find non-working DQS enable phase setting.
1706 static int sdr_nonworking_phase(const u32 grp
, u32
*work_end
, u32
*p
, u32
*i
)
1711 *work_end
+= iocfg
->delay_per_opa_tap
;
1712 if (*p
> iocfg
->dqs_en_phase_max
) {
1713 /* Fiddle with FIFO. */
1715 rw_mgr_incr_vfifo(grp
);
1718 ret
= sdr_find_phase(0, grp
, work_end
, i
, p
);
1720 /* Cannot see edge of failing read. */
1721 debug_cond(DLEVEL
== 2, "%s:%d: end: failed\n",
1722 __func__
, __LINE__
);
1729 * sdr_find_window_center() - Find center of the working DQS window.
1730 * @grp: Read/Write group
1731 * @work_bgn: First working settings
1732 * @work_end: Last working settings
1734 * Find center of the working DQS enable window.
1736 static int sdr_find_window_center(const u32 grp
, const u32 work_bgn
,
1743 work_mid
= (work_bgn
+ work_end
) / 2;
1745 debug_cond(DLEVEL
== 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1746 work_bgn
, work_end
, work_mid
);
1747 /* Get the middle delay to be less than a VFIFO delay */
1748 tmp_delay
= (iocfg
->dqs_en_phase_max
+ 1) * iocfg
->delay_per_opa_tap
;
1750 debug_cond(DLEVEL
== 2, "vfifo ptap delay %d\n", tmp_delay
);
1751 work_mid
%= tmp_delay
;
1752 debug_cond(DLEVEL
== 2, "new work_mid %d\n", work_mid
);
1754 tmp_delay
= rounddown(work_mid
, iocfg
->delay_per_opa_tap
);
1755 if (tmp_delay
> iocfg
->dqs_en_phase_max
* iocfg
->delay_per_opa_tap
)
1756 tmp_delay
= iocfg
->dqs_en_phase_max
* iocfg
->delay_per_opa_tap
;
1757 p
= tmp_delay
/ iocfg
->delay_per_opa_tap
;
1759 debug_cond(DLEVEL
== 2, "new p %d, tmp_delay=%d\n", p
, tmp_delay
);
1761 d
= DIV_ROUND_UP(work_mid
- tmp_delay
, iocfg
->delay_per_dqs_en_dchain_tap
);
1762 if (d
> iocfg
->dqs_en_delay_max
)
1763 d
= iocfg
->dqs_en_delay_max
;
1764 tmp_delay
+= d
* iocfg
->delay_per_dqs_en_dchain_tap
;
1766 debug_cond(DLEVEL
== 2, "new d %d, tmp_delay=%d\n", d
, tmp_delay
);
1768 scc_mgr_set_dqs_en_phase_all_ranks(grp
, p
);
1769 scc_mgr_set_dqs_en_delay_all_ranks(grp
, d
);
1772 * push vfifo until we can successfully calibrate. We can do this
1773 * because the largest possible margin in 1 VFIFO cycle.
1775 for (i
= 0; i
< VFIFO_SIZE
; i
++) {
1776 debug_cond(DLEVEL
== 2, "find_dqs_en_phase: center\n");
1777 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp
, 1,
1780 debug_cond(DLEVEL
== 2,
1781 "%s:%d center: found: ptap=%u dtap=%u\n",
1782 __func__
, __LINE__
, p
, d
);
1786 /* Fiddle with FIFO. */
1787 rw_mgr_incr_vfifo(grp
);
1790 debug_cond(DLEVEL
== 2, "%s:%d center: failed.\n",
1791 __func__
, __LINE__
);
1796 * rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() - Find a good DQS enable to use
1797 * @grp: Read/Write Group
1799 * Find a good DQS enable to use.
1801 static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp
)
1805 u32 work_bgn
, work_end
;
1806 u32 found_passing_read
, found_failing_read
, initial_failing_dtap
;
1809 debug("%s:%d %u\n", __func__
, __LINE__
, grp
);
1811 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER
);
1813 scc_mgr_set_dqs_en_delay_all_ranks(grp
, 0);
1814 scc_mgr_set_dqs_en_phase_all_ranks(grp
, 0);
1816 /* Step 0: Determine number of delay taps for each phase tap. */
1817 dtaps_per_ptap
= iocfg
->delay_per_opa_tap
/ iocfg
->delay_per_dqs_en_dchain_tap
;
1819 /* Step 1: First push vfifo until we get a failing read. */
1820 find_vfifo_failing_read(grp
);
1822 /* Step 2: Find first working phase, increment in ptaps. */
1824 ret
= sdr_working_phase(grp
, &work_bgn
, &d
, &p
, &i
);
1828 work_end
= work_bgn
;
1831 * If d is 0 then the working window covers a phase tap and we can
1832 * follow the old procedure. Otherwise, we've found the beginning
1833 * and we need to increment the dtaps until we find the end.
1837 * Step 3a: If we have room, back off by one and
1838 * increment in dtaps.
1840 sdr_backup_phase(grp
, &work_bgn
, &p
);
1843 * Step 4a: go forward from working phase to non working
1844 * phase, increment in ptaps.
1846 ret
= sdr_nonworking_phase(grp
, &work_end
, &p
, &i
);
1850 /* Step 5a: Back off one from last, increment in dtaps. */
1852 /* Special case code for backing up a phase */
1854 p
= iocfg
->dqs_en_phase_max
;
1855 rw_mgr_decr_vfifo(grp
);
1860 work_end
-= iocfg
->delay_per_opa_tap
;
1861 scc_mgr_set_dqs_en_phase_all_ranks(grp
, p
);
1865 debug_cond(DLEVEL
== 2, "%s:%d p: ptap=%u\n",
1866 __func__
, __LINE__
, p
);
1869 /* The dtap increment to find the failing edge is done here. */
1870 sdr_find_phase_delay(0, 1, grp
, &work_end
,
1871 iocfg
->delay_per_dqs_en_dchain_tap
, &d
);
1873 /* Go back to working dtap */
1875 work_end
-= iocfg
->delay_per_dqs_en_dchain_tap
;
1877 debug_cond(DLEVEL
== 2,
1878 "%s:%d p/d: ptap=%u dtap=%u end=%u\n",
1879 __func__
, __LINE__
, p
, d
- 1, work_end
);
1881 if (work_end
< work_bgn
) {
1883 debug_cond(DLEVEL
== 2, "%s:%d end-2: failed\n",
1884 __func__
, __LINE__
);
1888 debug_cond(DLEVEL
== 2, "%s:%d found range [%u,%u]\n",
1889 __func__
, __LINE__
, work_bgn
, work_end
);
1892 * We need to calculate the number of dtaps that equal a ptap.
1893 * To do that we'll back up a ptap and re-find the edge of the
1894 * window using dtaps
1896 debug_cond(DLEVEL
== 2, "%s:%d calculate dtaps_per_ptap for tracking\n",
1897 __func__
, __LINE__
);
1899 /* Special case code for backing up a phase */
1901 p
= iocfg
->dqs_en_phase_max
;
1902 rw_mgr_decr_vfifo(grp
);
1903 debug_cond(DLEVEL
== 2, "%s:%d backedup cycle/phase: p=%u\n",
1904 __func__
, __LINE__
, p
);
1907 debug_cond(DLEVEL
== 2, "%s:%d backedup phase only: p=%u",
1908 __func__
, __LINE__
, p
);
1911 scc_mgr_set_dqs_en_phase_all_ranks(grp
, p
);
1914 * Increase dtap until we first see a passing read (in case the
1915 * window is smaller than a ptap), and then a failing read to
1916 * mark the edge of the window again.
1919 /* Find a passing read. */
1920 debug_cond(DLEVEL
== 2, "%s:%d find passing read\n",
1921 __func__
, __LINE__
);
1923 initial_failing_dtap
= d
;
1925 found_passing_read
= !sdr_find_phase_delay(1, 1, grp
, NULL
, 0, &d
);
1926 if (found_passing_read
) {
1927 /* Find a failing read. */
1928 debug_cond(DLEVEL
== 2, "%s:%d find failing read\n",
1929 __func__
, __LINE__
);
1931 found_failing_read
= !sdr_find_phase_delay(0, 1, grp
, NULL
, 0,
1934 debug_cond(DLEVEL
== 1,
1935 "%s:%d failed to calculate dtaps per ptap. Fall back on static value\n",
1936 __func__
, __LINE__
);
1940 * The dynamically calculated dtaps_per_ptap is only valid if we
1941 * found a passing/failing read. If we didn't, it means d hit the max
1942 * (iocfg->dqs_en_delay_max). Otherwise, dtaps_per_ptap retains its
1943 * statically calculated value.
1945 if (found_passing_read
&& found_failing_read
)
1946 dtaps_per_ptap
= d
- initial_failing_dtap
;
1948 writel(dtaps_per_ptap
, &sdr_reg_file
->dtaps_per_ptap
);
1949 debug_cond(DLEVEL
== 2, "%s:%d dtaps_per_ptap=%u - %u = %u",
1950 __func__
, __LINE__
, d
, initial_failing_dtap
, dtaps_per_ptap
);
1952 /* Step 6: Find the centre of the window. */
1953 ret
= sdr_find_window_center(grp
, work_bgn
, work_end
);
1959 * search_stop_check() - Check if the detected edge is valid
1960 * @write: Perform read (Stage 2) or write (Stage 3) calibration
1962 * @rank_bgn: Rank number
1963 * @write_group: Write Group
1964 * @read_group: Read Group
1965 * @bit_chk: Resulting bit mask after the test
1966 * @sticky_bit_chk: Resulting sticky bit mask after the test
1967 * @use_read_test: Perform read test
1969 * Test if the found edge is valid.
1971 static u32
search_stop_check(const int write
, const int d
, const int rank_bgn
,
1972 const u32 write_group
, const u32 read_group
,
1973 u32
*bit_chk
, u32
*sticky_bit_chk
,
1974 const u32 use_read_test
)
1976 const u32 ratio
= rwcfg
->mem_if_read_dqs_width
/
1977 rwcfg
->mem_if_write_dqs_width
;
1978 const u32 correct_mask
= write
? param
->write_correct_mask
:
1979 param
->read_correct_mask
;
1980 const u32 per_dqs
= write
? rwcfg
->mem_dq_per_write_dqs
:
1981 rwcfg
->mem_dq_per_read_dqs
;
1984 * Stop searching when the read test doesn't pass AND when
1985 * we've seen a passing read on every bit.
1987 if (write
) { /* WRITE-ONLY */
1988 ret
= !rw_mgr_mem_calibrate_write_test(rank_bgn
, write_group
,
1991 } else if (use_read_test
) { /* READ-ONLY */
1992 ret
= !rw_mgr_mem_calibrate_read_test(rank_bgn
, read_group
,
1994 PASS_ONE_BIT
, bit_chk
,
1996 } else { /* READ-ONLY */
1997 rw_mgr_mem_calibrate_write_test(rank_bgn
, write_group
, 0,
1998 PASS_ONE_BIT
, bit_chk
, 0);
1999 *bit_chk
= *bit_chk
>> (per_dqs
*
2000 (read_group
- (write_group
* ratio
)));
2001 ret
= (*bit_chk
== 0);
2003 *sticky_bit_chk
= *sticky_bit_chk
| *bit_chk
;
2004 ret
= ret
&& (*sticky_bit_chk
== correct_mask
);
2005 debug_cond(DLEVEL
== 2,
2006 "%s:%d center(left): dtap=%u => %u == %u && %u",
2007 __func__
, __LINE__
, d
,
2008 *sticky_bit_chk
, correct_mask
, ret
);
2013 * search_left_edge() - Find left edge of DQ/DQS working phase
2014 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2015 * @rank_bgn: Rank number
2016 * @write_group: Write Group
2017 * @read_group: Read Group
2018 * @test_bgn: Rank number to begin the test
2019 * @sticky_bit_chk: Resulting sticky bit mask after the test
2020 * @left_edge: Left edge of the DQ/DQS phase
2021 * @right_edge: Right edge of the DQ/DQS phase
2022 * @use_read_test: Perform read test
2024 * Find left edge of DQ/DQS working phase.
2026 static void search_left_edge(const int write
, const int rank_bgn
,
2027 const u32 write_group
, const u32 read_group
, const u32 test_bgn
,
2028 u32
*sticky_bit_chk
,
2029 int *left_edge
, int *right_edge
, const u32 use_read_test
)
2031 const u32 delay_max
= write
? iocfg
->io_out1_delay_max
: iocfg
->io_in_delay_max
;
2032 const u32 dqs_max
= write
? iocfg
->io_out1_delay_max
: iocfg
->dqs_in_delay_max
;
2033 const u32 per_dqs
= write
? rwcfg
->mem_dq_per_write_dqs
:
2034 rwcfg
->mem_dq_per_read_dqs
;
2038 for (d
= 0; d
<= dqs_max
; d
++) {
2040 scc_mgr_apply_group_dq_out1_delay(d
);
2042 scc_mgr_apply_group_dq_in_delay(test_bgn
, d
);
2044 writel(0, &sdr_scc_mgr
->update
);
2046 stop
= search_stop_check(write
, d
, rank_bgn
, write_group
,
2047 read_group
, &bit_chk
, sticky_bit_chk
,
2053 for (i
= 0; i
< per_dqs
; i
++) {
2056 * Remember a passing test as
2062 * If a left edge has not been seen
2063 * yet, then a future passing test
2064 * will mark this edge as the right
2067 if (left_edge
[i
] == delay_max
+ 1)
2068 right_edge
[i
] = -(d
+ 1);
2074 /* Reset DQ delay chains to 0 */
2076 scc_mgr_apply_group_dq_out1_delay(0);
2078 scc_mgr_apply_group_dq_in_delay(test_bgn
, 0);
2080 *sticky_bit_chk
= 0;
2081 for (i
= per_dqs
- 1; i
>= 0; i
--) {
2082 debug_cond(DLEVEL
== 2,
2083 "%s:%d vfifo_center: left_edge[%u]: %d right_edge[%u]: %d\n",
2084 __func__
, __LINE__
, i
, left_edge
[i
],
2088 * Check for cases where we haven't found the left edge,
2089 * which makes our assignment of the the right edge invalid.
2090 * Reset it to the illegal value.
2092 if ((left_edge
[i
] == delay_max
+ 1) &&
2093 (right_edge
[i
] != delay_max
+ 1)) {
2094 right_edge
[i
] = delay_max
+ 1;
2095 debug_cond(DLEVEL
== 2,
2096 "%s:%d vfifo_center: reset right_edge[%u]: %d\n",
2097 __func__
, __LINE__
, i
, right_edge
[i
]);
2102 * READ: except for bits where we have seen both
2103 * the left and right edge.
2104 * WRITE: except for bits where we have seen the
2107 *sticky_bit_chk
<<= 1;
2109 if (left_edge
[i
] != delay_max
+ 1)
2110 *sticky_bit_chk
|= 1;
2112 if ((left_edge
[i
] != delay_max
+ 1) &&
2113 (right_edge
[i
] != delay_max
+ 1))
2114 *sticky_bit_chk
|= 1;
2122 * search_right_edge() - Find right edge of DQ/DQS working phase
2123 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2124 * @rank_bgn: Rank number
2125 * @write_group: Write Group
2126 * @read_group: Read Group
2127 * @start_dqs: DQS start phase
2128 * @start_dqs_en: DQS enable start phase
2129 * @sticky_bit_chk: Resulting sticky bit mask after the test
2130 * @left_edge: Left edge of the DQ/DQS phase
2131 * @right_edge: Right edge of the DQ/DQS phase
2132 * @use_read_test: Perform read test
2134 * Find right edge of DQ/DQS working phase.
2136 static int search_right_edge(const int write
, const int rank_bgn
,
2137 const u32 write_group
, const u32 read_group
,
2138 const int start_dqs
, const int start_dqs_en
,
2139 u32
*sticky_bit_chk
,
2140 int *left_edge
, int *right_edge
, const u32 use_read_test
)
2142 const u32 delay_max
= write
? iocfg
->io_out1_delay_max
: iocfg
->io_in_delay_max
;
2143 const u32 dqs_max
= write
? iocfg
->io_out1_delay_max
: iocfg
->dqs_in_delay_max
;
2144 const u32 per_dqs
= write
? rwcfg
->mem_dq_per_write_dqs
:
2145 rwcfg
->mem_dq_per_read_dqs
;
2149 for (d
= 0; d
<= dqs_max
- start_dqs
; d
++) {
2150 if (write
) { /* WRITE-ONLY */
2151 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group
,
2153 } else { /* READ-ONLY */
2154 scc_mgr_set_dqs_bus_in_delay(read_group
, d
+ start_dqs
);
2155 if (iocfg
->shift_dqs_en_when_shift_dqs
) {
2156 uint32_t delay
= d
+ start_dqs_en
;
2157 if (delay
> iocfg
->dqs_en_delay_max
)
2158 delay
= iocfg
->dqs_en_delay_max
;
2159 scc_mgr_set_dqs_en_delay(read_group
, delay
);
2161 scc_mgr_load_dqs(read_group
);
2164 writel(0, &sdr_scc_mgr
->update
);
2166 stop
= search_stop_check(write
, d
, rank_bgn
, write_group
,
2167 read_group
, &bit_chk
, sticky_bit_chk
,
2170 if (write
&& (d
== 0)) { /* WRITE-ONLY */
2171 for (i
= 0; i
< rwcfg
->mem_dq_per_write_dqs
; i
++) {
2173 * d = 0 failed, but it passed when
2174 * testing the left edge, so it must be
2175 * marginal, set it to -1
2177 if (right_edge
[i
] == delay_max
+ 1 &&
2178 left_edge
[i
] != delay_max
+ 1)
2186 for (i
= 0; i
< per_dqs
; i
++) {
2189 * Remember a passing test as
2196 * If a right edge has not
2197 * been seen yet, then a future
2198 * passing test will mark this
2199 * edge as the left edge.
2201 if (right_edge
[i
] == delay_max
+ 1)
2202 left_edge
[i
] = -(d
+ 1);
2205 * d = 0 failed, but it passed
2206 * when testing the left edge,
2207 * so it must be marginal, set
2210 if (right_edge
[i
] == delay_max
+ 1 &&
2211 left_edge
[i
] != delay_max
+ 1)
2214 * If a right edge has not been
2215 * seen yet, then a future
2216 * passing test will mark this
2217 * edge as the left edge.
2219 else if (right_edge
[i
] == delay_max
+ 1)
2220 left_edge
[i
] = -(d
+ 1);
2224 debug_cond(DLEVEL
== 2, "%s:%d center[r,d=%u]: ",
2225 __func__
, __LINE__
, d
);
2226 debug_cond(DLEVEL
== 2,
2227 "bit_chk_test=%i left_edge[%u]: %d ",
2228 bit_chk
& 1, i
, left_edge
[i
]);
2229 debug_cond(DLEVEL
== 2, "right_edge[%u]: %d\n", i
,
2235 /* Check that all bits have a window */
2236 for (i
= 0; i
< per_dqs
; i
++) {
2237 debug_cond(DLEVEL
== 2,
2238 "%s:%d write_center: left_edge[%u]: %d right_edge[%u]: %d",
2239 __func__
, __LINE__
, i
, left_edge
[i
],
2241 if ((left_edge
[i
] == dqs_max
+ 1) ||
2242 (right_edge
[i
] == dqs_max
+ 1))
2243 return i
+ 1; /* FIXME: If we fail, retval > 0 */
2250 * get_window_mid_index() - Find the best middle setting of DQ/DQS phase
2251 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2252 * @left_edge: Left edge of the DQ/DQS phase
2253 * @right_edge: Right edge of the DQ/DQS phase
2254 * @mid_min: Best DQ/DQS phase middle setting
2256 * Find index and value of the middle of the DQ/DQS working phase.
2258 static int get_window_mid_index(const int write
, int *left_edge
,
2259 int *right_edge
, int *mid_min
)
2261 const u32 per_dqs
= write
? rwcfg
->mem_dq_per_write_dqs
:
2262 rwcfg
->mem_dq_per_read_dqs
;
2263 int i
, mid
, min_index
;
2265 /* Find middle of window for each DQ bit */
2266 *mid_min
= left_edge
[0] - right_edge
[0];
2268 for (i
= 1; i
< per_dqs
; i
++) {
2269 mid
= left_edge
[i
] - right_edge
[i
];
2270 if (mid
< *mid_min
) {
2277 * -mid_min/2 represents the amount that we need to move DQS.
2278 * If mid_min is odd and positive we'll need to add one to make
2279 * sure the rounding in further calculations is correct (always
2280 * bias to the right), so just add 1 for all positive values.
2284 *mid_min
= *mid_min
/ 2;
2286 debug_cond(DLEVEL
== 1, "%s:%d vfifo_center: *mid_min=%d (index=%u)\n",
2287 __func__
, __LINE__
, *mid_min
, min_index
);
2292 * center_dq_windows() - Center the DQ/DQS windows
2293 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2294 * @left_edge: Left edge of the DQ/DQS phase
2295 * @right_edge: Right edge of the DQ/DQS phase
2296 * @mid_min: Adjusted DQ/DQS phase middle setting
2297 * @orig_mid_min: Original DQ/DQS phase middle setting
2298 * @min_index: DQ/DQS phase middle setting index
2299 * @test_bgn: Rank number to begin the test
2300 * @dq_margin: Amount of shift for the DQ
2301 * @dqs_margin: Amount of shift for the DQS
2303 * Align the DQ/DQS windows in each group.
2305 static void center_dq_windows(const int write
, int *left_edge
, int *right_edge
,
2306 const int mid_min
, const int orig_mid_min
,
2307 const int min_index
, const int test_bgn
,
2308 int *dq_margin
, int *dqs_margin
)
2310 const u32 delay_max
= write
? iocfg
->io_out1_delay_max
: iocfg
->io_in_delay_max
;
2311 const u32 per_dqs
= write
? rwcfg
->mem_dq_per_write_dqs
:
2312 rwcfg
->mem_dq_per_read_dqs
;
2313 const u32 delay_off
= write
? SCC_MGR_IO_OUT1_DELAY_OFFSET
:
2314 SCC_MGR_IO_IN_DELAY_OFFSET
;
2315 const u32 addr
= SDR_PHYGRP_SCCGRP_ADDRESS
| delay_off
;
2317 u32 temp_dq_io_delay1
, temp_dq_io_delay2
;
2320 /* Initialize data for export structures */
2321 *dqs_margin
= delay_max
+ 1;
2322 *dq_margin
= delay_max
+ 1;
2324 /* add delay to bring centre of all DQ windows to the same "level" */
2325 for (i
= 0, p
= test_bgn
; i
< per_dqs
; i
++, p
++) {
2326 /* Use values before divide by 2 to reduce round off error */
2327 shift_dq
= (left_edge
[i
] - right_edge
[i
] -
2328 (left_edge
[min_index
] - right_edge
[min_index
]))/2 +
2329 (orig_mid_min
- mid_min
);
2331 debug_cond(DLEVEL
== 2,
2332 "vfifo_center: before: shift_dq[%u]=%d\n",
2335 temp_dq_io_delay1
= readl(addr
+ (p
<< 2));
2336 temp_dq_io_delay2
= readl(addr
+ (i
<< 2));
2338 if (shift_dq
+ temp_dq_io_delay1
> delay_max
)
2339 shift_dq
= delay_max
- temp_dq_io_delay2
;
2340 else if (shift_dq
+ temp_dq_io_delay1
< 0)
2341 shift_dq
= -temp_dq_io_delay1
;
2343 debug_cond(DLEVEL
== 2,
2344 "vfifo_center: after: shift_dq[%u]=%d\n",
2348 scc_mgr_set_dq_out1_delay(i
, temp_dq_io_delay1
+ shift_dq
);
2350 scc_mgr_set_dq_in_delay(p
, temp_dq_io_delay1
+ shift_dq
);
2354 debug_cond(DLEVEL
== 2,
2355 "vfifo_center: margin[%u]=[%d,%d]\n", i
,
2356 left_edge
[i
] - shift_dq
+ (-mid_min
),
2357 right_edge
[i
] + shift_dq
- (-mid_min
));
2359 /* To determine values for export structures */
2360 if (left_edge
[i
] - shift_dq
+ (-mid_min
) < *dq_margin
)
2361 *dq_margin
= left_edge
[i
] - shift_dq
+ (-mid_min
);
2363 if (right_edge
[i
] + shift_dq
- (-mid_min
) < *dqs_margin
)
2364 *dqs_margin
= right_edge
[i
] + shift_dq
- (-mid_min
);
2370 * rw_mgr_mem_calibrate_vfifo_center() - Per-bit deskew DQ and centering
2371 * @rank_bgn: Rank number
2372 * @rw_group: Read/Write Group
2373 * @test_bgn: Rank at which the test begins
2374 * @use_read_test: Perform a read test
2375 * @update_fom: Update FOM
2377 * Per-bit deskew DQ and centering.
2379 static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn
,
2380 const u32 rw_group
, const u32 test_bgn
,
2381 const int use_read_test
, const int update_fom
)
2384 SDR_PHYGRP_SCCGRP_ADDRESS
+ SCC_MGR_DQS_IN_DELAY_OFFSET
+
2387 * Store these as signed since there are comparisons with
2390 uint32_t sticky_bit_chk
;
2391 int32_t left_edge
[rwcfg
->mem_dq_per_read_dqs
];
2392 int32_t right_edge
[rwcfg
->mem_dq_per_read_dqs
];
2393 int32_t orig_mid_min
, mid_min
;
2394 int32_t new_dqs
, start_dqs
, start_dqs_en
= 0, final_dqs_en
;
2395 int32_t dq_margin
, dqs_margin
;
2399 debug("%s:%d: %u %u", __func__
, __LINE__
, rw_group
, test_bgn
);
2401 start_dqs
= readl(addr
);
2402 if (iocfg
->shift_dqs_en_when_shift_dqs
)
2403 start_dqs_en
= readl(addr
- iocfg
->dqs_en_delay_offset
);
2405 /* set the left and right edge of each bit to an illegal value */
2406 /* use (iocfg->io_in_delay_max + 1) as an illegal value */
2408 for (i
= 0; i
< rwcfg
->mem_dq_per_read_dqs
; i
++) {
2409 left_edge
[i
] = iocfg
->io_in_delay_max
+ 1;
2410 right_edge
[i
] = iocfg
->io_in_delay_max
+ 1;
2413 /* Search for the left edge of the window for each bit */
2414 search_left_edge(0, rank_bgn
, rw_group
, rw_group
, test_bgn
,
2416 left_edge
, right_edge
, use_read_test
);
2419 /* Search for the right edge of the window for each bit */
2420 ret
= search_right_edge(0, rank_bgn
, rw_group
, rw_group
,
2421 start_dqs
, start_dqs_en
,
2423 left_edge
, right_edge
, use_read_test
);
2426 * Restore delay chain settings before letting the loop
2427 * in rw_mgr_mem_calibrate_vfifo to retry different
2428 * dqs/ck relationships.
2430 scc_mgr_set_dqs_bus_in_delay(rw_group
, start_dqs
);
2431 if (iocfg
->shift_dqs_en_when_shift_dqs
)
2432 scc_mgr_set_dqs_en_delay(rw_group
, start_dqs_en
);
2434 scc_mgr_load_dqs(rw_group
);
2435 writel(0, &sdr_scc_mgr
->update
);
2437 debug_cond(DLEVEL
== 1,
2438 "%s:%d vfifo_center: failed to find edge [%u]: %d %d",
2439 __func__
, __LINE__
, i
, left_edge
[i
], right_edge
[i
]);
2440 if (use_read_test
) {
2441 set_failing_group_stage(rw_group
*
2442 rwcfg
->mem_dq_per_read_dqs
+ i
,
2444 CAL_SUBSTAGE_VFIFO_CENTER
);
2446 set_failing_group_stage(rw_group
*
2447 rwcfg
->mem_dq_per_read_dqs
+ i
,
2448 CAL_STAGE_VFIFO_AFTER_WRITES
,
2449 CAL_SUBSTAGE_VFIFO_CENTER
);
2454 min_index
= get_window_mid_index(0, left_edge
, right_edge
, &mid_min
);
2456 /* Determine the amount we can change DQS (which is -mid_min) */
2457 orig_mid_min
= mid_min
;
2458 new_dqs
= start_dqs
- mid_min
;
2459 if (new_dqs
> iocfg
->dqs_in_delay_max
)
2460 new_dqs
= iocfg
->dqs_in_delay_max
;
2461 else if (new_dqs
< 0)
2464 mid_min
= start_dqs
- new_dqs
;
2465 debug_cond(DLEVEL
== 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2468 if (iocfg
->shift_dqs_en_when_shift_dqs
) {
2469 if (start_dqs_en
- mid_min
> iocfg
->dqs_en_delay_max
)
2470 mid_min
+= start_dqs_en
- mid_min
- iocfg
->dqs_en_delay_max
;
2471 else if (start_dqs_en
- mid_min
< 0)
2472 mid_min
+= start_dqs_en
- mid_min
;
2474 new_dqs
= start_dqs
- mid_min
;
2476 debug_cond(DLEVEL
== 1,
2477 "vfifo_center: start_dqs=%d start_dqs_en=%d new_dqs=%d mid_min=%d\n",
2479 iocfg
->shift_dqs_en_when_shift_dqs
? start_dqs_en
: -1,
2482 /* Add delay to bring centre of all DQ windows to the same "level". */
2483 center_dq_windows(0, left_edge
, right_edge
, mid_min
, orig_mid_min
,
2484 min_index
, test_bgn
, &dq_margin
, &dqs_margin
);
2487 if (iocfg
->shift_dqs_en_when_shift_dqs
) {
2488 final_dqs_en
= start_dqs_en
- mid_min
;
2489 scc_mgr_set_dqs_en_delay(rw_group
, final_dqs_en
);
2490 scc_mgr_load_dqs(rw_group
);
2494 scc_mgr_set_dqs_bus_in_delay(rw_group
, new_dqs
);
2495 scc_mgr_load_dqs(rw_group
);
2496 debug_cond(DLEVEL
== 2,
2497 "%s:%d vfifo_center: dq_margin=%d dqs_margin=%d",
2498 __func__
, __LINE__
, dq_margin
, dqs_margin
);
2501 * Do not remove this line as it makes sure all of our decisions
2502 * have been applied. Apply the update bit.
2504 writel(0, &sdr_scc_mgr
->update
);
2506 if ((dq_margin
< 0) || (dqs_margin
< 0))
2513 * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
2514 * @rw_group: Read/Write Group
2515 * @phase: DQ/DQS phase
2517 * Because initially no communication ca be reliably performed with the memory
2518 * device, the sequencer uses a guaranteed write mechanism to write data into
2519 * the memory device.
2521 static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group
,
2526 /* Set a particular DQ/DQS phase. */
2527 scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group
, phase
);
2529 debug_cond(DLEVEL
== 1, "%s:%d guaranteed write: g=%u p=%u\n",
2530 __func__
, __LINE__
, rw_group
, phase
);
2533 * Altera EMI_RM 2015.05.04 :: Figure 1-25
2534 * Load up the patterns used by read calibration using the
2535 * current DQDQS phase.
2537 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2539 if (gbl
->phy_debug_mode_flags
& PHY_DEBUG_DISABLE_GUARANTEED_READ
)
2543 * Altera EMI_RM 2015.05.04 :: Figure 1-26
2544 * Back-to-Back reads of the patterns used for calibration.
2546 ret
= rw_mgr_mem_calibrate_read_test_patterns(0, rw_group
, 1);
2548 debug_cond(DLEVEL
== 1,
2549 "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2550 __func__
, __LINE__
, rw_group
, phase
);
2555 * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2556 * @rw_group: Read/Write Group
2557 * @test_bgn: Rank at which the test begins
2559 * DQS enable calibration ensures reliable capture of the DQ signal without
2560 * glitches on the DQS line.
2562 static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group
,
2566 * Altera EMI_RM 2015.05.04 :: Figure 1-27
2567 * DQS and DQS Eanble Signal Relationships.
2570 /* We start at zero, so have one less dq to devide among */
2571 const u32 delay_step
= iocfg
->io_in_delay_max
/
2572 (rwcfg
->mem_dq_per_read_dqs
- 1);
2576 debug("%s:%d (%u,%u)\n", __func__
, __LINE__
, rw_group
, test_bgn
);
2578 /* Try different dq_in_delays since the DQ path is shorter than DQS. */
2579 for (r
= 0; r
< rwcfg
->mem_number_of_ranks
;
2580 r
+= NUM_RANKS_PER_SHADOW_REG
) {
2581 for (i
= 0, p
= test_bgn
, d
= 0;
2582 i
< rwcfg
->mem_dq_per_read_dqs
;
2583 i
++, p
++, d
+= delay_step
) {
2584 debug_cond(DLEVEL
== 1,
2585 "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
2586 __func__
, __LINE__
, rw_group
, r
, i
, p
, d
);
2588 scc_mgr_set_dq_in_delay(p
, d
);
2592 writel(0, &sdr_scc_mgr
->update
);
2596 * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
2597 * dq_in_delay values
2599 ret
= rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group
);
2601 debug_cond(DLEVEL
== 1,
2602 "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
2603 __func__
, __LINE__
, rw_group
, !ret
);
2605 for (r
= 0; r
< rwcfg
->mem_number_of_ranks
;
2606 r
+= NUM_RANKS_PER_SHADOW_REG
) {
2607 scc_mgr_apply_group_dq_in_delay(test_bgn
, 0);
2608 writel(0, &sdr_scc_mgr
->update
);
2615 * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
2616 * @rw_group: Read/Write Group
2617 * @test_bgn: Rank at which the test begins
2618 * @use_read_test: Perform a read test
2619 * @update_fom: Update FOM
2621 * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
2625 rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group
, const u32 test_bgn
,
2626 const int use_read_test
,
2627 const int update_fom
)
2630 int ret
, grp_calibrated
;
2634 * Altera EMI_RM 2015.05.04 :: Figure 1-28
2635 * Read per-bit deskew can be done on a per shadow register basis.
2638 for (rank_bgn
= 0, sr
= 0;
2639 rank_bgn
< rwcfg
->mem_number_of_ranks
;
2640 rank_bgn
+= NUM_RANKS_PER_SHADOW_REG
, sr
++) {
2641 ret
= rw_mgr_mem_calibrate_vfifo_center(rank_bgn
, rw_group
,
2651 if (!grp_calibrated
)
2658 * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2659 * @rw_group: Read/Write Group
2660 * @test_bgn: Rank at which the test begins
2662 * Stage 1: Calibrate the read valid prediction FIFO.
2664 * This function implements UniPHY calibration Stage 1, as explained in
2665 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2667 * - read valid prediction will consist of finding:
2668 * - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2669 * - DQS input phase and DQS input delay (DQ/DQS Centering)
2670 * - we also do a per-bit deskew on the DQ lines.
2672 static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group
, const u32 test_bgn
)
2675 uint32_t dtaps_per_ptap
;
2676 uint32_t failed_substage
;
2680 debug("%s:%d: %u %u\n", __func__
, __LINE__
, rw_group
, test_bgn
);
2682 /* Update info for sims */
2683 reg_file_set_group(rw_group
);
2684 reg_file_set_stage(CAL_STAGE_VFIFO
);
2685 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ
);
2687 failed_substage
= CAL_SUBSTAGE_GUARANTEED_READ
;
2689 /* USER Determine number of delay taps for each phase tap. */
2690 dtaps_per_ptap
= DIV_ROUND_UP(iocfg
->delay_per_opa_tap
,
2691 iocfg
->delay_per_dqs_en_dchain_tap
) - 1;
2693 for (d
= 0; d
<= dtaps_per_ptap
; d
+= 2) {
2695 * In RLDRAMX we may be messing the delay of pins in
2696 * the same write rw_group but outside of the current read
2697 * the rw_group, but that's ok because we haven't calibrated
2701 scc_mgr_apply_group_all_out_delay_add_all_ranks(
2705 for (p
= 0; p
<= iocfg
->dqdqs_out_phase_max
; p
++) {
2706 /* 1) Guaranteed Write */
2707 ret
= rw_mgr_mem_calibrate_guaranteed_write(rw_group
, p
);
2711 /* 2) DQS Enable Calibration */
2712 ret
= rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group
,
2715 failed_substage
= CAL_SUBSTAGE_DQS_EN_PHASE
;
2719 /* 3) Centering DQ/DQS */
2721 * If doing read after write calibration, do not update
2722 * FOM now. Do it then.
2724 ret
= rw_mgr_mem_calibrate_dq_dqs_centering(rw_group
,
2727 failed_substage
= CAL_SUBSTAGE_VFIFO_CENTER
;
2736 /* Calibration Stage 1 failed. */
2737 set_failing_group_stage(rw_group
, CAL_STAGE_VFIFO
, failed_substage
);
2740 /* Calibration Stage 1 completed OK. */
2743 * Reset the delay chains back to zero if they have moved > 1
2744 * (check for > 1 because loop will increase d even when pass in
2748 scc_mgr_zero_group(rw_group
, 1);
2754 * rw_mgr_mem_calibrate_vfifo_end() - DQ/DQS Centering.
2755 * @rw_group: Read/Write Group
2756 * @test_bgn: Rank at which the test begins
2758 * Stage 3: DQ/DQS Centering.
2760 * This function implements UniPHY calibration Stage 3, as explained in
2761 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2763 static int rw_mgr_mem_calibrate_vfifo_end(const u32 rw_group
,
2768 debug("%s:%d %u %u", __func__
, __LINE__
, rw_group
, test_bgn
);
2770 /* Update info for sims. */
2771 reg_file_set_group(rw_group
);
2772 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES
);
2773 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER
);
2775 ret
= rw_mgr_mem_calibrate_dq_dqs_centering(rw_group
, test_bgn
, 0, 1);
2777 set_failing_group_stage(rw_group
,
2778 CAL_STAGE_VFIFO_AFTER_WRITES
,
2779 CAL_SUBSTAGE_VFIFO_CENTER
);
2784 * rw_mgr_mem_calibrate_lfifo() - Minimize latency
2786 * Stage 4: Minimize latency.
2788 * This function implements UniPHY calibration Stage 4, as explained in
2789 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2790 * Calibrate LFIFO to find smallest read latency.
2792 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2796 debug("%s:%d\n", __func__
, __LINE__
);
2798 /* Update info for sims. */
2799 reg_file_set_stage(CAL_STAGE_LFIFO
);
2800 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY
);
2802 /* Load up the patterns used by read calibration for all ranks */
2803 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2806 writel(gbl
->curr_read_lat
, &phy_mgr_cfg
->phy_rlat
);
2807 debug_cond(DLEVEL
== 2, "%s:%d lfifo: read_lat=%u",
2808 __func__
, __LINE__
, gbl
->curr_read_lat
);
2810 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0, NUM_READ_TESTS
,
2816 * Reduce read latency and see if things are
2817 * working correctly.
2819 gbl
->curr_read_lat
--;
2820 } while (gbl
->curr_read_lat
> 0);
2822 /* Reset the fifos to get pointers to known state. */
2823 writel(0, &phy_mgr_cmd
->fifo_reset
);
2826 /* Add a fudge factor to the read latency that was determined */
2827 gbl
->curr_read_lat
+= 2;
2828 writel(gbl
->curr_read_lat
, &phy_mgr_cfg
->phy_rlat
);
2829 debug_cond(DLEVEL
== 2,
2830 "%s:%d lfifo: success: using read_lat=%u\n",
2831 __func__
, __LINE__
, gbl
->curr_read_lat
);
2833 set_failing_group_stage(0xff, CAL_STAGE_LFIFO
,
2834 CAL_SUBSTAGE_READ_LATENCY
);
2836 debug_cond(DLEVEL
== 2,
2837 "%s:%d lfifo: failed at initial read_lat=%u\n",
2838 __func__
, __LINE__
, gbl
->curr_read_lat
);
2845 * search_window() - Search for the/part of the window with DM/DQS shift
2846 * @search_dm: If 1, search for the DM shift, if 0, search for DQS shift
2847 * @rank_bgn: Rank number
2848 * @write_group: Write Group
2849 * @bgn_curr: Current window begin
2850 * @end_curr: Current window end
2851 * @bgn_best: Current best window begin
2852 * @end_best: Current best window end
2853 * @win_best: Size of the best window
2854 * @new_dqs: New DQS value (only applicable if search_dm = 0).
2856 * Search for the/part of the window with DM/DQS shift.
2858 static void search_window(const int search_dm
,
2859 const u32 rank_bgn
, const u32 write_group
,
2860 int *bgn_curr
, int *end_curr
, int *bgn_best
,
2861 int *end_best
, int *win_best
, int new_dqs
)
2864 const int max
= iocfg
->io_out1_delay_max
- new_dqs
;
2867 /* Search for the/part of the window with DM/DQS shift. */
2868 for (di
= max
; di
>= 0; di
-= DELTA_D
) {
2871 scc_mgr_apply_group_dm_out1_delay(d
);
2873 /* For DQS, we go from 0...max */
2876 * Note: This only shifts DQS, so are we limiting ourselve to
2877 * width of DQ unnecessarily.
2879 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group
,
2883 writel(0, &sdr_scc_mgr
->update
);
2885 if (rw_mgr_mem_calibrate_write_test(rank_bgn
, write_group
, 1,
2886 PASS_ALL_BITS
, &bit_chk
,
2888 /* Set current end of the window. */
2889 *end_curr
= search_dm
? -d
: d
;
2892 * If a starting edge of our window has not been seen
2893 * this is our current start of the DM window.
2895 if (*bgn_curr
== iocfg
->io_out1_delay_max
+ 1)
2896 *bgn_curr
= search_dm
? -d
: d
;
2899 * If current window is bigger than best seen.
2900 * Set best seen to be current window.
2902 if ((*end_curr
- *bgn_curr
+ 1) > *win_best
) {
2903 *win_best
= *end_curr
- *bgn_curr
+ 1;
2904 *bgn_best
= *bgn_curr
;
2905 *end_best
= *end_curr
;
2908 /* We just saw a failing test. Reset temp edge. */
2909 *bgn_curr
= iocfg
->io_out1_delay_max
+ 1;
2910 *end_curr
= iocfg
->io_out1_delay_max
+ 1;
2912 /* Early exit is only applicable to DQS. */
2917 * Early exit optimization: if the remaining delay
2918 * chain space is less than already seen largest
2919 * window we can exit.
2921 if (*win_best
- 1 > iocfg
->io_out1_delay_max
- new_dqs
- d
)
2928 * rw_mgr_mem_calibrate_writes_center() - Center all windows
2929 * @rank_bgn: Rank number
2930 * @write_group: Write group
2931 * @test_bgn: Rank at which the test begins
2933 * Center all windows. Do per-bit-deskew to possibly increase size of
2937 rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn
, const u32 write_group
,
2943 int left_edge
[rwcfg
->mem_dq_per_write_dqs
];
2944 int right_edge
[rwcfg
->mem_dq_per_write_dqs
];
2946 int mid_min
, orig_mid_min
;
2947 int new_dqs
, start_dqs
;
2948 int dq_margin
, dqs_margin
, dm_margin
;
2949 int bgn_curr
= iocfg
->io_out1_delay_max
+ 1;
2950 int end_curr
= iocfg
->io_out1_delay_max
+ 1;
2951 int bgn_best
= iocfg
->io_out1_delay_max
+ 1;
2952 int end_best
= iocfg
->io_out1_delay_max
+ 1;
2957 debug("%s:%d %u %u", __func__
, __LINE__
, write_group
, test_bgn
);
2961 start_dqs
= readl((SDR_PHYGRP_SCCGRP_ADDRESS
|
2962 SCC_MGR_IO_OUT1_DELAY_OFFSET
) +
2963 (rwcfg
->mem_dq_per_write_dqs
<< 2));
2965 /* Per-bit deskew. */
2968 * Set the left and right edge of each bit to an illegal value.
2969 * Use (iocfg->io_out1_delay_max + 1) as an illegal value.
2972 for (i
= 0; i
< rwcfg
->mem_dq_per_write_dqs
; i
++) {
2973 left_edge
[i
] = iocfg
->io_out1_delay_max
+ 1;
2974 right_edge
[i
] = iocfg
->io_out1_delay_max
+ 1;
2977 /* Search for the left edge of the window for each bit. */
2978 search_left_edge(1, rank_bgn
, write_group
, 0, test_bgn
,
2980 left_edge
, right_edge
, 0);
2982 /* Search for the right edge of the window for each bit. */
2983 ret
= search_right_edge(1, rank_bgn
, write_group
, 0,
2986 left_edge
, right_edge
, 0);
2988 set_failing_group_stage(test_bgn
+ ret
- 1, CAL_STAGE_WRITES
,
2989 CAL_SUBSTAGE_WRITES_CENTER
);
2993 min_index
= get_window_mid_index(1, left_edge
, right_edge
, &mid_min
);
2995 /* Determine the amount we can change DQS (which is -mid_min). */
2996 orig_mid_min
= mid_min
;
2997 new_dqs
= start_dqs
;
2999 debug_cond(DLEVEL
== 1,
3000 "%s:%d write_center: start_dqs=%d new_dqs=%d mid_min=%d\n",
3001 __func__
, __LINE__
, start_dqs
, new_dqs
, mid_min
);
3003 /* Add delay to bring centre of all DQ windows to the same "level". */
3004 center_dq_windows(1, left_edge
, right_edge
, mid_min
, orig_mid_min
,
3005 min_index
, 0, &dq_margin
, &dqs_margin
);
3008 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group
, new_dqs
);
3009 writel(0, &sdr_scc_mgr
->update
);
3012 debug_cond(DLEVEL
== 2, "%s:%d write_center: DM\n", __func__
, __LINE__
);
3015 * Set the left and right edge of each bit to an illegal value.
3016 * Use (iocfg->io_out1_delay_max + 1) as an illegal value.
3018 left_edge
[0] = iocfg
->io_out1_delay_max
+ 1;
3019 right_edge
[0] = iocfg
->io_out1_delay_max
+ 1;
3021 /* Search for the/part of the window with DM shift. */
3022 search_window(1, rank_bgn
, write_group
, &bgn_curr
, &end_curr
,
3023 &bgn_best
, &end_best
, &win_best
, 0);
3025 /* Reset DM delay chains to 0. */
3026 scc_mgr_apply_group_dm_out1_delay(0);
3029 * Check to see if the current window nudges up aganist 0 delay.
3030 * If so we need to continue the search by shifting DQS otherwise DQS
3031 * search begins as a new search.
3033 if (end_curr
!= 0) {
3034 bgn_curr
= iocfg
->io_out1_delay_max
+ 1;
3035 end_curr
= iocfg
->io_out1_delay_max
+ 1;
3038 /* Search for the/part of the window with DQS shifts. */
3039 search_window(0, rank_bgn
, write_group
, &bgn_curr
, &end_curr
,
3040 &bgn_best
, &end_best
, &win_best
, new_dqs
);
3042 /* Assign left and right edge for cal and reporting. */
3043 left_edge
[0] = -1 * bgn_best
;
3044 right_edge
[0] = end_best
;
3046 debug_cond(DLEVEL
== 2, "%s:%d dm_calib: left=%d right=%d\n",
3047 __func__
, __LINE__
, left_edge
[0], right_edge
[0]);
3049 /* Move DQS (back to orig). */
3050 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group
, new_dqs
);
3054 /* Find middle of window for the DM bit. */
3055 mid
= (left_edge
[0] - right_edge
[0]) / 2;
3057 /* Only move right, since we are not moving DQS/DQ. */
3061 /* dm_marign should fail if we never find a window. */
3065 dm_margin
= left_edge
[0] - mid
;
3067 scc_mgr_apply_group_dm_out1_delay(mid
);
3068 writel(0, &sdr_scc_mgr
->update
);
3070 debug_cond(DLEVEL
== 2,
3071 "%s:%d dm_calib: left=%d right=%d mid=%d dm_margin=%d\n",
3072 __func__
, __LINE__
, left_edge
[0], right_edge
[0],
3074 /* Export values. */
3075 gbl
->fom_out
+= dq_margin
+ dqs_margin
;
3077 debug_cond(DLEVEL
== 2,
3078 "%s:%d write_center: dq_margin=%d dqs_margin=%d dm_margin=%d\n",
3079 __func__
, __LINE__
, dq_margin
, dqs_margin
, dm_margin
);
3082 * Do not remove this line as it makes sure all of our
3083 * decisions have been applied.
3085 writel(0, &sdr_scc_mgr
->update
);
3087 if ((dq_margin
< 0) || (dqs_margin
< 0) || (dm_margin
< 0))
3094 * rw_mgr_mem_calibrate_writes() - Write Calibration Part One
3095 * @rank_bgn: Rank number
3096 * @group: Read/Write Group
3097 * @test_bgn: Rank at which the test begins
3099 * Stage 2: Write Calibration Part One.
3101 * This function implements UniPHY calibration Stage 2, as explained in
3102 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
3104 static int rw_mgr_mem_calibrate_writes(const u32 rank_bgn
, const u32 group
,
3109 /* Update info for sims */
3110 debug("%s:%d %u %u\n", __func__
, __LINE__
, group
, test_bgn
);
3112 reg_file_set_group(group
);
3113 reg_file_set_stage(CAL_STAGE_WRITES
);
3114 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER
);
3116 ret
= rw_mgr_mem_calibrate_writes_center(rank_bgn
, group
, test_bgn
);
3118 set_failing_group_stage(group
, CAL_STAGE_WRITES
,
3119 CAL_SUBSTAGE_WRITES_CENTER
);
3125 * mem_precharge_and_activate() - Precharge all banks and activate
3127 * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3129 static void mem_precharge_and_activate(void)
3133 for (r
= 0; r
< rwcfg
->mem_number_of_ranks
; r
++) {
3135 set_rank_and_odt_mask(r
, RW_MGR_ODT_MODE_OFF
);
3137 /* Precharge all banks. */
3138 writel(rwcfg
->precharge_all
, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
3139 RW_MGR_RUN_SINGLE_GROUP_OFFSET
);
3141 writel(0x0F, &sdr_rw_load_mgr_regs
->load_cntr0
);
3142 writel(rwcfg
->activate_0_and_1_wait1
,
3143 &sdr_rw_load_jump_mgr_regs
->load_jump_add0
);
3145 writel(0x0F, &sdr_rw_load_mgr_regs
->load_cntr1
);
3146 writel(rwcfg
->activate_0_and_1_wait2
,
3147 &sdr_rw_load_jump_mgr_regs
->load_jump_add1
);
3149 /* Activate rows. */
3150 writel(rwcfg
->activate_0_and_1
, SDR_PHYGRP_RWMGRGRP_ADDRESS
|
3151 RW_MGR_RUN_SINGLE_GROUP_OFFSET
);
3156 * mem_init_latency() - Configure memory RLAT and WLAT settings
3158 * Configure memory RLAT and WLAT parameters.
3160 static void mem_init_latency(void)
3163 * For AV/CV, LFIFO is hardened and always runs at full rate
3164 * so max latency in AFI clocks, used here, is correspondingly
3167 const u32 max_latency
= (1 << MAX_LATENCY_COUNT_WIDTH
) - 1;
3170 debug("%s:%d\n", __func__
, __LINE__
);
3173 * Read in write latency.
3174 * WL for Hard PHY does not include additive latency.
3176 wlat
= readl(&data_mgr
->t_wl_add
);
3177 wlat
+= readl(&data_mgr
->mem_t_add
);
3179 gbl
->rw_wl_nop_cycles
= wlat
- 1;
3181 /* Read in readl latency. */
3182 rlat
= readl(&data_mgr
->t_rl_add
);
3184 /* Set a pretty high read latency initially. */
3185 gbl
->curr_read_lat
= rlat
+ 16;
3186 if (gbl
->curr_read_lat
> max_latency
)
3187 gbl
->curr_read_lat
= max_latency
;
3189 writel(gbl
->curr_read_lat
, &phy_mgr_cfg
->phy_rlat
);
3191 /* Advertise write latency. */
3192 writel(wlat
, &phy_mgr_cfg
->afi_wlat
);
3196 * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3198 * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3200 static void mem_skip_calibrate(void)
3202 uint32_t vfifo_offset
;
3205 debug("%s:%d\n", __func__
, __LINE__
);
3206 /* Need to update every shadow register set used by the interface */
3207 for (r
= 0; r
< rwcfg
->mem_number_of_ranks
;
3208 r
+= NUM_RANKS_PER_SHADOW_REG
) {
3210 * Set output phase alignment settings appropriate for
3213 for (i
= 0; i
< rwcfg
->mem_if_read_dqs_width
; i
++) {
3214 scc_mgr_set_dqs_en_phase(i
, 0);
3215 if (iocfg
->dll_chain_length
== 6)
3216 scc_mgr_set_dqdqs_output_phase(i
, 6);
3218 scc_mgr_set_dqdqs_output_phase(i
, 7);
3222 * Write data arrives to the I/O two cycles before write
3223 * latency is reached (720 deg).
3224 * -> due to bit-slip in a/c bus
3225 * -> to allow board skew where dqs is longer than ck
3226 * -> how often can this happen!?
3227 * -> can claim back some ptaps for high freq
3228 * support if we can relax this, but i digress...
3230 * The write_clk leads mem_ck by 90 deg
3231 * The minimum ptap of the OPA is 180 deg
3232 * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3233 * The write_clk is always delayed by 2 ptaps
3235 * Hence, to make DQS aligned to CK, we need to delay
3237 * (720 - 90 - 180 - 2 * (360 / iocfg->dll_chain_length))
3239 * Dividing the above by (360 / iocfg->dll_chain_length)
3240 * gives us the number of ptaps, which simplies to:
3242 * (1.25 * iocfg->dll_chain_length - 2)
3244 scc_mgr_set_dqdqs_output_phase(i
,
3245 1.25 * iocfg
->dll_chain_length
- 2);
3247 writel(0xff, &sdr_scc_mgr
->dqs_ena
);
3248 writel(0xff, &sdr_scc_mgr
->dqs_io_ena
);
3250 for (i
= 0; i
< rwcfg
->mem_if_write_dqs_width
; i
++) {
3251 writel(i
, SDR_PHYGRP_SCCGRP_ADDRESS
|
3252 SCC_MGR_GROUP_COUNTER_OFFSET
);
3254 writel(0xff, &sdr_scc_mgr
->dq_ena
);
3255 writel(0xff, &sdr_scc_mgr
->dm_ena
);
3256 writel(0, &sdr_scc_mgr
->update
);
3259 /* Compensate for simulation model behaviour */
3260 for (i
= 0; i
< rwcfg
->mem_if_read_dqs_width
; i
++) {
3261 scc_mgr_set_dqs_bus_in_delay(i
, 10);
3262 scc_mgr_load_dqs(i
);
3264 writel(0, &sdr_scc_mgr
->update
);
3267 * ArriaV has hard FIFOs that can only be initialized by incrementing
3270 vfifo_offset
= CALIB_VFIFO_OFFSET
;
3271 for (j
= 0; j
< vfifo_offset
; j
++)
3272 writel(0xff, &phy_mgr_cmd
->inc_vfifo_hard_phy
);
3273 writel(0, &phy_mgr_cmd
->fifo_reset
);
3276 * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3277 * setting from generation-time constant.
3279 gbl
->curr_read_lat
= CALIB_LFIFO_OFFSET
;
3280 writel(gbl
->curr_read_lat
, &phy_mgr_cfg
->phy_rlat
);
3284 * mem_calibrate() - Memory calibration entry point.
3286 * Perform memory calibration.
3288 static uint32_t mem_calibrate(void)
3291 uint32_t rank_bgn
, sr
;
3292 uint32_t write_group
, write_test_bgn
;
3293 uint32_t read_group
, read_test_bgn
;
3294 uint32_t run_groups
, current_run
;
3295 uint32_t failing_groups
= 0;
3296 uint32_t group_failed
= 0;
3298 const u32 rwdqs_ratio
= rwcfg
->mem_if_read_dqs_width
/
3299 rwcfg
->mem_if_write_dqs_width
;
3301 debug("%s:%d\n", __func__
, __LINE__
);
3303 /* Initialize the data settings */
3304 gbl
->error_substage
= CAL_SUBSTAGE_NIL
;
3305 gbl
->error_stage
= CAL_STAGE_NIL
;
3306 gbl
->error_group
= 0xff;
3310 /* Initialize WLAT and RLAT. */
3313 /* Initialize bit slips. */
3314 mem_precharge_and_activate();
3316 for (i
= 0; i
< rwcfg
->mem_if_read_dqs_width
; i
++) {
3317 writel(i
, SDR_PHYGRP_SCCGRP_ADDRESS
|
3318 SCC_MGR_GROUP_COUNTER_OFFSET
);
3319 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3321 scc_mgr_set_hhp_extras();
3323 scc_set_bypass_mode(i
);
3326 /* Calibration is skipped. */
3327 if ((dyn_calib_steps
& CALIB_SKIP_ALL
) == CALIB_SKIP_ALL
) {
3329 * Set VFIFO and LFIFO to instant-on settings in skip
3332 mem_skip_calibrate();
3335 * Do not remove this line as it makes sure all of our
3336 * decisions have been applied.
3338 writel(0, &sdr_scc_mgr
->update
);
3342 /* Calibration is not skipped. */
3343 for (i
= 0; i
< NUM_CALIB_REPEAT
; i
++) {
3345 * Zero all delay chain/phase settings for all
3346 * groups and all shadow register sets.
3352 for (write_group
= 0, write_test_bgn
= 0; write_group
3353 < rwcfg
->mem_if_write_dqs_width
; write_group
++,
3354 write_test_bgn
+= rwcfg
->mem_dq_per_write_dqs
) {
3356 /* Initialize the group failure */
3359 current_run
= run_groups
& ((1 <<
3360 RW_MGR_NUM_DQS_PER_WRITE_GROUP
) - 1);
3361 run_groups
= run_groups
>>
3362 RW_MGR_NUM_DQS_PER_WRITE_GROUP
;
3364 if (current_run
== 0)
3367 writel(write_group
, SDR_PHYGRP_SCCGRP_ADDRESS
|
3368 SCC_MGR_GROUP_COUNTER_OFFSET
);
3369 scc_mgr_zero_group(write_group
, 0);
3371 for (read_group
= write_group
* rwdqs_ratio
,
3373 read_group
< (write_group
+ 1) * rwdqs_ratio
;
3375 read_test_bgn
+= rwcfg
->mem_dq_per_read_dqs
) {
3376 if (STATIC_CALIB_STEPS
& CALIB_SKIP_VFIFO
)
3379 /* Calibrate the VFIFO */
3380 if (rw_mgr_mem_calibrate_vfifo(read_group
,
3384 if (!(gbl
->phy_debug_mode_flags
& PHY_DEBUG_SWEEP_ALL_GROUPS
))
3387 /* The group failed, we're done. */
3391 /* Calibrate the output side */
3392 for (rank_bgn
= 0, sr
= 0;
3393 rank_bgn
< rwcfg
->mem_number_of_ranks
;
3394 rank_bgn
+= NUM_RANKS_PER_SHADOW_REG
, sr
++) {
3395 if (STATIC_CALIB_STEPS
& CALIB_SKIP_WRITES
)
3398 /* Not needed in quick mode! */
3399 if (STATIC_CALIB_STEPS
& CALIB_SKIP_DELAY_SWEEPS
)
3402 /* Calibrate WRITEs */
3403 if (!rw_mgr_mem_calibrate_writes(rank_bgn
,
3404 write_group
, write_test_bgn
))
3408 if (!(gbl
->phy_debug_mode_flags
& PHY_DEBUG_SWEEP_ALL_GROUPS
))
3412 /* Some group failed, we're done. */
3416 for (read_group
= write_group
* rwdqs_ratio
,
3418 read_group
< (write_group
+ 1) * rwdqs_ratio
;
3420 read_test_bgn
+= rwcfg
->mem_dq_per_read_dqs
) {
3421 if (STATIC_CALIB_STEPS
& CALIB_SKIP_WRITES
)
3424 if (!rw_mgr_mem_calibrate_vfifo_end(read_group
,
3428 if (!(gbl
->phy_debug_mode_flags
& PHY_DEBUG_SWEEP_ALL_GROUPS
))
3431 /* The group failed, we're done. */
3435 /* No group failed, continue as usual. */
3438 grp_failed
: /* A group failed, increment the counter. */
3443 * USER If there are any failing groups then report
3446 if (failing_groups
!= 0)
3449 if (STATIC_CALIB_STEPS
& CALIB_SKIP_LFIFO
)
3452 /* Calibrate the LFIFO */
3453 if (!rw_mgr_mem_calibrate_lfifo())
3458 * Do not remove this line as it makes sure all of our decisions
3459 * have been applied.
3461 writel(0, &sdr_scc_mgr
->update
);
3466 * run_mem_calibrate() - Perform memory calibration
3468 * This function triggers the entire memory calibration procedure.
3470 static int run_mem_calibrate(void)
3474 debug("%s:%d\n", __func__
, __LINE__
);
3476 /* Reset pass/fail status shown on afi_cal_success/fail */
3477 writel(PHY_MGR_CAL_RESET
, &phy_mgr_cfg
->cal_status
);
3479 /* Stop tracking manager. */
3480 clrbits_le32(&sdr_ctrl
->ctrl_cfg
, 1 << 22);
3482 phy_mgr_initialize();
3483 rw_mgr_mem_initialize();
3485 /* Perform the actual memory calibration. */
3486 pass
= mem_calibrate();
3488 mem_precharge_and_activate();
3489 writel(0, &phy_mgr_cmd
->fifo_reset
);
3492 rw_mgr_mem_handoff();
3494 * In Hard PHY this is a 2-bit control:
3496 * 1: DDIO Mux Select
3498 writel(0x2, &phy_mgr_cfg
->mux_sel
);
3500 /* Start tracking manager. */
3501 setbits_le32(&sdr_ctrl
->ctrl_cfg
, 1 << 22);
3507 * debug_mem_calibrate() - Report result of memory calibration
3508 * @pass: Value indicating whether calibration passed or failed
3510 * This function reports the results of the memory calibration
3511 * and writes debug information into the register file.
3513 static void debug_mem_calibrate(int pass
)
3515 uint32_t debug_info
;
3518 printf("%s: CALIBRATION PASSED\n", __FILE__
);
3523 if (gbl
->fom_in
> 0xff)
3526 if (gbl
->fom_out
> 0xff)
3527 gbl
->fom_out
= 0xff;
3529 /* Update the FOM in the register file */
3530 debug_info
= gbl
->fom_in
;
3531 debug_info
|= gbl
->fom_out
<< 8;
3532 writel(debug_info
, &sdr_reg_file
->fom
);
3534 writel(debug_info
, &phy_mgr_cfg
->cal_debug_info
);
3535 writel(PHY_MGR_CAL_SUCCESS
, &phy_mgr_cfg
->cal_status
);
3537 printf("%s: CALIBRATION FAILED\n", __FILE__
);
3539 debug_info
= gbl
->error_stage
;
3540 debug_info
|= gbl
->error_substage
<< 8;
3541 debug_info
|= gbl
->error_group
<< 16;
3543 writel(debug_info
, &sdr_reg_file
->failing_stage
);
3544 writel(debug_info
, &phy_mgr_cfg
->cal_debug_info
);
3545 writel(PHY_MGR_CAL_FAIL
, &phy_mgr_cfg
->cal_status
);
3547 /* Update the failing group/stage in the register file */
3548 debug_info
= gbl
->error_stage
;
3549 debug_info
|= gbl
->error_substage
<< 8;
3550 debug_info
|= gbl
->error_group
<< 16;
3551 writel(debug_info
, &sdr_reg_file
->failing_stage
);
3554 printf("%s: Calibration complete\n", __FILE__
);
3558 * hc_initialize_rom_data() - Initialize ROM data
3560 * Initialize ROM data.
3562 static void hc_initialize_rom_data(void)
3564 unsigned int nelem
= 0;
3565 const u32
*rom_init
;
3568 socfpga_get_seq_inst_init(&rom_init
, &nelem
);
3569 addr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
| RW_MGR_INST_ROM_WRITE_OFFSET
;
3570 for (i
= 0; i
< nelem
; i
++)
3571 writel(rom_init
[i
], addr
+ (i
<< 2));
3573 socfpga_get_seq_ac_init(&rom_init
, &nelem
);
3574 addr
= SDR_PHYGRP_RWMGRGRP_ADDRESS
| RW_MGR_AC_ROM_WRITE_OFFSET
;
3575 for (i
= 0; i
< nelem
; i
++)
3576 writel(rom_init
[i
], addr
+ (i
<< 2));
3580 * initialize_reg_file() - Initialize SDR register file
3582 * Initialize SDR register file.
3584 static void initialize_reg_file(void)
3586 /* Initialize the register file with the correct data */
3587 writel(REG_FILE_INIT_SEQ_SIGNATURE
, &sdr_reg_file
->signature
);
3588 writel(0, &sdr_reg_file
->debug_data_addr
);
3589 writel(0, &sdr_reg_file
->cur_stage
);
3590 writel(0, &sdr_reg_file
->fom
);
3591 writel(0, &sdr_reg_file
->failing_stage
);
3592 writel(0, &sdr_reg_file
->debug1
);
3593 writel(0, &sdr_reg_file
->debug2
);
3597 * initialize_hps_phy() - Initialize HPS PHY
3599 * Initialize HPS PHY.
3601 static void initialize_hps_phy(void)
3605 * Tracking also gets configured here because it's in the
3608 uint32_t trk_sample_count
= 7500;
3609 uint32_t trk_long_idle_sample_count
= (10 << 16) | 100;
3611 * Format is number of outer loops in the 16 MSB, sample
3616 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3617 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3618 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3619 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3620 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3621 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3623 * This field selects the intrinsic latency to RDATA_EN/FULL path.
3624 * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3626 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3627 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3629 writel(reg
, &sdr_ctrl
->phy_ctrl0
);
3632 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3634 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH
);
3635 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3636 trk_long_idle_sample_count
);
3637 writel(reg
, &sdr_ctrl
->phy_ctrl1
);
3640 reg
|= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3641 trk_long_idle_sample_count
>>
3642 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH
);
3643 writel(reg
, &sdr_ctrl
->phy_ctrl2
);
3647 * initialize_tracking() - Initialize tracking
3649 * Initialize the register file with usable initial data.
3651 static void initialize_tracking(void)
3654 * Initialize the register file with the correct data.
3655 * Compute usable version of value in case we skip full
3656 * computation later.
3658 writel(DIV_ROUND_UP(iocfg
->delay_per_opa_tap
, iocfg
->delay_per_dchain_tap
) - 1,
3659 &sdr_reg_file
->dtaps_per_ptap
);
3661 /* trk_sample_count */
3662 writel(7500, &sdr_reg_file
->trk_sample_count
);
3664 /* longidle outer loop [15:0] */
3665 writel((10 << 16) | (100 << 0), &sdr_reg_file
->trk_longidle
);
3668 * longidle sample count [31:24]
3669 * trfc, worst case of 933Mhz 4Gb [23:16]
3670 * trcd, worst case [15:8]
3673 writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3674 &sdr_reg_file
->delays
);
3677 writel((rwcfg
->idle
<< 24) | (rwcfg
->activate_1
<< 16) |
3678 (rwcfg
->sgle_read
<< 8) | (rwcfg
->precharge_all
<< 0),
3679 &sdr_reg_file
->trk_rw_mgr_addr
);
3681 writel(rwcfg
->mem_if_read_dqs_width
,
3682 &sdr_reg_file
->trk_read_dqs_width
);
3685 writel((rwcfg
->refresh_all
<< 24) | (1000 << 0),
3686 &sdr_reg_file
->trk_rfsh
);
3689 int sdram_calibration_full(void)
3691 struct param_type my_param
;
3692 struct gbl_type my_gbl
;
3695 memset(&my_param
, 0, sizeof(my_param
));
3696 memset(&my_gbl
, 0, sizeof(my_gbl
));
3701 rwcfg
= socfpga_get_sdram_rwmgr_config();
3702 iocfg
= socfpga_get_sdram_io_config();
3704 /* Set the calibration enabled by default */
3705 gbl
->phy_debug_mode_flags
|= PHY_DEBUG_ENABLE_CAL_RPT
;
3707 * Only sweep all groups (regardless of fail state) by default
3708 * Set enabled read test by default.
3710 #if DISABLE_GUARANTEED_READ
3711 gbl
->phy_debug_mode_flags
|= PHY_DEBUG_DISABLE_GUARANTEED_READ
;
3713 /* Initialize the register file */
3714 initialize_reg_file();
3716 /* Initialize any PHY CSR */
3717 initialize_hps_phy();
3719 scc_mgr_initialize();
3721 initialize_tracking();
3723 printf("%s: Preparing to start memory calibration\n", __FILE__
);
3725 debug("%s:%d\n", __func__
, __LINE__
);
3726 debug_cond(DLEVEL
== 1,
3727 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3728 rwcfg
->mem_number_of_ranks
, rwcfg
->mem_number_of_cs_per_dimm
,
3729 rwcfg
->mem_dq_per_read_dqs
, rwcfg
->mem_dq_per_write_dqs
,
3730 rwcfg
->mem_virtual_groups_per_read_dqs
,
3731 rwcfg
->mem_virtual_groups_per_write_dqs
);
3732 debug_cond(DLEVEL
== 1,
3733 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3734 rwcfg
->mem_if_read_dqs_width
, rwcfg
->mem_if_write_dqs_width
,
3735 rwcfg
->mem_data_width
, rwcfg
->mem_data_mask_width
,
3736 iocfg
->delay_per_opa_tap
, iocfg
->delay_per_dchain_tap
);
3737 debug_cond(DLEVEL
== 1, "dtap_dqsen_delay=%u, dll=%u",
3738 iocfg
->delay_per_dqs_en_dchain_tap
, iocfg
->dll_chain_length
);
3739 debug_cond(DLEVEL
== 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3740 iocfg
->dqs_en_phase_max
, iocfg
->dqdqs_out_phase_max
,
3741 iocfg
->dqs_en_delay_max
, iocfg
->dqs_in_delay_max
);
3742 debug_cond(DLEVEL
== 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3743 iocfg
->io_in_delay_max
, iocfg
->io_out1_delay_max
,
3744 iocfg
->io_out2_delay_max
);
3745 debug_cond(DLEVEL
== 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3746 iocfg
->dqs_in_reserve
, iocfg
->dqs_out_reserve
);
3748 hc_initialize_rom_data();
3750 /* update info for sims */
3751 reg_file_set_stage(CAL_STAGE_NIL
);
3752 reg_file_set_group(0);
3755 * Load global needed for those actions that require
3756 * some dynamic calibration support.
3758 dyn_calib_steps
= STATIC_CALIB_STEPS
;
3760 * Load global to allow dynamic selection of delay loop settings
3761 * based on calibration mode.
3763 if (!(dyn_calib_steps
& CALIB_SKIP_DELAY_LOOPS
))
3764 skip_delay_mask
= 0xff;
3766 skip_delay_mask
= 0x0;
3768 pass
= run_mem_calibrate();
3769 debug_mem_calibrate(pass
);