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Merge branch 'master' of git://git.denx.de/u-boot-usb
[people/ms/u-boot.git] / drivers / ddr / fsl / ctrl_regs.c
1 /*
2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 /*
8 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
9 * Based on code from spd_sdram.c
10 * Author: James Yang [at freescale.com]
11 */
12
13 #include <common.h>
14 #include <fsl_ddr_sdram.h>
15
16 #include <fsl_ddr.h>
17 #include <fsl_immap.h>
18 #include <asm/io.h>
19
20 unsigned int picos_to_mclk(unsigned int picos);
21
22 /*
23 * Determine Rtt value.
24 *
25 * This should likely be either board or controller specific.
26 *
27 * Rtt(nominal) - DDR2:
28 * 0 = Rtt disabled
29 * 1 = 75 ohm
30 * 2 = 150 ohm
31 * 3 = 50 ohm
32 * Rtt(nominal) - DDR3:
33 * 0 = Rtt disabled
34 * 1 = 60 ohm
35 * 2 = 120 ohm
36 * 3 = 40 ohm
37 * 4 = 20 ohm
38 * 5 = 30 ohm
39 *
40 * FIXME: Apparently 8641 needs a value of 2
41 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
42 *
43 * FIXME: There was some effort down this line earlier:
44 *
45 * unsigned int i;
46 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
47 * if (popts->dimmslot[i].num_valid_cs
48 * && (popts->cs_local_opts[2*i].odt_rd_cfg
49 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
50 * rtt = 2;
51 * break;
52 * }
53 * }
54 */
55 static inline int fsl_ddr_get_rtt(void)
56 {
57 int rtt;
58
59 #if defined(CONFIG_SYS_FSL_DDR1)
60 rtt = 0;
61 #elif defined(CONFIG_SYS_FSL_DDR2)
62 rtt = 3;
63 #else
64 rtt = 0;
65 #endif
66
67 return rtt;
68 }
69
70 #ifdef CONFIG_SYS_FSL_DDR4
71 /*
72 * compute CAS write latency according to DDR4 spec
73 * CWL = 9 for <= 1600MT/s
74 * 10 for <= 1866MT/s
75 * 11 for <= 2133MT/s
76 * 12 for <= 2400MT/s
77 * 14 for <= 2667MT/s
78 * 16 for <= 2933MT/s
79 * 18 for higher
80 */
81 static inline unsigned int compute_cas_write_latency(void)
82 {
83 unsigned int cwl;
84 const unsigned int mclk_ps = get_memory_clk_period_ps();
85 if (mclk_ps >= 1250)
86 cwl = 9;
87 else if (mclk_ps >= 1070)
88 cwl = 10;
89 else if (mclk_ps >= 935)
90 cwl = 11;
91 else if (mclk_ps >= 833)
92 cwl = 12;
93 else if (mclk_ps >= 750)
94 cwl = 14;
95 else if (mclk_ps >= 681)
96 cwl = 16;
97 else
98 cwl = 18;
99
100 return cwl;
101 }
102 #else
103 /*
104 * compute the CAS write latency according to DDR3 spec
105 * CWL = 5 if tCK >= 2.5ns
106 * 6 if 2.5ns > tCK >= 1.875ns
107 * 7 if 1.875ns > tCK >= 1.5ns
108 * 8 if 1.5ns > tCK >= 1.25ns
109 * 9 if 1.25ns > tCK >= 1.07ns
110 * 10 if 1.07ns > tCK >= 0.935ns
111 * 11 if 0.935ns > tCK >= 0.833ns
112 * 12 if 0.833ns > tCK >= 0.75ns
113 */
114 static inline unsigned int compute_cas_write_latency(void)
115 {
116 unsigned int cwl;
117 const unsigned int mclk_ps = get_memory_clk_period_ps();
118
119 if (mclk_ps >= 2500)
120 cwl = 5;
121 else if (mclk_ps >= 1875)
122 cwl = 6;
123 else if (mclk_ps >= 1500)
124 cwl = 7;
125 else if (mclk_ps >= 1250)
126 cwl = 8;
127 else if (mclk_ps >= 1070)
128 cwl = 9;
129 else if (mclk_ps >= 935)
130 cwl = 10;
131 else if (mclk_ps >= 833)
132 cwl = 11;
133 else if (mclk_ps >= 750)
134 cwl = 12;
135 else {
136 cwl = 12;
137 printf("Warning: CWL is out of range\n");
138 }
139 return cwl;
140 }
141 #endif
142
143 /* Chip Select Configuration (CSn_CONFIG) */
144 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
145 const memctl_options_t *popts,
146 const dimm_params_t *dimm_params)
147 {
148 unsigned int cs_n_en = 0; /* Chip Select enable */
149 unsigned int intlv_en = 0; /* Memory controller interleave enable */
150 unsigned int intlv_ctl = 0; /* Interleaving control */
151 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
152 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
153 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
154 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
155 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
156 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
157 int go_config = 0;
158 #ifdef CONFIG_SYS_FSL_DDR4
159 unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */
160 #else
161 unsigned int n_banks_per_sdram_device;
162 #endif
163
164 /* Compute CS_CONFIG only for existing ranks of each DIMM. */
165 switch (i) {
166 case 0:
167 if (dimm_params[dimm_number].n_ranks > 0) {
168 go_config = 1;
169 /* These fields only available in CS0_CONFIG */
170 if (!popts->memctl_interleaving)
171 break;
172 switch (popts->memctl_interleaving_mode) {
173 case FSL_DDR_256B_INTERLEAVING:
174 case FSL_DDR_CACHE_LINE_INTERLEAVING:
175 case FSL_DDR_PAGE_INTERLEAVING:
176 case FSL_DDR_BANK_INTERLEAVING:
177 case FSL_DDR_SUPERBANK_INTERLEAVING:
178 intlv_en = popts->memctl_interleaving;
179 intlv_ctl = popts->memctl_interleaving_mode;
180 break;
181 default:
182 break;
183 }
184 }
185 break;
186 case 1:
187 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
188 (dimm_number == 1 && dimm_params[1].n_ranks > 0))
189 go_config = 1;
190 break;
191 case 2:
192 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
193 (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
194 go_config = 1;
195 break;
196 case 3:
197 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
198 (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
199 (dimm_number == 3 && dimm_params[3].n_ranks > 0))
200 go_config = 1;
201 break;
202 default:
203 break;
204 }
205 if (go_config) {
206 cs_n_en = 1;
207 ap_n_en = popts->cs_local_opts[i].auto_precharge;
208 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
209 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
210 #ifdef CONFIG_SYS_FSL_DDR4
211 ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;
212 bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
213 #else
214 n_banks_per_sdram_device
215 = dimm_params[dimm_number].n_banks_per_sdram_device;
216 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
217 #endif
218 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
219 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
220 }
221 ddr->cs[i].config = (0
222 | ((cs_n_en & 0x1) << 31)
223 | ((intlv_en & 0x3) << 29)
224 | ((intlv_ctl & 0xf) << 24)
225 | ((ap_n_en & 0x1) << 23)
226
227 /* XXX: some implementation only have 1 bit starting at left */
228 | ((odt_rd_cfg & 0x7) << 20)
229
230 /* XXX: Some implementation only have 1 bit starting at left */
231 | ((odt_wr_cfg & 0x7) << 16)
232
233 | ((ba_bits_cs_n & 0x3) << 14)
234 | ((row_bits_cs_n & 0x7) << 8)
235 #ifdef CONFIG_SYS_FSL_DDR4
236 | ((bg_bits_cs_n & 0x3) << 4)
237 #endif
238 | ((col_bits_cs_n & 0x7) << 0)
239 );
240 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
241 }
242
243 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
244 /* FIXME: 8572 */
245 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
246 {
247 unsigned int pasr_cfg = 0; /* Partial array self refresh config */
248
249 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
250 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
251 }
252
253 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
254
255 #if !defined(CONFIG_SYS_FSL_DDR1)
256 /*
257 * Check DIMM configuration, return 2 if quad-rank or two dual-rank
258 * Return 1 if other two slots configuration. Return 0 if single slot.
259 */
260 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
261 {
262 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
263 if (dimm_params[0].n_ranks == 4)
264 return 2;
265 #endif
266
267 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
268 if ((dimm_params[0].n_ranks == 2) &&
269 (dimm_params[1].n_ranks == 2))
270 return 2;
271
272 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
273 if (dimm_params[0].n_ranks == 4)
274 return 2;
275 #endif
276
277 if ((dimm_params[0].n_ranks != 0) &&
278 (dimm_params[2].n_ranks != 0))
279 return 1;
280 #endif
281 return 0;
282 }
283
284 /*
285 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
286 *
287 * Avoid writing for DDR I. The new PQ38 DDR controller
288 * dreams up non-zero default values to be backwards compatible.
289 */
290 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
291 const memctl_options_t *popts,
292 const dimm_params_t *dimm_params)
293 {
294 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
295 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
296 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
297 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
298 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
299
300 /* Active powerdown exit timing (tXARD and tXARDS). */
301 unsigned char act_pd_exit_mclk;
302 /* Precharge powerdown exit timing (tXP). */
303 unsigned char pre_pd_exit_mclk;
304 /* ODT powerdown exit timing (tAXPD). */
305 unsigned char taxpd_mclk = 0;
306 /* Mode register set cycle time (tMRD). */
307 unsigned char tmrd_mclk;
308 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
309 const unsigned int mclk_ps = get_memory_clk_period_ps();
310 #endif
311
312 #ifdef CONFIG_SYS_FSL_DDR4
313 /* tXP=max(4nCK, 6ns) */
314 int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
315 trwt_mclk = 2;
316 twrt_mclk = 1;
317 act_pd_exit_mclk = picos_to_mclk(txp);
318 pre_pd_exit_mclk = act_pd_exit_mclk;
319 /*
320 * MRS_CYC = max(tMRD, tMOD)
321 * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
322 */
323 tmrd_mclk = max(24U, picos_to_mclk(15000));
324 #elif defined(CONFIG_SYS_FSL_DDR3)
325 unsigned int data_rate = get_ddr_freq(0);
326 int txp;
327 unsigned int ip_rev;
328 int odt_overlap;
329 /*
330 * (tXARD and tXARDS). Empirical?
331 * The DDR3 spec has not tXARD,
332 * we use the tXP instead of it.
333 * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066
334 * max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133
335 * spec has not the tAXPD, we use
336 * tAXPD=1, need design to confirm.
337 */
338 txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
339
340 ip_rev = fsl_ddr_get_version();
341 if (ip_rev >= 0x40700) {
342 /*
343 * MRS_CYC = max(tMRD, tMOD)
344 * tMRD = 4nCK (8nCK for RDIMM)
345 * tMOD = max(12nCK, 15ns)
346 */
347 tmrd_mclk = max((unsigned int)12, picos_to_mclk(15000));
348 } else {
349 /*
350 * MRS_CYC = tMRD
351 * tMRD = 4nCK (8nCK for RDIMM)
352 */
353 if (popts->registered_dimm_en)
354 tmrd_mclk = 8;
355 else
356 tmrd_mclk = 4;
357 }
358
359 /* set the turnaround time */
360
361 /*
362 * for single quad-rank DIMM and two-slot DIMMs
363 * to avoid ODT overlap
364 */
365 odt_overlap = avoid_odt_overlap(dimm_params);
366 switch (odt_overlap) {
367 case 2:
368 twwt_mclk = 2;
369 trrt_mclk = 1;
370 break;
371 case 1:
372 twwt_mclk = 1;
373 trrt_mclk = 0;
374 break;
375 default:
376 break;
377 }
378
379 /* for faster clock, need more time for data setup */
380 trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
381
382 if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
383 twrt_mclk = 1;
384
385 if (popts->dynamic_power == 0) { /* powerdown is not used */
386 act_pd_exit_mclk = 1;
387 pre_pd_exit_mclk = 1;
388 taxpd_mclk = 1;
389 } else {
390 /* act_pd_exit_mclk = tXARD, see above */
391 act_pd_exit_mclk = picos_to_mclk(txp);
392 /* Mode register MR0[A12] is '1' - fast exit */
393 pre_pd_exit_mclk = act_pd_exit_mclk;
394 taxpd_mclk = 1;
395 }
396 #else /* CONFIG_SYS_FSL_DDR2 */
397 /*
398 * (tXARD and tXARDS). Empirical?
399 * tXARD = 2 for DDR2
400 * tXP=2
401 * tAXPD=8
402 */
403 act_pd_exit_mclk = 2;
404 pre_pd_exit_mclk = 2;
405 taxpd_mclk = 8;
406 tmrd_mclk = 2;
407 #endif
408
409 if (popts->trwt_override)
410 trwt_mclk = popts->trwt;
411
412 ddr->timing_cfg_0 = (0
413 | ((trwt_mclk & 0x3) << 30) /* RWT */
414 | ((twrt_mclk & 0x3) << 28) /* WRT */
415 | ((trrt_mclk & 0x3) << 26) /* RRT */
416 | ((twwt_mclk & 0x3) << 24) /* WWT */
417 | ((act_pd_exit_mclk & 0xf) << 20) /* ACT_PD_EXIT */
418 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
419 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
420 | ((tmrd_mclk & 0x1f) << 0) /* MRS_CYC */
421 );
422 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
423 }
424 #endif /* !defined(CONFIG_SYS_FSL_DDR1) */
425
426 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
427 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
428 const memctl_options_t *popts,
429 const common_timing_params_t *common_dimm,
430 unsigned int cas_latency,
431 unsigned int additive_latency)
432 {
433 /* Extended precharge to activate interval (tRP) */
434 unsigned int ext_pretoact = 0;
435 /* Extended Activate to precharge interval (tRAS) */
436 unsigned int ext_acttopre = 0;
437 /* Extended activate to read/write interval (tRCD) */
438 unsigned int ext_acttorw = 0;
439 /* Extended refresh recovery time (tRFC) */
440 unsigned int ext_refrec;
441 /* Extended MCAS latency from READ cmd */
442 unsigned int ext_caslat = 0;
443 /* Extended additive latency */
444 unsigned int ext_add_lat = 0;
445 /* Extended last data to precharge interval (tWR) */
446 unsigned int ext_wrrec = 0;
447 /* Control Adjust */
448 unsigned int cntl_adj = 0;
449
450 ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4;
451 ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4;
452 ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4;
453 ext_caslat = (2 * cas_latency - 1) >> 4;
454 ext_add_lat = additive_latency >> 4;
455 #ifdef CONFIG_SYS_FSL_DDR4
456 ext_refrec = (picos_to_mclk(common_dimm->trfc1_ps) - 8) >> 4;
457 #else
458 ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4;
459 /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
460 #endif
461 ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) +
462 (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
463
464 ddr->timing_cfg_3 = (0
465 | ((ext_pretoact & 0x1) << 28)
466 | ((ext_acttopre & 0x3) << 24)
467 | ((ext_acttorw & 0x1) << 22)
468 | ((ext_refrec & 0x1F) << 16)
469 | ((ext_caslat & 0x3) << 12)
470 | ((ext_add_lat & 0x1) << 10)
471 | ((ext_wrrec & 0x1) << 8)
472 | ((cntl_adj & 0x7) << 0)
473 );
474 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
475 }
476
477 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
478 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
479 const memctl_options_t *popts,
480 const common_timing_params_t *common_dimm,
481 unsigned int cas_latency)
482 {
483 /* Precharge-to-activate interval (tRP) */
484 unsigned char pretoact_mclk;
485 /* Activate to precharge interval (tRAS) */
486 unsigned char acttopre_mclk;
487 /* Activate to read/write interval (tRCD) */
488 unsigned char acttorw_mclk;
489 /* CASLAT */
490 unsigned char caslat_ctrl;
491 /* Refresh recovery time (tRFC) ; trfc_low */
492 unsigned char refrec_ctrl;
493 /* Last data to precharge minimum interval (tWR) */
494 unsigned char wrrec_mclk;
495 /* Activate-to-activate interval (tRRD) */
496 unsigned char acttoact_mclk;
497 /* Last write data pair to read command issue interval (tWTR) */
498 unsigned char wrtord_mclk;
499 #ifdef CONFIG_SYS_FSL_DDR4
500 /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
501 static const u8 wrrec_table[] = {
502 10, 10, 10, 10, 10,
503 10, 10, 10, 10, 10,
504 12, 12, 14, 14, 16,
505 16, 18, 18, 20, 20,
506 24, 24, 24, 24};
507 #else
508 /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
509 static const u8 wrrec_table[] = {
510 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
511 #endif
512
513 pretoact_mclk = picos_to_mclk(common_dimm->trp_ps);
514 acttopre_mclk = picos_to_mclk(common_dimm->tras_ps);
515 acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps);
516
517 /*
518 * Translate CAS Latency to a DDR controller field value:
519 *
520 * CAS Lat DDR I DDR II Ctrl
521 * Clocks SPD Bit SPD Bit Value
522 * ------- ------- ------- -----
523 * 1.0 0 0001
524 * 1.5 1 0010
525 * 2.0 2 2 0011
526 * 2.5 3 0100
527 * 3.0 4 3 0101
528 * 3.5 5 0110
529 * 4.0 4 0111
530 * 4.5 1000
531 * 5.0 5 1001
532 */
533 #if defined(CONFIG_SYS_FSL_DDR1)
534 caslat_ctrl = (cas_latency + 1) & 0x07;
535 #elif defined(CONFIG_SYS_FSL_DDR2)
536 caslat_ctrl = 2 * cas_latency - 1;
537 #else
538 /*
539 * if the CAS latency more than 8 cycle,
540 * we need set extend bit for it at
541 * TIMING_CFG_3[EXT_CASLAT]
542 */
543 if (fsl_ddr_get_version() <= 0x40400)
544 caslat_ctrl = 2 * cas_latency - 1;
545 else
546 caslat_ctrl = (cas_latency - 1) << 1;
547 #endif
548
549 #ifdef CONFIG_SYS_FSL_DDR4
550 refrec_ctrl = picos_to_mclk(common_dimm->trfc1_ps) - 8;
551 wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
552 acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4U);
553 wrtord_mclk = max(2U, picos_to_mclk(2500));
554 if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
555 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
556 else
557 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
558 #else
559 refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8;
560 wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
561 acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps);
562 wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps);
563 if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
564 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
565 else
566 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
567 #endif
568 if (popts->otf_burst_chop_en)
569 wrrec_mclk += 2;
570
571 /*
572 * JEDEC has min requirement for tRRD
573 */
574 #if defined(CONFIG_SYS_FSL_DDR3)
575 if (acttoact_mclk < 4)
576 acttoact_mclk = 4;
577 #endif
578 /*
579 * JEDEC has some min requirements for tWTR
580 */
581 #if defined(CONFIG_SYS_FSL_DDR2)
582 if (wrtord_mclk < 2)
583 wrtord_mclk = 2;
584 #elif defined(CONFIG_SYS_FSL_DDR3)
585 if (wrtord_mclk < 4)
586 wrtord_mclk = 4;
587 #endif
588 if (popts->otf_burst_chop_en)
589 wrtord_mclk += 2;
590
591 ddr->timing_cfg_1 = (0
592 | ((pretoact_mclk & 0x0F) << 28)
593 | ((acttopre_mclk & 0x0F) << 24)
594 | ((acttorw_mclk & 0xF) << 20)
595 | ((caslat_ctrl & 0xF) << 16)
596 | ((refrec_ctrl & 0xF) << 12)
597 | ((wrrec_mclk & 0x0F) << 8)
598 | ((acttoact_mclk & 0x0F) << 4)
599 | ((wrtord_mclk & 0x0F) << 0)
600 );
601 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
602 }
603
604 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
605 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
606 const memctl_options_t *popts,
607 const common_timing_params_t *common_dimm,
608 unsigned int cas_latency,
609 unsigned int additive_latency)
610 {
611 /* Additive latency */
612 unsigned char add_lat_mclk;
613 /* CAS-to-preamble override */
614 unsigned short cpo;
615 /* Write latency */
616 unsigned char wr_lat;
617 /* Read to precharge (tRTP) */
618 unsigned char rd_to_pre;
619 /* Write command to write data strobe timing adjustment */
620 unsigned char wr_data_delay;
621 /* Minimum CKE pulse width (tCKE) */
622 unsigned char cke_pls;
623 /* Window for four activates (tFAW) */
624 unsigned short four_act;
625 #ifdef CONFIG_SYS_FSL_DDR3
626 const unsigned int mclk_ps = get_memory_clk_period_ps();
627 #endif
628
629 /* FIXME add check that this must be less than acttorw_mclk */
630 add_lat_mclk = additive_latency;
631 cpo = popts->cpo_override;
632
633 #if defined(CONFIG_SYS_FSL_DDR1)
634 /*
635 * This is a lie. It should really be 1, but if it is
636 * set to 1, bits overlap into the old controller's
637 * otherwise unused ACSM field. If we leave it 0, then
638 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
639 */
640 wr_lat = 0;
641 #elif defined(CONFIG_SYS_FSL_DDR2)
642 wr_lat = cas_latency - 1;
643 #else
644 wr_lat = compute_cas_write_latency();
645 #endif
646
647 #ifdef CONFIG_SYS_FSL_DDR4
648 rd_to_pre = picos_to_mclk(7500);
649 #else
650 rd_to_pre = picos_to_mclk(common_dimm->trtp_ps);
651 #endif
652 /*
653 * JEDEC has some min requirements for tRTP
654 */
655 #if defined(CONFIG_SYS_FSL_DDR2)
656 if (rd_to_pre < 2)
657 rd_to_pre = 2;
658 #elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
659 if (rd_to_pre < 4)
660 rd_to_pre = 4;
661 #endif
662 if (popts->otf_burst_chop_en)
663 rd_to_pre += 2; /* according to UM */
664
665 wr_data_delay = popts->write_data_delay;
666 #ifdef CONFIG_SYS_FSL_DDR4
667 cpo = 0;
668 cke_pls = max(3U, picos_to_mclk(5000));
669 #elif defined(CONFIG_SYS_FSL_DDR3)
670 /*
671 * cke pulse = max(3nCK, 7.5ns) for DDR3-800
672 * max(3nCK, 5.625ns) for DDR3-1066, 1333
673 * max(3nCK, 5ns) for DDR3-1600, 1866, 2133
674 */
675 cke_pls = max(3U, picos_to_mclk(mclk_ps > 1870 ? 7500 :
676 (mclk_ps > 1245 ? 5625 : 5000)));
677 #else
678 cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
679 #endif
680 four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps);
681
682 ddr->timing_cfg_2 = (0
683 | ((add_lat_mclk & 0xf) << 28)
684 | ((cpo & 0x1f) << 23)
685 | ((wr_lat & 0xf) << 19)
686 | ((wr_lat & 0x10) << 14)
687 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
688 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
689 | ((cke_pls & 0x7) << 6)
690 | ((four_act & 0x3f) << 0)
691 );
692 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
693 }
694
695 /* DDR SDRAM Register Control Word */
696 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
697 const memctl_options_t *popts,
698 const common_timing_params_t *common_dimm)
699 {
700 if (common_dimm->all_dimms_registered &&
701 !common_dimm->all_dimms_unbuffered) {
702 if (popts->rcw_override) {
703 ddr->ddr_sdram_rcw_1 = popts->rcw_1;
704 ddr->ddr_sdram_rcw_2 = popts->rcw_2;
705 } else {
706 ddr->ddr_sdram_rcw_1 =
707 common_dimm->rcw[0] << 28 | \
708 common_dimm->rcw[1] << 24 | \
709 common_dimm->rcw[2] << 20 | \
710 common_dimm->rcw[3] << 16 | \
711 common_dimm->rcw[4] << 12 | \
712 common_dimm->rcw[5] << 8 | \
713 common_dimm->rcw[6] << 4 | \
714 common_dimm->rcw[7];
715 ddr->ddr_sdram_rcw_2 =
716 common_dimm->rcw[8] << 28 | \
717 common_dimm->rcw[9] << 24 | \
718 common_dimm->rcw[10] << 20 | \
719 common_dimm->rcw[11] << 16 | \
720 common_dimm->rcw[12] << 12 | \
721 common_dimm->rcw[13] << 8 | \
722 common_dimm->rcw[14] << 4 | \
723 common_dimm->rcw[15];
724 }
725 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
726 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
727 }
728 }
729
730 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
731 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
732 const memctl_options_t *popts,
733 const common_timing_params_t *common_dimm)
734 {
735 unsigned int mem_en; /* DDR SDRAM interface logic enable */
736 unsigned int sren; /* Self refresh enable (during sleep) */
737 unsigned int ecc_en; /* ECC enable. */
738 unsigned int rd_en; /* Registered DIMM enable */
739 unsigned int sdram_type; /* Type of SDRAM */
740 unsigned int dyn_pwr; /* Dynamic power management mode */
741 unsigned int dbw; /* DRAM dta bus width */
742 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
743 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
744 unsigned int threet_en; /* Enable 3T timing */
745 unsigned int twot_en; /* Enable 2T timing */
746 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
747 unsigned int x32_en = 0; /* x32 enable */
748 unsigned int pchb8 = 0; /* precharge bit 8 enable */
749 unsigned int hse; /* Global half strength override */
750 unsigned int acc_ecc_en = 0; /* Accumulated ECC enable */
751 unsigned int mem_halt = 0; /* memory controller halt */
752 unsigned int bi = 0; /* Bypass initialization */
753
754 mem_en = 1;
755 sren = popts->self_refresh_in_sleep;
756 if (common_dimm->all_dimms_ecc_capable) {
757 /* Allow setting of ECC only if all DIMMs are ECC. */
758 ecc_en = popts->ecc_mode;
759 } else {
760 ecc_en = 0;
761 }
762
763 if (common_dimm->all_dimms_registered &&
764 !common_dimm->all_dimms_unbuffered) {
765 rd_en = 1;
766 twot_en = 0;
767 } else {
768 rd_en = 0;
769 twot_en = popts->twot_en;
770 }
771
772 sdram_type = CONFIG_FSL_SDRAM_TYPE;
773
774 dyn_pwr = popts->dynamic_power;
775 dbw = popts->data_bus_width;
776 /* 8-beat burst enable DDR-III case
777 * we must clear it when use the on-the-fly mode,
778 * must set it when use the 32-bits bus mode.
779 */
780 if ((sdram_type == SDRAM_TYPE_DDR3) ||
781 (sdram_type == SDRAM_TYPE_DDR4)) {
782 if (popts->burst_length == DDR_BL8)
783 eight_be = 1;
784 if (popts->burst_length == DDR_OTF)
785 eight_be = 0;
786 if (dbw == 0x1)
787 eight_be = 1;
788 }
789
790 threet_en = popts->threet_en;
791 ba_intlv_ctl = popts->ba_intlv_ctl;
792 hse = popts->half_strength_driver_enable;
793
794 /* set when ddr bus width < 64 */
795 acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
796
797 ddr->ddr_sdram_cfg = (0
798 | ((mem_en & 0x1) << 31)
799 | ((sren & 0x1) << 30)
800 | ((ecc_en & 0x1) << 29)
801 | ((rd_en & 0x1) << 28)
802 | ((sdram_type & 0x7) << 24)
803 | ((dyn_pwr & 0x1) << 21)
804 | ((dbw & 0x3) << 19)
805 | ((eight_be & 0x1) << 18)
806 | ((ncap & 0x1) << 17)
807 | ((threet_en & 0x1) << 16)
808 | ((twot_en & 0x1) << 15)
809 | ((ba_intlv_ctl & 0x7F) << 8)
810 | ((x32_en & 0x1) << 5)
811 | ((pchb8 & 0x1) << 4)
812 | ((hse & 0x1) << 3)
813 | ((acc_ecc_en & 0x1) << 2)
814 | ((mem_halt & 0x1) << 1)
815 | ((bi & 0x1) << 0)
816 );
817 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
818 }
819
820 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
821 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
822 const memctl_options_t *popts,
823 const unsigned int unq_mrs_en)
824 {
825 unsigned int frc_sr = 0; /* Force self refresh */
826 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
827 unsigned int odt_cfg = 0; /* ODT configuration */
828 unsigned int num_pr; /* Number of posted refreshes */
829 unsigned int slow = 0; /* DDR will be run less than 1250 */
830 unsigned int x4_en = 0; /* x4 DRAM enable */
831 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
832 unsigned int ap_en; /* Address Parity Enable */
833 unsigned int d_init; /* DRAM data initialization */
834 unsigned int rcw_en = 0; /* Register Control Word Enable */
835 unsigned int md_en = 0; /* Mirrored DIMM Enable */
836 unsigned int qd_en = 0; /* quad-rank DIMM Enable */
837 int i;
838 #ifndef CONFIG_SYS_FSL_DDR4
839 unsigned int dll_rst_dis = 1; /* DLL reset disable */
840 unsigned int dqs_cfg; /* DQS configuration */
841
842 dqs_cfg = popts->dqs_config;
843 #endif
844 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
845 if (popts->cs_local_opts[i].odt_rd_cfg
846 || popts->cs_local_opts[i].odt_wr_cfg) {
847 odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
848 break;
849 }
850 }
851
852 num_pr = 1; /* Make this configurable */
853
854 /*
855 * 8572 manual says
856 * {TIMING_CFG_1[PRETOACT]
857 * + [DDR_SDRAM_CFG_2[NUM_PR]
858 * * ({EXT_REFREC || REFREC} + 8 + 2)]}
859 * << DDR_SDRAM_INTERVAL[REFINT]
860 */
861 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
862 obc_cfg = popts->otf_burst_chop_en;
863 #else
864 obc_cfg = 0;
865 #endif
866
867 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
868 slow = get_ddr_freq(0) < 1249000000;
869 #endif
870
871 if (popts->registered_dimm_en) {
872 rcw_en = 1;
873 ap_en = popts->ap_en;
874 } else {
875 ap_en = 0;
876 }
877
878 x4_en = popts->x4_en ? 1 : 0;
879
880 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
881 /* Use the DDR controller to auto initialize memory. */
882 d_init = popts->ecc_init_using_memctl;
883 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
884 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
885 #else
886 /* Memory will be initialized via DMA, or not at all. */
887 d_init = 0;
888 #endif
889
890 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
891 md_en = popts->mirrored_dimm;
892 #endif
893 qd_en = popts->quad_rank_present ? 1 : 0;
894 ddr->ddr_sdram_cfg_2 = (0
895 | ((frc_sr & 0x1) << 31)
896 | ((sr_ie & 0x1) << 30)
897 #ifndef CONFIG_SYS_FSL_DDR4
898 | ((dll_rst_dis & 0x1) << 29)
899 | ((dqs_cfg & 0x3) << 26)
900 #endif
901 | ((odt_cfg & 0x3) << 21)
902 | ((num_pr & 0xf) << 12)
903 | ((slow & 1) << 11)
904 | (x4_en << 10)
905 | (qd_en << 9)
906 | (unq_mrs_en << 8)
907 | ((obc_cfg & 0x1) << 6)
908 | ((ap_en & 0x1) << 5)
909 | ((d_init & 0x1) << 4)
910 | ((rcw_en & 0x1) << 2)
911 | ((md_en & 0x1) << 0)
912 );
913 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
914 }
915
916 #ifdef CONFIG_SYS_FSL_DDR4
917 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
918 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
919 const memctl_options_t *popts,
920 const common_timing_params_t *common_dimm,
921 const unsigned int unq_mrs_en)
922 {
923 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
924 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
925 int i;
926 unsigned int wr_crc = 0; /* Disable */
927 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
928 unsigned int srt = 0; /* self-refresh temerature, normal range */
929 unsigned int cwl = compute_cas_write_latency() - 9;
930 unsigned int mpr = 0; /* serial */
931 unsigned int wc_lat;
932 const unsigned int mclk_ps = get_memory_clk_period_ps();
933
934 if (popts->rtt_override)
935 rtt_wr = popts->rtt_wr_override_value;
936 else
937 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
938
939 if (common_dimm->extended_op_srt)
940 srt = common_dimm->extended_op_srt;
941
942 esdmode2 = (0
943 | ((wr_crc & 0x1) << 12)
944 | ((rtt_wr & 0x3) << 9)
945 | ((srt & 0x3) << 6)
946 | ((cwl & 0x7) << 3));
947
948 if (mclk_ps >= 1250)
949 wc_lat = 0;
950 else if (mclk_ps >= 833)
951 wc_lat = 1;
952 else
953 wc_lat = 2;
954
955 esdmode3 = (0
956 | ((mpr & 0x3) << 11)
957 | ((wc_lat & 0x3) << 9));
958
959 ddr->ddr_sdram_mode_2 = (0
960 | ((esdmode2 & 0xFFFF) << 16)
961 | ((esdmode3 & 0xFFFF) << 0)
962 );
963 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
964
965 if (unq_mrs_en) { /* unique mode registers are supported */
966 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
967 if (popts->rtt_override)
968 rtt_wr = popts->rtt_wr_override_value;
969 else
970 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
971
972 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
973 esdmode2 |= (rtt_wr & 0x3) << 9;
974 switch (i) {
975 case 1:
976 ddr->ddr_sdram_mode_4 = (0
977 | ((esdmode2 & 0xFFFF) << 16)
978 | ((esdmode3 & 0xFFFF) << 0)
979 );
980 break;
981 case 2:
982 ddr->ddr_sdram_mode_6 = (0
983 | ((esdmode2 & 0xFFFF) << 16)
984 | ((esdmode3 & 0xFFFF) << 0)
985 );
986 break;
987 case 3:
988 ddr->ddr_sdram_mode_8 = (0
989 | ((esdmode2 & 0xFFFF) << 16)
990 | ((esdmode3 & 0xFFFF) << 0)
991 );
992 break;
993 }
994 }
995 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
996 ddr->ddr_sdram_mode_4);
997 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
998 ddr->ddr_sdram_mode_6);
999 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1000 ddr->ddr_sdram_mode_8);
1001 }
1002 }
1003 #elif defined(CONFIG_SYS_FSL_DDR3)
1004 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1005 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
1006 const memctl_options_t *popts,
1007 const common_timing_params_t *common_dimm,
1008 const unsigned int unq_mrs_en)
1009 {
1010 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
1011 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
1012 int i;
1013 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
1014 unsigned int srt = 0; /* self-refresh temerature, normal range */
1015 unsigned int asr = 0; /* auto self-refresh disable */
1016 unsigned int cwl = compute_cas_write_latency() - 5;
1017 unsigned int pasr = 0; /* partial array self refresh disable */
1018
1019 if (popts->rtt_override)
1020 rtt_wr = popts->rtt_wr_override_value;
1021 else
1022 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
1023
1024 if (common_dimm->extended_op_srt)
1025 srt = common_dimm->extended_op_srt;
1026
1027 esdmode2 = (0
1028 | ((rtt_wr & 0x3) << 9)
1029 | ((srt & 0x1) << 7)
1030 | ((asr & 0x1) << 6)
1031 | ((cwl & 0x7) << 3)
1032 | ((pasr & 0x7) << 0));
1033 ddr->ddr_sdram_mode_2 = (0
1034 | ((esdmode2 & 0xFFFF) << 16)
1035 | ((esdmode3 & 0xFFFF) << 0)
1036 );
1037 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1038
1039 if (unq_mrs_en) { /* unique mode registers are supported */
1040 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1041 if (popts->rtt_override)
1042 rtt_wr = popts->rtt_wr_override_value;
1043 else
1044 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1045
1046 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
1047 esdmode2 |= (rtt_wr & 0x3) << 9;
1048 switch (i) {
1049 case 1:
1050 ddr->ddr_sdram_mode_4 = (0
1051 | ((esdmode2 & 0xFFFF) << 16)
1052 | ((esdmode3 & 0xFFFF) << 0)
1053 );
1054 break;
1055 case 2:
1056 ddr->ddr_sdram_mode_6 = (0
1057 | ((esdmode2 & 0xFFFF) << 16)
1058 | ((esdmode3 & 0xFFFF) << 0)
1059 );
1060 break;
1061 case 3:
1062 ddr->ddr_sdram_mode_8 = (0
1063 | ((esdmode2 & 0xFFFF) << 16)
1064 | ((esdmode3 & 0xFFFF) << 0)
1065 );
1066 break;
1067 }
1068 }
1069 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1070 ddr->ddr_sdram_mode_4);
1071 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1072 ddr->ddr_sdram_mode_6);
1073 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1074 ddr->ddr_sdram_mode_8);
1075 }
1076 }
1077
1078 #else /* for DDR2 and DDR1 */
1079 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1080 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
1081 const memctl_options_t *popts,
1082 const common_timing_params_t *common_dimm,
1083 const unsigned int unq_mrs_en)
1084 {
1085 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
1086 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
1087
1088 ddr->ddr_sdram_mode_2 = (0
1089 | ((esdmode2 & 0xFFFF) << 16)
1090 | ((esdmode3 & 0xFFFF) << 0)
1091 );
1092 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1093 }
1094 #endif
1095
1096 #ifdef CONFIG_SYS_FSL_DDR4
1097 /* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */
1098 static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
1099 const memctl_options_t *popts,
1100 const common_timing_params_t *common_dimm,
1101 const unsigned int unq_mrs_en)
1102 {
1103 int i;
1104 unsigned short esdmode4 = 0; /* Extended SDRAM mode 4 */
1105 unsigned short esdmode5; /* Extended SDRAM mode 5 */
1106
1107 esdmode5 = 0x00000400; /* Data mask enabled */
1108
1109 ddr->ddr_sdram_mode_9 = (0
1110 | ((esdmode4 & 0xffff) << 16)
1111 | ((esdmode5 & 0xffff) << 0)
1112 );
1113 debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9);
1114 if (unq_mrs_en) { /* unique mode registers are supported */
1115 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1116 switch (i) {
1117 case 1:
1118 ddr->ddr_sdram_mode_11 = (0
1119 | ((esdmode4 & 0xFFFF) << 16)
1120 | ((esdmode5 & 0xFFFF) << 0)
1121 );
1122 break;
1123 case 2:
1124 ddr->ddr_sdram_mode_13 = (0
1125 | ((esdmode4 & 0xFFFF) << 16)
1126 | ((esdmode5 & 0xFFFF) << 0)
1127 );
1128 break;
1129 case 3:
1130 ddr->ddr_sdram_mode_15 = (0
1131 | ((esdmode4 & 0xFFFF) << 16)
1132 | ((esdmode5 & 0xFFFF) << 0)
1133 );
1134 break;
1135 }
1136 }
1137 debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n",
1138 ddr->ddr_sdram_mode_11);
1139 debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n",
1140 ddr->ddr_sdram_mode_13);
1141 debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n",
1142 ddr->ddr_sdram_mode_15);
1143 }
1144 }
1145
1146 /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
1147 static void set_ddr_sdram_mode_10(fsl_ddr_cfg_regs_t *ddr,
1148 const memctl_options_t *popts,
1149 const common_timing_params_t *common_dimm,
1150 const unsigned int unq_mrs_en)
1151 {
1152 int i;
1153 unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */
1154 unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */
1155 unsigned int tccdl_min = picos_to_mclk(common_dimm->tccdl_ps);
1156
1157 esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
1158
1159 ddr->ddr_sdram_mode_10 = (0
1160 | ((esdmode6 & 0xffff) << 16)
1161 | ((esdmode7 & 0xffff) << 0)
1162 );
1163 debug("FSLDDR: ddr_sdram_mode_10) = 0x%08x\n", ddr->ddr_sdram_mode_10);
1164 if (unq_mrs_en) { /* unique mode registers are supported */
1165 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1166 switch (i) {
1167 case 1:
1168 ddr->ddr_sdram_mode_12 = (0
1169 | ((esdmode6 & 0xFFFF) << 16)
1170 | ((esdmode7 & 0xFFFF) << 0)
1171 );
1172 break;
1173 case 2:
1174 ddr->ddr_sdram_mode_14 = (0
1175 | ((esdmode6 & 0xFFFF) << 16)
1176 | ((esdmode7 & 0xFFFF) << 0)
1177 );
1178 break;
1179 case 3:
1180 ddr->ddr_sdram_mode_16 = (0
1181 | ((esdmode6 & 0xFFFF) << 16)
1182 | ((esdmode7 & 0xFFFF) << 0)
1183 );
1184 break;
1185 }
1186 }
1187 debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n",
1188 ddr->ddr_sdram_mode_12);
1189 debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n",
1190 ddr->ddr_sdram_mode_14);
1191 debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n",
1192 ddr->ddr_sdram_mode_16);
1193 }
1194 }
1195
1196 #endif
1197
1198 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
1199 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
1200 const memctl_options_t *popts,
1201 const common_timing_params_t *common_dimm)
1202 {
1203 unsigned int refint; /* Refresh interval */
1204 unsigned int bstopre; /* Precharge interval */
1205
1206 refint = picos_to_mclk(common_dimm->refresh_rate_ps);
1207
1208 bstopre = popts->bstopre;
1209
1210 /* refint field used 0x3FFF in earlier controllers */
1211 ddr->ddr_sdram_interval = (0
1212 | ((refint & 0xFFFF) << 16)
1213 | ((bstopre & 0x3FFF) << 0)
1214 );
1215 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
1216 }
1217
1218 #ifdef CONFIG_SYS_FSL_DDR4
1219 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1220 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1221 const memctl_options_t *popts,
1222 const common_timing_params_t *common_dimm,
1223 unsigned int cas_latency,
1224 unsigned int additive_latency,
1225 const unsigned int unq_mrs_en)
1226 {
1227 int i;
1228 unsigned short esdmode; /* Extended SDRAM mode */
1229 unsigned short sdmode; /* SDRAM mode */
1230
1231 /* Mode Register - MR1 */
1232 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
1233 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
1234 unsigned int rtt;
1235 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
1236 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
1237 unsigned int dic = 0; /* Output driver impedance, 40ohm */
1238 unsigned int dll_en = 1; /* DLL Enable 1=Enable (Normal),
1239 0=Disable (Test/Debug) */
1240
1241 /* Mode Register - MR0 */
1242 unsigned int wr = 0; /* Write Recovery */
1243 unsigned int dll_rst; /* DLL Reset */
1244 unsigned int mode; /* Normal=0 or Test=1 */
1245 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1246 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1247 unsigned int bt;
1248 unsigned int bl; /* BL: Burst Length */
1249
1250 unsigned int wr_mclk;
1251 /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
1252 static const u8 wr_table[] = {
1253 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6};
1254 /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
1255 static const u8 cas_latency_table[] = {
1256 0, 1, 2, 3, 4, 5, 6, 7, 8, 8,
1257 9, 9, 10, 10, 11, 11};
1258
1259 if (popts->rtt_override)
1260 rtt = popts->rtt_override_value;
1261 else
1262 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1263
1264 if (additive_latency == (cas_latency - 1))
1265 al = 1;
1266 if (additive_latency == (cas_latency - 2))
1267 al = 2;
1268
1269 if (popts->quad_rank_present)
1270 dic = 1; /* output driver impedance 240/7 ohm */
1271
1272 /*
1273 * The esdmode value will also be used for writing
1274 * MR1 during write leveling for DDR3, although the
1275 * bits specifically related to the write leveling
1276 * scheme will be handled automatically by the DDR
1277 * controller. so we set the wrlvl_en = 0 here.
1278 */
1279 esdmode = (0
1280 | ((qoff & 0x1) << 12)
1281 | ((tdqs_en & 0x1) << 11)
1282 | ((rtt & 0x7) << 8)
1283 | ((wrlvl_en & 0x1) << 7)
1284 | ((al & 0x3) << 3)
1285 | ((dic & 0x3) << 1) /* DIC field is split */
1286 | ((dll_en & 0x1) << 0)
1287 );
1288
1289 /*
1290 * DLL control for precharge PD
1291 * 0=slow exit DLL off (tXPDLL)
1292 * 1=fast exit DLL on (tXP)
1293 */
1294
1295 wr_mclk = picos_to_mclk(common_dimm->twr_ps);
1296 if (wr_mclk <= 24) {
1297 wr = wr_table[wr_mclk - 10];
1298 } else {
1299 printf("Error: unsupported write recovery for mode register wr_mclk = %d\n",
1300 wr_mclk);
1301 }
1302
1303 dll_rst = 0; /* dll no reset */
1304 mode = 0; /* normal mode */
1305
1306 /* look up table to get the cas latency bits */
1307 if (cas_latency >= 9 && cas_latency <= 24)
1308 caslat = cas_latency_table[cas_latency - 9];
1309 else
1310 printf("Error: unsupported cas latency for mode register\n");
1311
1312 bt = 0; /* Nibble sequential */
1313
1314 switch (popts->burst_length) {
1315 case DDR_BL8:
1316 bl = 0;
1317 break;
1318 case DDR_OTF:
1319 bl = 1;
1320 break;
1321 case DDR_BC4:
1322 bl = 2;
1323 break;
1324 default:
1325 printf("Error: invalid burst length of %u specified. ",
1326 popts->burst_length);
1327 puts("Defaulting to on-the-fly BC4 or BL8 beats.\n");
1328 bl = 1;
1329 break;
1330 }
1331
1332 sdmode = (0
1333 | ((wr & 0x7) << 9)
1334 | ((dll_rst & 0x1) << 8)
1335 | ((mode & 0x1) << 7)
1336 | (((caslat >> 1) & 0x7) << 4)
1337 | ((bt & 0x1) << 3)
1338 | ((caslat & 1) << 2)
1339 | ((bl & 0x3) << 0)
1340 );
1341
1342 ddr->ddr_sdram_mode = (0
1343 | ((esdmode & 0xFFFF) << 16)
1344 | ((sdmode & 0xFFFF) << 0)
1345 );
1346
1347 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1348
1349 if (unq_mrs_en) { /* unique mode registers are supported */
1350 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1351 if (popts->rtt_override)
1352 rtt = popts->rtt_override_value;
1353 else
1354 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1355
1356 esdmode &= 0xF8FF; /* clear bit 10,9,8 for rtt */
1357 esdmode |= (rtt & 0x7) << 8;
1358 switch (i) {
1359 case 1:
1360 ddr->ddr_sdram_mode_3 = (0
1361 | ((esdmode & 0xFFFF) << 16)
1362 | ((sdmode & 0xFFFF) << 0)
1363 );
1364 break;
1365 case 2:
1366 ddr->ddr_sdram_mode_5 = (0
1367 | ((esdmode & 0xFFFF) << 16)
1368 | ((sdmode & 0xFFFF) << 0)
1369 );
1370 break;
1371 case 3:
1372 ddr->ddr_sdram_mode_7 = (0
1373 | ((esdmode & 0xFFFF) << 16)
1374 | ((sdmode & 0xFFFF) << 0)
1375 );
1376 break;
1377 }
1378 }
1379 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1380 ddr->ddr_sdram_mode_3);
1381 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1382 ddr->ddr_sdram_mode_5);
1383 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1384 ddr->ddr_sdram_mode_5);
1385 }
1386 }
1387
1388 #elif defined(CONFIG_SYS_FSL_DDR3)
1389 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1390 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1391 const memctl_options_t *popts,
1392 const common_timing_params_t *common_dimm,
1393 unsigned int cas_latency,
1394 unsigned int additive_latency,
1395 const unsigned int unq_mrs_en)
1396 {
1397 int i;
1398 unsigned short esdmode; /* Extended SDRAM mode */
1399 unsigned short sdmode; /* SDRAM mode */
1400
1401 /* Mode Register - MR1 */
1402 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
1403 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
1404 unsigned int rtt;
1405 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
1406 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
1407 unsigned int dic = 0; /* Output driver impedance, 40ohm */
1408 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1409 1=Disable (Test/Debug) */
1410
1411 /* Mode Register - MR0 */
1412 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
1413 unsigned int wr = 0; /* Write Recovery */
1414 unsigned int dll_rst; /* DLL Reset */
1415 unsigned int mode; /* Normal=0 or Test=1 */
1416 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1417 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1418 unsigned int bt;
1419 unsigned int bl; /* BL: Burst Length */
1420
1421 unsigned int wr_mclk;
1422 /*
1423 * DDR_SDRAM_MODE doesn't support 9,11,13,15
1424 * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
1425 * for this table
1426 */
1427 static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
1428
1429 if (popts->rtt_override)
1430 rtt = popts->rtt_override_value;
1431 else
1432 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1433
1434 if (additive_latency == (cas_latency - 1))
1435 al = 1;
1436 if (additive_latency == (cas_latency - 2))
1437 al = 2;
1438
1439 if (popts->quad_rank_present)
1440 dic = 1; /* output driver impedance 240/7 ohm */
1441
1442 /*
1443 * The esdmode value will also be used for writing
1444 * MR1 during write leveling for DDR3, although the
1445 * bits specifically related to the write leveling
1446 * scheme will be handled automatically by the DDR
1447 * controller. so we set the wrlvl_en = 0 here.
1448 */
1449 esdmode = (0
1450 | ((qoff & 0x1) << 12)
1451 | ((tdqs_en & 0x1) << 11)
1452 | ((rtt & 0x4) << 7) /* rtt field is split */
1453 | ((wrlvl_en & 0x1) << 7)
1454 | ((rtt & 0x2) << 5) /* rtt field is split */
1455 | ((dic & 0x2) << 4) /* DIC field is split */
1456 | ((al & 0x3) << 3)
1457 | ((rtt & 0x1) << 2) /* rtt field is split */
1458 | ((dic & 0x1) << 1) /* DIC field is split */
1459 | ((dll_en & 0x1) << 0)
1460 );
1461
1462 /*
1463 * DLL control for precharge PD
1464 * 0=slow exit DLL off (tXPDLL)
1465 * 1=fast exit DLL on (tXP)
1466 */
1467 dll_on = 1;
1468
1469 wr_mclk = picos_to_mclk(common_dimm->twr_ps);
1470 if (wr_mclk <= 16) {
1471 wr = wr_table[wr_mclk - 5];
1472 } else {
1473 printf("Error: unsupported write recovery for mode register "
1474 "wr_mclk = %d\n", wr_mclk);
1475 }
1476
1477 dll_rst = 0; /* dll no reset */
1478 mode = 0; /* normal mode */
1479
1480 /* look up table to get the cas latency bits */
1481 if (cas_latency >= 5 && cas_latency <= 16) {
1482 unsigned char cas_latency_table[] = {
1483 0x2, /* 5 clocks */
1484 0x4, /* 6 clocks */
1485 0x6, /* 7 clocks */
1486 0x8, /* 8 clocks */
1487 0xa, /* 9 clocks */
1488 0xc, /* 10 clocks */
1489 0xe, /* 11 clocks */
1490 0x1, /* 12 clocks */
1491 0x3, /* 13 clocks */
1492 0x5, /* 14 clocks */
1493 0x7, /* 15 clocks */
1494 0x9, /* 16 clocks */
1495 };
1496 caslat = cas_latency_table[cas_latency - 5];
1497 } else {
1498 printf("Error: unsupported cas latency for mode register\n");
1499 }
1500
1501 bt = 0; /* Nibble sequential */
1502
1503 switch (popts->burst_length) {
1504 case DDR_BL8:
1505 bl = 0;
1506 break;
1507 case DDR_OTF:
1508 bl = 1;
1509 break;
1510 case DDR_BC4:
1511 bl = 2;
1512 break;
1513 default:
1514 printf("Error: invalid burst length of %u specified. "
1515 " Defaulting to on-the-fly BC4 or BL8 beats.\n",
1516 popts->burst_length);
1517 bl = 1;
1518 break;
1519 }
1520
1521 sdmode = (0
1522 | ((dll_on & 0x1) << 12)
1523 | ((wr & 0x7) << 9)
1524 | ((dll_rst & 0x1) << 8)
1525 | ((mode & 0x1) << 7)
1526 | (((caslat >> 1) & 0x7) << 4)
1527 | ((bt & 0x1) << 3)
1528 | ((caslat & 1) << 2)
1529 | ((bl & 0x3) << 0)
1530 );
1531
1532 ddr->ddr_sdram_mode = (0
1533 | ((esdmode & 0xFFFF) << 16)
1534 | ((sdmode & 0xFFFF) << 0)
1535 );
1536
1537 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1538
1539 if (unq_mrs_en) { /* unique mode registers are supported */
1540 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1541 if (popts->rtt_override)
1542 rtt = popts->rtt_override_value;
1543 else
1544 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1545
1546 esdmode &= 0xFDBB; /* clear bit 9,6,2 */
1547 esdmode |= (0
1548 | ((rtt & 0x4) << 7) /* rtt field is split */
1549 | ((rtt & 0x2) << 5) /* rtt field is split */
1550 | ((rtt & 0x1) << 2) /* rtt field is split */
1551 );
1552 switch (i) {
1553 case 1:
1554 ddr->ddr_sdram_mode_3 = (0
1555 | ((esdmode & 0xFFFF) << 16)
1556 | ((sdmode & 0xFFFF) << 0)
1557 );
1558 break;
1559 case 2:
1560 ddr->ddr_sdram_mode_5 = (0
1561 | ((esdmode & 0xFFFF) << 16)
1562 | ((sdmode & 0xFFFF) << 0)
1563 );
1564 break;
1565 case 3:
1566 ddr->ddr_sdram_mode_7 = (0
1567 | ((esdmode & 0xFFFF) << 16)
1568 | ((sdmode & 0xFFFF) << 0)
1569 );
1570 break;
1571 }
1572 }
1573 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1574 ddr->ddr_sdram_mode_3);
1575 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1576 ddr->ddr_sdram_mode_5);
1577 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1578 ddr->ddr_sdram_mode_5);
1579 }
1580 }
1581
1582 #else /* !CONFIG_SYS_FSL_DDR3 */
1583
1584 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1585 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1586 const memctl_options_t *popts,
1587 const common_timing_params_t *common_dimm,
1588 unsigned int cas_latency,
1589 unsigned int additive_latency,
1590 const unsigned int unq_mrs_en)
1591 {
1592 unsigned short esdmode; /* Extended SDRAM mode */
1593 unsigned short sdmode; /* SDRAM mode */
1594
1595 /*
1596 * FIXME: This ought to be pre-calculated in a
1597 * technology-specific routine,
1598 * e.g. compute_DDR2_mode_register(), and then the
1599 * sdmode and esdmode passed in as part of common_dimm.
1600 */
1601
1602 /* Extended Mode Register */
1603 unsigned int mrs = 0; /* Mode Register Set */
1604 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
1605 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
1606 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
1607 unsigned int ocd = 0; /* 0x0=OCD not supported,
1608 0x7=OCD default state */
1609 unsigned int rtt;
1610 unsigned int al; /* Posted CAS# additive latency (AL) */
1611 unsigned int ods = 0; /* Output Drive Strength:
1612 0 = Full strength (18ohm)
1613 1 = Reduced strength (4ohm) */
1614 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1615 1=Disable (Test/Debug) */
1616
1617 /* Mode Register (MR) */
1618 unsigned int mr; /* Mode Register Definition */
1619 unsigned int pd; /* Power-Down Mode */
1620 unsigned int wr; /* Write Recovery */
1621 unsigned int dll_res; /* DLL Reset */
1622 unsigned int mode; /* Normal=0 or Test=1 */
1623 unsigned int caslat = 0;/* CAS# latency */
1624 /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1625 unsigned int bt;
1626 unsigned int bl; /* BL: Burst Length */
1627
1628 dqs_en = !popts->dqs_config;
1629 rtt = fsl_ddr_get_rtt();
1630
1631 al = additive_latency;
1632
1633 esdmode = (0
1634 | ((mrs & 0x3) << 14)
1635 | ((outputs & 0x1) << 12)
1636 | ((rdqs_en & 0x1) << 11)
1637 | ((dqs_en & 0x1) << 10)
1638 | ((ocd & 0x7) << 7)
1639 | ((rtt & 0x2) << 5) /* rtt field is split */
1640 | ((al & 0x7) << 3)
1641 | ((rtt & 0x1) << 2) /* rtt field is split */
1642 | ((ods & 0x1) << 1)
1643 | ((dll_en & 0x1) << 0)
1644 );
1645
1646 mr = 0; /* FIXME: CHECKME */
1647
1648 /*
1649 * 0 = Fast Exit (Normal)
1650 * 1 = Slow Exit (Low Power)
1651 */
1652 pd = 0;
1653
1654 #if defined(CONFIG_SYS_FSL_DDR1)
1655 wr = 0; /* Historical */
1656 #elif defined(CONFIG_SYS_FSL_DDR2)
1657 wr = picos_to_mclk(common_dimm->twr_ps);
1658 #endif
1659 dll_res = 0;
1660 mode = 0;
1661
1662 #if defined(CONFIG_SYS_FSL_DDR1)
1663 if (1 <= cas_latency && cas_latency <= 4) {
1664 unsigned char mode_caslat_table[4] = {
1665 0x5, /* 1.5 clocks */
1666 0x2, /* 2.0 clocks */
1667 0x6, /* 2.5 clocks */
1668 0x3 /* 3.0 clocks */
1669 };
1670 caslat = mode_caslat_table[cas_latency - 1];
1671 } else {
1672 printf("Warning: unknown cas_latency %d\n", cas_latency);
1673 }
1674 #elif defined(CONFIG_SYS_FSL_DDR2)
1675 caslat = cas_latency;
1676 #endif
1677 bt = 0;
1678
1679 switch (popts->burst_length) {
1680 case DDR_BL4:
1681 bl = 2;
1682 break;
1683 case DDR_BL8:
1684 bl = 3;
1685 break;
1686 default:
1687 printf("Error: invalid burst length of %u specified. "
1688 " Defaulting to 4 beats.\n",
1689 popts->burst_length);
1690 bl = 2;
1691 break;
1692 }
1693
1694 sdmode = (0
1695 | ((mr & 0x3) << 14)
1696 | ((pd & 0x1) << 12)
1697 | ((wr & 0x7) << 9)
1698 | ((dll_res & 0x1) << 8)
1699 | ((mode & 0x1) << 7)
1700 | ((caslat & 0x7) << 4)
1701 | ((bt & 0x1) << 3)
1702 | ((bl & 0x7) << 0)
1703 );
1704
1705 ddr->ddr_sdram_mode = (0
1706 | ((esdmode & 0xFFFF) << 16)
1707 | ((sdmode & 0xFFFF) << 0)
1708 );
1709 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1710 }
1711 #endif
1712
1713 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1714 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1715 {
1716 unsigned int init_value; /* Initialization value */
1717
1718 #ifdef CONFIG_MEM_INIT_VALUE
1719 init_value = CONFIG_MEM_INIT_VALUE;
1720 #else
1721 init_value = 0xDEADBEEF;
1722 #endif
1723 ddr->ddr_data_init = init_value;
1724 }
1725
1726 /*
1727 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1728 * The old controller on the 8540/60 doesn't have this register.
1729 * Hope it's OK to set it (to 0) anyway.
1730 */
1731 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1732 const memctl_options_t *popts)
1733 {
1734 unsigned int clk_adjust; /* Clock adjust */
1735
1736 clk_adjust = popts->clk_adjust;
1737 ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
1738 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1739 }
1740
1741 /* DDR Initialization Address (DDR_INIT_ADDR) */
1742 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1743 {
1744 unsigned int init_addr = 0; /* Initialization address */
1745
1746 ddr->ddr_init_addr = init_addr;
1747 }
1748
1749 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1750 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1751 {
1752 unsigned int uia = 0; /* Use initialization address */
1753 unsigned int init_ext_addr = 0; /* Initialization address */
1754
1755 ddr->ddr_init_ext_addr = (0
1756 | ((uia & 0x1) << 31)
1757 | (init_ext_addr & 0xF)
1758 );
1759 }
1760
1761 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1762 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1763 const memctl_options_t *popts)
1764 {
1765 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1766 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1767 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1768 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1769 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1770
1771 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1772 if (popts->burst_length == DDR_BL8) {
1773 /* We set BL/2 for fixed BL8 */
1774 rrt = 0; /* BL/2 clocks */
1775 wwt = 0; /* BL/2 clocks */
1776 } else {
1777 /* We need to set BL/2 + 2 to BC4 and OTF */
1778 rrt = 2; /* BL/2 + 2 clocks */
1779 wwt = 2; /* BL/2 + 2 clocks */
1780 }
1781 #endif
1782
1783 #ifdef CONFIG_SYS_FSL_DDR4
1784 dll_lock = 2; /* tDLLK = 1024 clocks */
1785 #elif defined(CONFIG_SYS_FSL_DDR3)
1786 dll_lock = 1; /* tDLLK = 512 clocks from spec */
1787 #endif
1788 ddr->timing_cfg_4 = (0
1789 | ((rwt & 0xf) << 28)
1790 | ((wrt & 0xf) << 24)
1791 | ((rrt & 0xf) << 20)
1792 | ((wwt & 0xf) << 16)
1793 | (dll_lock & 0x3)
1794 );
1795 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1796 }
1797
1798 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1799 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1800 {
1801 unsigned int rodt_on = 0; /* Read to ODT on */
1802 unsigned int rodt_off = 0; /* Read to ODT off */
1803 unsigned int wodt_on = 0; /* Write to ODT on */
1804 unsigned int wodt_off = 0; /* Write to ODT off */
1805
1806 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1807 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1808 ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1809 /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1810 if (cas_latency >= wr_lat)
1811 rodt_on = cas_latency - wr_lat + 1;
1812 rodt_off = 4; /* 4 clocks */
1813 wodt_on = 1; /* 1 clocks */
1814 wodt_off = 4; /* 4 clocks */
1815 #endif
1816
1817 ddr->timing_cfg_5 = (0
1818 | ((rodt_on & 0x1f) << 24)
1819 | ((rodt_off & 0x7) << 20)
1820 | ((wodt_on & 0x1f) << 12)
1821 | ((wodt_off & 0x7) << 8)
1822 );
1823 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1824 }
1825
1826 #ifdef CONFIG_SYS_FSL_DDR4
1827 static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
1828 {
1829 unsigned int hs_caslat = 0;
1830 unsigned int hs_wrlat = 0;
1831 unsigned int hs_wrrec = 0;
1832 unsigned int hs_clkadj = 0;
1833 unsigned int hs_wrlvl_start = 0;
1834
1835 ddr->timing_cfg_6 = (0
1836 | ((hs_caslat & 0x1f) << 24)
1837 | ((hs_wrlat & 0x1f) << 19)
1838 | ((hs_wrrec & 0x1f) << 12)
1839 | ((hs_clkadj & 0x1f) << 6)
1840 | ((hs_wrlvl_start & 0x1f) << 0)
1841 );
1842 debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
1843 }
1844
1845 static void set_timing_cfg_7(fsl_ddr_cfg_regs_t *ddr,
1846 const common_timing_params_t *common_dimm)
1847 {
1848 unsigned int txpr, tcksre, tcksrx;
1849 unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
1850
1851 txpr = max(5U, picos_to_mclk(common_dimm->trfc1_ps + 10000));
1852 tcksre = max(5U, picos_to_mclk(10000));
1853 tcksrx = max(5U, picos_to_mclk(10000));
1854 par_lat = 0;
1855 cs_to_cmd = 0;
1856
1857 if (txpr <= 200)
1858 cke_rst = 0;
1859 else if (txpr <= 256)
1860 cke_rst = 1;
1861 else if (txpr <= 512)
1862 cke_rst = 2;
1863 else
1864 cke_rst = 3;
1865
1866 if (tcksre <= 19)
1867 cksre = tcksre - 5;
1868 else
1869 cksre = 15;
1870
1871 if (tcksrx <= 19)
1872 cksrx = tcksrx - 5;
1873 else
1874 cksrx = 15;
1875
1876 ddr->timing_cfg_7 = (0
1877 | ((cke_rst & 0x3) << 28)
1878 | ((cksre & 0xf) << 24)
1879 | ((cksrx & 0xf) << 20)
1880 | ((par_lat & 0xf) << 16)
1881 | ((cs_to_cmd & 0xf) << 4)
1882 );
1883 debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
1884 }
1885
1886 static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr,
1887 const memctl_options_t *popts,
1888 const common_timing_params_t *common_dimm,
1889 unsigned int cas_latency)
1890 {
1891 unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
1892 unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
1893 unsigned int tccdl = picos_to_mclk(common_dimm->tccdl_ps);
1894 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1895 ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1896
1897 rwt_bg = cas_latency + 2 + 4 - wr_lat;
1898 if (rwt_bg < tccdl)
1899 rwt_bg = tccdl - rwt_bg;
1900 else
1901 rwt_bg = 0;
1902
1903 wrt_bg = wr_lat + 4 + 1 - cas_latency;
1904 if (wrt_bg < tccdl)
1905 wrt_bg = tccdl - wrt_bg;
1906 else
1907 wrt_bg = 0;
1908
1909 if (popts->burst_length == DDR_BL8) {
1910 rrt_bg = tccdl - 4;
1911 wwt_bg = tccdl - 4;
1912 } else {
1913 rrt_bg = tccdl - 2;
1914 wwt_bg = tccdl - 4;
1915 }
1916
1917 acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps);
1918 wrtord_bg = max(4U, picos_to_mclk(7500));
1919 if (popts->otf_burst_chop_en)
1920 wrtord_bg += 2;
1921
1922 pre_all_rec = 0;
1923
1924 ddr->timing_cfg_8 = (0
1925 | ((rwt_bg & 0xf) << 28)
1926 | ((wrt_bg & 0xf) << 24)
1927 | ((rrt_bg & 0xf) << 20)
1928 | ((wwt_bg & 0xf) << 16)
1929 | ((acttoact_bg & 0xf) << 12)
1930 | ((wrtord_bg & 0xf) << 8)
1931 | ((pre_all_rec & 0x1f) << 0)
1932 );
1933
1934 debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8);
1935 }
1936
1937 static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr)
1938 {
1939 ddr->timing_cfg_9 = 0;
1940 debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
1941 }
1942
1943 /* This function needs to be called after set_ddr_sdram_cfg() is called */
1944 static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
1945 const dimm_params_t *dimm_params)
1946 {
1947 unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1;
1948
1949 ddr->dq_map_0 = ((dimm_params->dq_mapping[0] & 0x3F) << 26) |
1950 ((dimm_params->dq_mapping[1] & 0x3F) << 20) |
1951 ((dimm_params->dq_mapping[2] & 0x3F) << 14) |
1952 ((dimm_params->dq_mapping[3] & 0x3F) << 8) |
1953 ((dimm_params->dq_mapping[4] & 0x3F) << 2);
1954
1955 ddr->dq_map_1 = ((dimm_params->dq_mapping[5] & 0x3F) << 26) |
1956 ((dimm_params->dq_mapping[6] & 0x3F) << 20) |
1957 ((dimm_params->dq_mapping[7] & 0x3F) << 14) |
1958 ((dimm_params->dq_mapping[10] & 0x3F) << 8) |
1959 ((dimm_params->dq_mapping[11] & 0x3F) << 2);
1960
1961 ddr->dq_map_2 = ((dimm_params->dq_mapping[12] & 0x3F) << 26) |
1962 ((dimm_params->dq_mapping[13] & 0x3F) << 20) |
1963 ((dimm_params->dq_mapping[14] & 0x3F) << 14) |
1964 ((dimm_params->dq_mapping[15] & 0x3F) << 8) |
1965 ((dimm_params->dq_mapping[16] & 0x3F) << 2);
1966
1967 /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */
1968 ddr->dq_map_3 = ((dimm_params->dq_mapping[17] & 0x3F) << 26) |
1969 ((dimm_params->dq_mapping[8] & 0x3F) << 20) |
1970 (acc_ecc_en ? 0 :
1971 (dimm_params->dq_mapping[9] & 0x3F) << 14) |
1972 dimm_params->dq_mapping_ors;
1973
1974 debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
1975 debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1);
1976 debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2);
1977 debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3);
1978 }
1979 static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr,
1980 const memctl_options_t *popts)
1981 {
1982 int rd_pre;
1983
1984 rd_pre = popts->quad_rank_present ? 1 : 0;
1985
1986 ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16;
1987
1988 debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3);
1989 }
1990 #endif /* CONFIG_SYS_FSL_DDR4 */
1991
1992 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
1993 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
1994 {
1995 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1996 /* Normal Operation Full Calibration Time (tZQoper) */
1997 unsigned int zqoper = 0;
1998 /* Normal Operation Short Calibration Time (tZQCS) */
1999 unsigned int zqcs = 0;
2000 #ifdef CONFIG_SYS_FSL_DDR4
2001 unsigned int zqcs_init;
2002 #endif
2003
2004 if (zq_en) {
2005 #ifdef CONFIG_SYS_FSL_DDR4
2006 zqinit = 10; /* 1024 clocks */
2007 zqoper = 9; /* 512 clocks */
2008 zqcs = 7; /* 128 clocks */
2009 zqcs_init = 5; /* 1024 refresh sequences */
2010 #else
2011 zqinit = 9; /* 512 clocks */
2012 zqoper = 8; /* 256 clocks */
2013 zqcs = 6; /* 64 clocks */
2014 #endif
2015 }
2016
2017 ddr->ddr_zq_cntl = (0
2018 | ((zq_en & 0x1) << 31)
2019 | ((zqinit & 0xF) << 24)
2020 | ((zqoper & 0xF) << 16)
2021 | ((zqcs & 0xF) << 8)
2022 #ifdef CONFIG_SYS_FSL_DDR4
2023 | ((zqcs_init & 0xF) << 0)
2024 #endif
2025 );
2026 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
2027 }
2028
2029 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
2030 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
2031 const memctl_options_t *popts)
2032 {
2033 /*
2034 * First DQS pulse rising edge after margining mode
2035 * is programmed (tWL_MRD)
2036 */
2037 unsigned int wrlvl_mrd = 0;
2038 /* ODT delay after margining mode is programmed (tWL_ODTEN) */
2039 unsigned int wrlvl_odten = 0;
2040 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
2041 unsigned int wrlvl_dqsen = 0;
2042 /* WRLVL_SMPL: Write leveling sample time */
2043 unsigned int wrlvl_smpl = 0;
2044 /* WRLVL_WLR: Write leveling repeition time */
2045 unsigned int wrlvl_wlr = 0;
2046 /* WRLVL_START: Write leveling start time */
2047 unsigned int wrlvl_start = 0;
2048
2049 /* suggest enable write leveling for DDR3 due to fly-by topology */
2050 if (wrlvl_en) {
2051 /* tWL_MRD min = 40 nCK, we set it 64 */
2052 wrlvl_mrd = 0x6;
2053 /* tWL_ODTEN 128 */
2054 wrlvl_odten = 0x7;
2055 /* tWL_DQSEN min = 25 nCK, we set it 32 */
2056 wrlvl_dqsen = 0x5;
2057 /*
2058 * Write leveling sample time at least need 6 clocks
2059 * higher than tWLO to allow enough time for progagation
2060 * delay and sampling the prime data bits.
2061 */
2062 wrlvl_smpl = 0xf;
2063 /*
2064 * Write leveling repetition time
2065 * at least tWLO + 6 clocks clocks
2066 * we set it 64
2067 */
2068 wrlvl_wlr = 0x6;
2069 /*
2070 * Write leveling start time
2071 * The value use for the DQS_ADJUST for the first sample
2072 * when write leveling is enabled. It probably needs to be
2073 * overriden per platform.
2074 */
2075 wrlvl_start = 0x8;
2076 /*
2077 * Override the write leveling sample and start time
2078 * according to specific board
2079 */
2080 if (popts->wrlvl_override) {
2081 wrlvl_smpl = popts->wrlvl_sample;
2082 wrlvl_start = popts->wrlvl_start;
2083 }
2084 }
2085
2086 ddr->ddr_wrlvl_cntl = (0
2087 | ((wrlvl_en & 0x1) << 31)
2088 | ((wrlvl_mrd & 0x7) << 24)
2089 | ((wrlvl_odten & 0x7) << 20)
2090 | ((wrlvl_dqsen & 0x7) << 16)
2091 | ((wrlvl_smpl & 0xf) << 12)
2092 | ((wrlvl_wlr & 0x7) << 8)
2093 | ((wrlvl_start & 0x1F) << 0)
2094 );
2095 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
2096 ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
2097 debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
2098 ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
2099 debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
2100
2101 }
2102
2103 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
2104 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
2105 {
2106 /* Self Refresh Idle Threshold */
2107 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
2108 }
2109
2110 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2111 {
2112 if (popts->addr_hash) {
2113 ddr->ddr_eor = 0x40000000; /* address hash enable */
2114 puts("Address hashing enabled.\n");
2115 }
2116 }
2117
2118 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2119 {
2120 ddr->ddr_cdr1 = popts->ddr_cdr1;
2121 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
2122 }
2123
2124 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2125 {
2126 ddr->ddr_cdr2 = popts->ddr_cdr2;
2127 debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
2128 }
2129
2130 unsigned int
2131 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
2132 {
2133 unsigned int res = 0;
2134
2135 /*
2136 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
2137 * not set at the same time.
2138 */
2139 if (ddr->ddr_sdram_cfg & 0x10000000
2140 && ddr->ddr_sdram_cfg & 0x00008000) {
2141 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
2142 " should not be set at the same time.\n");
2143 res++;
2144 }
2145
2146 return res;
2147 }
2148
2149 unsigned int
2150 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
2151 fsl_ddr_cfg_regs_t *ddr,
2152 const common_timing_params_t *common_dimm,
2153 const dimm_params_t *dimm_params,
2154 unsigned int dbw_cap_adj,
2155 unsigned int size_only)
2156 {
2157 unsigned int i;
2158 unsigned int cas_latency;
2159 unsigned int additive_latency;
2160 unsigned int sr_it;
2161 unsigned int zq_en;
2162 unsigned int wrlvl_en;
2163 unsigned int ip_rev = 0;
2164 unsigned int unq_mrs_en = 0;
2165 int cs_en = 1;
2166
2167 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
2168
2169 if (common_dimm == NULL) {
2170 printf("Error: subset DIMM params struct null pointer\n");
2171 return 1;
2172 }
2173
2174 /*
2175 * Process overrides first.
2176 *
2177 * FIXME: somehow add dereated caslat to this
2178 */
2179 cas_latency = (popts->cas_latency_override)
2180 ? popts->cas_latency_override_value
2181 : common_dimm->lowest_common_spd_caslat;
2182
2183 additive_latency = (popts->additive_latency_override)
2184 ? popts->additive_latency_override_value
2185 : common_dimm->additive_latency;
2186
2187 sr_it = (popts->auto_self_refresh_en)
2188 ? popts->sr_it
2189 : 0;
2190 /* ZQ calibration */
2191 zq_en = (popts->zq_en) ? 1 : 0;
2192 /* write leveling */
2193 wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
2194
2195 /* Chip Select Memory Bounds (CSn_BNDS) */
2196 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
2197 unsigned long long ea, sa;
2198 unsigned int cs_per_dimm
2199 = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
2200 unsigned int dimm_number
2201 = i / cs_per_dimm;
2202 unsigned long long rank_density
2203 = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
2204
2205 if (dimm_params[dimm_number].n_ranks == 0) {
2206 debug("Skipping setup of CS%u "
2207 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
2208 continue;
2209 }
2210 if (popts->memctl_interleaving) {
2211 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2212 case FSL_DDR_CS0_CS1_CS2_CS3:
2213 break;
2214 case FSL_DDR_CS0_CS1:
2215 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2216 if (i > 1)
2217 cs_en = 0;
2218 break;
2219 case FSL_DDR_CS2_CS3:
2220 default:
2221 if (i > 0)
2222 cs_en = 0;
2223 break;
2224 }
2225 sa = common_dimm->base_address;
2226 ea = sa + common_dimm->total_mem - 1;
2227 } else if (!popts->memctl_interleaving) {
2228 /*
2229 * If memory interleaving between controllers is NOT
2230 * enabled, the starting address for each memory
2231 * controller is distinct. However, because rank
2232 * interleaving is enabled, the starting and ending
2233 * addresses of the total memory on that memory
2234 * controller needs to be programmed into its
2235 * respective CS0_BNDS.
2236 */
2237 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2238 case FSL_DDR_CS0_CS1_CS2_CS3:
2239 sa = common_dimm->base_address;
2240 ea = sa + common_dimm->total_mem - 1;
2241 break;
2242 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2243 if ((i >= 2) && (dimm_number == 0)) {
2244 sa = dimm_params[dimm_number].base_address +
2245 2 * rank_density;
2246 ea = sa + 2 * rank_density - 1;
2247 } else {
2248 sa = dimm_params[dimm_number].base_address;
2249 ea = sa + 2 * rank_density - 1;
2250 }
2251 break;
2252 case FSL_DDR_CS0_CS1:
2253 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2254 sa = dimm_params[dimm_number].base_address;
2255 ea = sa + rank_density - 1;
2256 if (i != 1)
2257 sa += (i % cs_per_dimm) * rank_density;
2258 ea += (i % cs_per_dimm) * rank_density;
2259 } else {
2260 sa = 0;
2261 ea = 0;
2262 }
2263 if (i == 0)
2264 ea += rank_density;
2265 break;
2266 case FSL_DDR_CS2_CS3:
2267 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2268 sa = dimm_params[dimm_number].base_address;
2269 ea = sa + rank_density - 1;
2270 if (i != 3)
2271 sa += (i % cs_per_dimm) * rank_density;
2272 ea += (i % cs_per_dimm) * rank_density;
2273 } else {
2274 sa = 0;
2275 ea = 0;
2276 }
2277 if (i == 2)
2278 ea += (rank_density >> dbw_cap_adj);
2279 break;
2280 default: /* No bank(chip-select) interleaving */
2281 sa = dimm_params[dimm_number].base_address;
2282 ea = sa + rank_density - 1;
2283 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2284 sa += (i % cs_per_dimm) * rank_density;
2285 ea += (i % cs_per_dimm) * rank_density;
2286 } else {
2287 sa = 0;
2288 ea = 0;
2289 }
2290 break;
2291 }
2292 }
2293
2294 sa >>= 24;
2295 ea >>= 24;
2296
2297 if (cs_en) {
2298 ddr->cs[i].bnds = (0
2299 | ((sa & 0xffff) << 16) /* starting address */
2300 | ((ea & 0xffff) << 0) /* ending address */
2301 );
2302 } else {
2303 /* setting bnds to 0xffffffff for inactive CS */
2304 ddr->cs[i].bnds = 0xffffffff;
2305 }
2306
2307 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
2308 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
2309 set_csn_config_2(i, ddr);
2310 }
2311
2312 /*
2313 * In the case we only need to compute the ddr sdram size, we only need
2314 * to set csn registers, so return from here.
2315 */
2316 if (size_only)
2317 return 0;
2318
2319 set_ddr_eor(ddr, popts);
2320
2321 #if !defined(CONFIG_SYS_FSL_DDR1)
2322 set_timing_cfg_0(ddr, popts, dimm_params);
2323 #endif
2324
2325 set_timing_cfg_3(ddr, popts, common_dimm, cas_latency,
2326 additive_latency);
2327 set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
2328 set_timing_cfg_2(ddr, popts, common_dimm,
2329 cas_latency, additive_latency);
2330
2331 set_ddr_cdr1(ddr, popts);
2332 set_ddr_cdr2(ddr, popts);
2333 set_ddr_sdram_cfg(ddr, popts, common_dimm);
2334 ip_rev = fsl_ddr_get_version();
2335 if (ip_rev > 0x40400)
2336 unq_mrs_en = 1;
2337
2338 if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
2339 ddr->debug[18] = popts->cswl_override;
2340
2341 set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
2342 set_ddr_sdram_mode(ddr, popts, common_dimm,
2343 cas_latency, additive_latency, unq_mrs_en);
2344 set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en);
2345 #ifdef CONFIG_SYS_FSL_DDR4
2346 set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
2347 set_ddr_sdram_mode_10(ddr, popts, common_dimm, unq_mrs_en);
2348 #endif
2349 set_ddr_sdram_interval(ddr, popts, common_dimm);
2350 set_ddr_data_init(ddr);
2351 set_ddr_sdram_clk_cntl(ddr, popts);
2352 set_ddr_init_addr(ddr);
2353 set_ddr_init_ext_addr(ddr);
2354 set_timing_cfg_4(ddr, popts);
2355 set_timing_cfg_5(ddr, cas_latency);
2356 #ifdef CONFIG_SYS_FSL_DDR4
2357 set_ddr_sdram_cfg_3(ddr, popts);
2358 set_timing_cfg_6(ddr);
2359 set_timing_cfg_7(ddr, common_dimm);
2360 set_timing_cfg_8(ddr, popts, common_dimm, cas_latency);
2361 set_timing_cfg_9(ddr);
2362 set_ddr_dq_mapping(ddr, dimm_params);
2363 #endif
2364
2365 set_ddr_zq_cntl(ddr, zq_en);
2366 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
2367
2368 set_ddr_sr_cntr(ddr, sr_it);
2369
2370 set_ddr_sdram_rcw(ddr, popts, common_dimm);
2371
2372 #ifdef CONFIG_SYS_FSL_DDR_EMU
2373 /* disble DDR training for emulator */
2374 ddr->debug[2] = 0x00000400;
2375 ddr->debug[4] = 0xff800000;
2376 #endif
2377 #ifdef CONFIG_SYS_FSL_ERRATUM_A004508
2378 if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
2379 ddr->debug[2] |= 0x00000200; /* set bit 22 */
2380 #endif
2381
2382 return check_fsl_memctl_config_regs(ddr);
2383 }
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