drivers/ddr/fsl/ddr3_dimm_params.c

   1 /*
   2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   3  *      Dave Liu <daveliu@freescale.com>
   4  *
   5  * calculate the organization and timing parameter
   6  * from ddr3 spd, please refer to the spec
   7  * JEDEC standard No.21-C 4_01_02_11R18.pdf
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0
  10  */
  11
  12 #include <common.h>
  13 #include <fsl_ddr_sdram.h>
  14
  15 #include <fsl_ddr.h>
  16
  17 /*
  18  * Calculate the Density of each Physical Rank.
  19  * Returned size is in bytes.
  20  *
  21  * each rank size =
  22  * sdram capacity(bit) / 8 * primary bus width / sdram width
  23  *
  24  * where: sdram capacity  = spd byte4[3:0]
  25  *        primary bus width = spd byte8[2:0]
  26  *        sdram width = spd byte7[2:0]
  27  *
  28  * SPD byte4 - sdram density and banks
  29  *      bit[3:0]        size(bit)       size(byte)
  30  *      0000            256Mb           32MB
  31  *      0001            512Mb           64MB
  32  *      0010            1Gb             128MB
  33  *      0011            2Gb             256MB
  34  *      0100            4Gb             512MB
  35  *      0101            8Gb             1GB
  36  *      0110            16Gb            2GB
  37  *
  38  * SPD byte8 - module memory bus width
  39  *      bit[2:0]        primary bus width
  40  *      000             8bits
  41  *      001             16bits
  42  *      010             32bits
  43  *      011             64bits
  44  *
  45  * SPD byte7 - module organiztion
  46  *      bit[2:0]        sdram device width
  47  *      000             4bits
  48  *      001             8bits
  49  *      010             16bits
  50  *      011             32bits
  51  *
  52  */
  53 static unsigned long long
  54 compute_ranksize(const ddr3_spd_eeprom_t *spd)
  55 {
  56         unsigned long long bsize;
  57
  58         int nbit_sdram_cap_bsize = 0;
  59         int nbit_primary_bus_width = 0;
  60         int nbit_sdram_width = 0;
  61
  62         if ((spd->density_banks & 0xf) < 7)
  63                 nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
  64         if ((spd->bus_width & 0x7) < 4)
  65                 nbit_primary_bus_width = (spd->bus_width & 0x7) + 3;
  66         if ((spd->organization & 0x7) < 4)
  67                 nbit_sdram_width = (spd->organization & 0x7) + 2;
  68
  69         bsize = 1ULL << (nbit_sdram_cap_bsize - 3
  70                     + nbit_primary_bus_width - nbit_sdram_width);
  71
  72         debug("DDR: DDR III rank density = 0x%16llx\n", bsize);
  73
  74         return bsize;
  75 }
  76
  77 /*
  78  * ddr_compute_dimm_parameters for DDR3 SPD
  79  *
  80  * Compute DIMM parameters based upon the SPD information in spd.
  81  * Writes the results to the dimm_params_t structure pointed by pdimm.
  82  *
  83  */
  84 unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
  85                                          const ddr3_spd_eeprom_t *spd,
  86                                          dimm_params_t *pdimm,
  87                                          unsigned int dimm_number)
  88 {
  89         unsigned int retval;
  90         unsigned int mtb_ps;
  91         int ftb_10th_ps;
  92         int i;
  93
  94         if (spd->mem_type) {
  95                 if (spd->mem_type != SPD_MEMTYPE_DDR3) {
  96                         printf("DIMM %u: is not a DDR3 SPD.\n", dimm_number);
  97                         return 1;
  98                 }
  99         } else {
 100                 memset(pdimm, 0, sizeof(dimm_params_t));
 101                 return 1;
 102         }
 103
 104         retval = ddr3_spd_check(spd);
 105         if (retval) {
 106                 printf("DIMM %u: failed checksum\n", dimm_number);
 107                 return 2;
 108         }
 109
 110         /*
 111          * The part name in ASCII in the SPD EEPROM is not null terminated.
 112          * Guarantee null termination here by presetting all bytes to 0
 113          * and copying the part name in ASCII from the SPD onto it
 114          */
 115         memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
 116         if ((spd->info_size_crc & 0xF) > 1)
 117                 memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
 118
 119         /* DIMM organization parameters */
 120         pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
 121         pdimm->rank_density = compute_ranksize(spd);
 122         pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
 123         pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
 124         if ((spd->bus_width >> 3) & 0x3)
 125                 pdimm->ec_sdram_width = 8;
 126         else
 127                 pdimm->ec_sdram_width = 0;
 128         pdimm->data_width = pdimm->primary_sdram_width
 129                           + pdimm->ec_sdram_width;
 130         pdimm->device_width = 1 << ((spd->organization & 0x7) + 2);
 131
 132         /* These are the types defined by the JEDEC DDR3 SPD spec */
 133         pdimm->mirrored_dimm = 0;
 134         pdimm->registered_dimm = 0;
 135         switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) {
 136         case DDR3_SPD_MODULETYPE_RDIMM:
 137         case DDR3_SPD_MODULETYPE_MINI_RDIMM:
 138         case DDR3_SPD_MODULETYPE_72B_SO_RDIMM:
 139                 /* Registered/buffered DIMMs */
 140                 pdimm->registered_dimm = 1;
 141                 for (i = 0; i < 16; i += 2) {
 142                         u8 rcw = spd->mod_section.registered.rcw[i/2];
 143                         pdimm->rcw[i]   = (rcw >> 0) & 0x0F;
 144                         pdimm->rcw[i+1] = (rcw >> 4) & 0x0F;
 145                 }
 146                 break;
 147
 148         case DDR3_SPD_MODULETYPE_UDIMM:
 149         case DDR3_SPD_MODULETYPE_SO_DIMM:
 150         case DDR3_SPD_MODULETYPE_MICRO_DIMM:
 151         case DDR3_SPD_MODULETYPE_MINI_UDIMM:
 152         case DDR3_SPD_MODULETYPE_MINI_CDIMM:
 153         case DDR3_SPD_MODULETYPE_72B_SO_UDIMM:
 154         case DDR3_SPD_MODULETYPE_72B_SO_CDIMM:
 155         case DDR3_SPD_MODULETYPE_LRDIMM:
 156         case DDR3_SPD_MODULETYPE_16B_SO_DIMM:
 157         case DDR3_SPD_MODULETYPE_32B_SO_DIMM:
 158                 /* Unbuffered DIMMs */
 159                 if (spd->mod_section.unbuffered.addr_mapping & 0x1)
 160                         pdimm->mirrored_dimm = 1;
 161                 break;
 162
 163         default:
 164                 printf("unknown module_type 0x%02X\n", spd->module_type);
 165                 return 1;
 166         }
 167
 168         /* SDRAM device parameters */
 169         pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
 170         pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
 171         pdimm->n_banks_per_sdram_device = 8 << ((spd->density_banks >> 4) & 0x7);
 172
 173         /*
 174          * The SPD spec has not the ECC bit,
 175          * We consider the DIMM as ECC capability
 176          * when the extension bus exist
 177          */
 178         if (pdimm->ec_sdram_width)
 179                 pdimm->edc_config = 0x02;
 180         else
 181                 pdimm->edc_config = 0x00;
 182
 183         /*
 184          * The SPD spec has not the burst length byte
 185          * but DDR3 spec has nature BL8 and BC4,
 186          * BL8 -bit3, BC4 -bit2
 187          */
 188         pdimm->burst_lengths_bitmask = 0x0c;
 189         pdimm->row_density = __ilog2(pdimm->rank_density);
 190
 191         /* MTB - medium timebase
 192          * The unit in the SPD spec is ns,
 193          * We convert it to ps.
 194          * eg: MTB = 0.125ns (125ps)
 195          */
 196         mtb_ps = (spd->mtb_dividend * 1000) /spd->mtb_divisor;
 197         pdimm->mtb_ps = mtb_ps;
 198
 199         /*
 200          * FTB - fine timebase
 201          * use 1/10th of ps as our unit to avoid floating point
 202          * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps
 203          */
 204         ftb_10th_ps =
 205                 ((spd->ftb_div & 0xf0) >> 4) * 10 / (spd->ftb_div & 0x0f);
 206         pdimm->ftb_10th_ps = ftb_10th_ps;
 207         /*
 208          * sdram minimum cycle time
 209          * we assume the MTB is 0.125ns
 210          * eg:
 211          * tck_min=15 MTB (1.875ns) ->DDR3-1066
 212          *        =12 MTB (1.5ns) ->DDR3-1333
 213          *        =10 MTB (1.25ns) ->DDR3-1600
 214          */
 215         pdimm->tckmin_x_ps = spd->tck_min * mtb_ps +
 216                 (spd->fine_tck_min * ftb_10th_ps) / 10;
 217
 218         /*
 219          * CAS latency supported
 220          * bit4 - CL4
 221          * bit5 - CL5
 222          * bit18 - CL18
 223          */
 224         pdimm->caslat_x  = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4;
 225
 226         /*
 227          * min CAS latency time
 228          * eg: taa_min =
 229          * DDR3-800D    100 MTB (12.5ns)
 230          * DDR3-1066F   105 MTB (13.125ns)
 231          * DDR3-1333H   108 MTB (13.5ns)
 232          * DDR3-1600H   90 MTB (11.25ns)
 233          */
 234         pdimm->taa_ps = spd->taa_min * mtb_ps +
 235                 (spd->fine_taa_min * ftb_10th_ps) / 10;
 236
 237         /*
 238          * min write recovery time
 239          * eg:
 240          * twr_min = 120 MTB (15ns) -> all speed grades.
 241          */
 242         pdimm->twr_ps = spd->twr_min * mtb_ps;
 243
 244         /*
 245          * min RAS to CAS delay time
 246          * eg: trcd_min =
 247          * DDR3-800     100 MTB (12.5ns)
 248          * DDR3-1066F   105 MTB (13.125ns)
 249          * DDR3-1333H   108 MTB (13.5ns)
 250          * DDR3-1600H   90 MTB (11.25)
 251          */
 252         pdimm->trcd_ps = spd->trcd_min * mtb_ps +
 253                 (spd->fine_trcd_min * ftb_10th_ps) / 10;
 254
 255         /*
 256          * min row active to row active delay time
 257          * eg: trrd_min =
 258          * DDR3-800(1KB page)   80 MTB (10ns)
 259          * DDR3-1333(1KB page)  48 MTB (6ns)
 260          */
 261         pdimm->trrd_ps = spd->trrd_min * mtb_ps;
 262
 263         /*
 264          * min row precharge delay time
 265          * eg: trp_min =
 266          * DDR3-800D    100 MTB (12.5ns)
 267          * DDR3-1066F   105 MTB (13.125ns)
 268          * DDR3-1333H   108 MTB (13.5ns)
 269          * DDR3-1600H   90 MTB (11.25ns)
 270          */
 271         pdimm->trp_ps = spd->trp_min * mtb_ps +
 272                 (spd->fine_trp_min * ftb_10th_ps) / 10;
 273
 274         /* min active to precharge delay time
 275          * eg: tRAS_min =
 276          * DDR3-800D    300 MTB (37.5ns)
 277          * DDR3-1066F   300 MTB (37.5ns)
 278          * DDR3-1333H   288 MTB (36ns)
 279          * DDR3-1600H   280 MTB (35ns)
 280          */
 281         pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) | spd->tras_min_lsb)
 282                         * mtb_ps;
 283         /*
 284          * min active to actice/refresh delay time
 285          * eg: tRC_min =
 286          * DDR3-800D    400 MTB (50ns)
 287          * DDR3-1066F   405 MTB (50.625ns)
 288          * DDR3-1333H   396 MTB (49.5ns)
 289          * DDR3-1600H   370 MTB (46.25ns)
 290          */
 291         pdimm->trc_ps = (((spd->tras_trc_ext & 0xf0) << 4) | spd->trc_min_lsb)
 292                         * mtb_ps + (spd->fine_trc_min * ftb_10th_ps) / 10;
 293         /*
 294          * min refresh recovery delay time
 295          * eg: tRFC_min =
 296          * 512Mb        720 MTB (90ns)
 297          * 1Gb          880 MTB (110ns)
 298          * 2Gb          1280 MTB (160ns)
 299          */
 300         pdimm->trfc_ps = ((spd->trfc_min_msb << 8) | spd->trfc_min_lsb)
 301                         * mtb_ps;
 302         /*
 303          * min internal write to read command delay time
 304          * eg: twtr_min = 40 MTB (7.5ns) - all speed bins.
 305          * tWRT is at least 4 mclk independent of operating freq.
 306          */
 307         pdimm->twtr_ps = spd->twtr_min * mtb_ps;
 308
 309         /*
 310          * min internal read to precharge command delay time
 311          * eg: trtp_min = 40 MTB (7.5ns) - all speed bins.
 312          * tRTP is at least 4 mclk independent of operating freq.
 313          */
 314         pdimm->trtp_ps = spd->trtp_min * mtb_ps;
 315
 316         /*
 317          * Average periodic refresh interval
 318          * tREFI = 7.8 us at normal temperature range
 319          *       = 3.9 us at ext temperature range
 320          */
 321         pdimm->refresh_rate_ps = 7800000;
 322         if ((spd->therm_ref_opt & 0x1) && !(spd->therm_ref_opt & 0x2)) {
 323                 pdimm->refresh_rate_ps = 3900000;
 324                 pdimm->extended_op_srt = 1;
 325         }
 326
 327         /*
 328          * min four active window delay time
 329          * eg: tfaw_min =
 330          * DDR3-800(1KB page)   320 MTB (40ns)
 331          * DDR3-1066(1KB page)  300 MTB (37.5ns)
 332          * DDR3-1333(1KB page)  240 MTB (30ns)
 333          * DDR3-1600(1KB page)  240 MTB (30ns)
 334          */
 335         pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min)
 336                         * mtb_ps;
 337
 338         return 0;
 339 }