drivers/ddr/fsl/ddr4_dimm_params.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * calculate the organization and timing parameter
   5  * from ddr3 spd, please refer to the spec
   6  * JEDEC standard No.21-C 4_01_02_12R23A.pdf
   7  *
   8  *
   9  */
  10
  11 #include <common.h>
  12 #include <fsl_ddr_sdram.h>
  13
  14 #include <fsl_ddr.h>
  15
  16 /*
  17  * Calculate the Density of each Physical Rank.
  18  * Returned size is in bytes.
  19  *
  20  * Total DIMM size =
  21  * sdram capacity(bit) / 8 * primary bus width / sdram width
  22  *                     * Logical Ranks per DIMM
  23  *
  24  * where: sdram capacity  = spd byte4[3:0]
  25  *        primary bus width = spd byte13[2:0]
  26  *        sdram width = spd byte12[2:0]
  27  *        Logical Ranks per DIMM = spd byte12[5:3] for SDP, DDP, QDP
  28  *                                 spd byte12{5:3] * spd byte6[6:4] for 3DS
  29  *
  30  * To simplify each rank size = total DIMM size / Number of Package Ranks
  31  * where Number of Package Ranks = spd byte12[5:3]
  32  *
  33  * SPD byte4 - sdram density and banks
  34  *      bit[3:0]        size(bit)       size(byte)
  35  *      0000            256Mb           32MB
  36  *      0001            512Mb           64MB
  37  *      0010            1Gb             128MB
  38  *      0011            2Gb             256MB
  39  *      0100            4Gb             512MB
  40  *      0101            8Gb             1GB
  41  *      0110            16Gb            2GB
  42  *      0111            32Gb            4GB
  43  *
  44  * SPD byte13 - module memory bus width
  45  *      bit[2:0]        primary bus width
  46  *      000             8bits
  47  *      001             16bits
  48  *      010             32bits
  49  *      011             64bits
  50  *
  51  * SPD byte12 - module organization
  52  *      bit[2:0]        sdram device width
  53  *      000             4bits
  54  *      001             8bits
  55  *      010             16bits
  56  *      011             32bits
  57  *
  58  * SPD byte12 - module organization
  59  *      bit[5:3]        number of package ranks per DIMM
  60  *      000             1
  61  *      001             2
  62  *      010             3
  63  *      011             4
  64  *
  65  * SPD byte6 - SDRAM package type
  66  *      bit[6:4]        Die count
  67  *      000             1
  68  *      001             2
  69  *      010             3
  70  *      011             4
  71  *      100             5
  72  *      101             6
  73  *      110             7
  74  *      111             8
  75  *
  76  * SPD byte6 - SRAM package type
  77  *      bit[1:0]        Signal loading
  78  *      00              Not specified
  79  *      01              Multi load stack
  80  *      10              Sigle load stack (3DS)
  81  *      11              Reserved
  82  */
  83 static unsigned long long
  84 compute_ranksize(const struct ddr4_spd_eeprom_s *spd)
  85 {
  86         unsigned long long bsize;
  87
  88         int nbit_sdram_cap_bsize = 0;
  89         int nbit_primary_bus_width = 0;
  90         int nbit_sdram_width = 0;
  91         int die_count = 0;
  92         bool package_3ds;
  93
  94         if ((spd->density_banks & 0xf) <= 7)
  95                 nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
  96         if ((spd->bus_width & 0x7) < 4)
  97                 nbit_primary_bus_width = (spd->bus_width & 0x7) + 3;
  98         if ((spd->organization & 0x7) < 4)
  99                 nbit_sdram_width = (spd->organization & 0x7) + 2;
 100         package_3ds = (spd->package_type & 0x3) == 0x2;
 101         if (package_3ds)
 102                 die_count = (spd->package_type >> 4) & 0x7;
 103
 104         bsize = 1ULL << (nbit_sdram_cap_bsize - 3 +
 105                          nbit_primary_bus_width - nbit_sdram_width +
 106                          die_count);
 107
 108         debug("DDR: DDR III rank density = 0x%16llx\n", bsize);
 109
 110         return bsize;
 111 }
 112
 113 #define spd_to_ps(mtb, ftb)     \
 114         (mtb * pdimm->mtb_ps + (ftb * pdimm->ftb_10th_ps) / 10)
 115 /*
 116  * ddr_compute_dimm_parameters for DDR4 SPD
 117  *
 118  * Compute DIMM parameters based upon the SPD information in spd.
 119  * Writes the results to the dimm_params_t structure pointed by pdimm.
 120  *
 121  */
 122 unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
 123                                          const generic_spd_eeprom_t *spd,
 124                                          dimm_params_t *pdimm,
 125                                          unsigned int dimm_number)
 126 {
 127         unsigned int retval;
 128         int i;
 129         const u8 udimm_rc_e_dq[18] = {
 130                 0x0c, 0x2c, 0x15, 0x35, 0x15, 0x35, 0x0b, 0x2c, 0x15,
 131                 0x35, 0x0b, 0x35, 0x0b, 0x2c, 0x0b, 0x35, 0x15, 0x36
 132         };
 133         int spd_error = 0;
 134         u8 *ptr;
 135
 136         if (spd->mem_type) {
 137                 if (spd->mem_type != SPD_MEMTYPE_DDR4) {
 138                         printf("Ctrl %u DIMM %u: is not a DDR4 SPD.\n",
 139                                ctrl_num, dimm_number);
 140                         return 1;
 141                 }
 142         } else {
 143                 memset(pdimm, 0, sizeof(dimm_params_t));
 144                 return 1;
 145         }
 146
 147         retval = ddr4_spd_check(spd);
 148         if (retval) {
 149                 printf("DIMM %u: failed checksum\n", dimm_number);
 150                 return 2;
 151         }
 152
 153         /*
 154          * The part name in ASCII in the SPD EEPROM is not null terminated.
 155          * Guarantee null termination here by presetting all bytes to 0
 156          * and copying the part name in ASCII from the SPD onto it
 157          */
 158         memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
 159         if ((spd->info_size_crc & 0xF) > 2)
 160                 memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
 161
 162         /* DIMM organization parameters */
 163         pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
 164         pdimm->rank_density = compute_ranksize(spd);
 165         pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
 166         pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
 167         if ((spd->bus_width >> 3) & 0x3)
 168                 pdimm->ec_sdram_width = 8;
 169         else
 170                 pdimm->ec_sdram_width = 0;
 171         pdimm->data_width = pdimm->primary_sdram_width
 172                           + pdimm->ec_sdram_width;
 173         pdimm->device_width = 1 << ((spd->organization & 0x7) + 2);
 174
 175         /* These are the types defined by the JEDEC SPD spec */
 176         pdimm->mirrored_dimm = 0;
 177         pdimm->registered_dimm = 0;
 178         switch (spd->module_type & DDR4_SPD_MODULETYPE_MASK) {
 179         case DDR4_SPD_MODULETYPE_RDIMM:
 180                 /* Registered/buffered DIMMs */
 181                 pdimm->registered_dimm = 1;
 182                 break;
 183
 184         case DDR4_SPD_MODULETYPE_UDIMM:
 185         case DDR4_SPD_MODULETYPE_SO_DIMM:
 186                 /* Unbuffered DIMMs */
 187                 if (spd->mod_section.unbuffered.addr_mapping & 0x1)
 188                         pdimm->mirrored_dimm = 1;
 189                 if ((spd->mod_section.unbuffered.mod_height & 0xe0) == 0 &&
 190                     (spd->mod_section.unbuffered.ref_raw_card == 0x04)) {
 191                         /* Fix SPD error found on DIMMs with raw card E0 */
 192                         for (i = 0; i < 18; i++) {
 193                                 if (spd->mapping[i] == udimm_rc_e_dq[i])
 194                                         continue;
 195                                 spd_error = 1;
 196                                 debug("SPD byte %d: 0x%x, should be 0x%x\n",
 197                                       60 + i, spd->mapping[i],
 198                                       udimm_rc_e_dq[i]);
 199                                 ptr = (u8 *)&spd->mapping[i];
 200                                 *ptr = udimm_rc_e_dq[i];
 201                         }
 202                         if (spd_error)
 203                                 puts("SPD DQ mapping error fixed\n");
 204                 }
 205                 break;
 206
 207         default:
 208                 printf("unknown module_type 0x%02X\n", spd->module_type);
 209                 return 1;
 210         }
 211
 212         /* SDRAM device parameters */
 213         pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
 214         pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
 215         pdimm->bank_addr_bits = (spd->density_banks >> 4) & 0x3;
 216         pdimm->bank_group_bits = (spd->density_banks >> 6) & 0x3;
 217
 218         /*
 219          * The SPD spec has not the ECC bit,
 220          * We consider the DIMM as ECC capability
 221          * when the extension bus exist
 222          */
 223         if (pdimm->ec_sdram_width)
 224                 pdimm->edc_config = 0x02;
 225         else
 226                 pdimm->edc_config = 0x00;
 227
 228         /*
 229          * The SPD spec has not the burst length byte
 230          * but DDR4 spec has nature BL8 and BC4,
 231          * BL8 -bit3, BC4 -bit2
 232          */
 233         pdimm->burst_lengths_bitmask = 0x0c;
 234         pdimm->row_density = __ilog2(pdimm->rank_density);
 235
 236         /* MTB - medium timebase
 237          * The MTB in the SPD spec is 125ps,
 238          *
 239          * FTB - fine timebase
 240          * use 1/10th of ps as our unit to avoid floating point
 241          * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps
 242          */
 243         if ((spd->timebases & 0xf) == 0x0) {
 244                 pdimm->mtb_ps = 125;
 245                 pdimm->ftb_10th_ps = 10;
 246
 247         } else {
 248                 printf("Unknown Timebases\n");
 249         }
 250
 251         /* sdram minimum cycle time */
 252         pdimm->tckmin_x_ps = spd_to_ps(spd->tck_min, spd->fine_tck_min);
 253
 254         /* sdram max cycle time */
 255         pdimm->tckmax_ps = spd_to_ps(spd->tck_max, spd->fine_tck_max);
 256
 257         /*
 258          * CAS latency supported
 259          * bit0 - CL7
 260          * bit4 - CL11
 261          * bit8 - CL15
 262          * bit12- CL19
 263          * bit16- CL23
 264          */
 265         pdimm->caslat_x  = (spd->caslat_b1 << 7)        |
 266                            (spd->caslat_b2 << 15)       |
 267                            (spd->caslat_b3 << 23);
 268
 269         BUG_ON(spd->caslat_b4 != 0);
 270
 271         /*
 272          * min CAS latency time
 273          */
 274         pdimm->taa_ps = spd_to_ps(spd->taa_min, spd->fine_taa_min);
 275
 276         /*
 277          * min RAS to CAS delay time
 278          */
 279         pdimm->trcd_ps = spd_to_ps(spd->trcd_min, spd->fine_trcd_min);
 280
 281         /*
 282          * Min Row Precharge Delay Time
 283          */
 284         pdimm->trp_ps = spd_to_ps(spd->trp_min, spd->fine_trp_min);
 285
 286         /* min active to precharge delay time */
 287         pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) +
 288                           spd->tras_min_lsb) * pdimm->mtb_ps;
 289
 290         /* min active to actice/refresh delay time */
 291         pdimm->trc_ps = spd_to_ps((((spd->tras_trc_ext & 0xf0) << 4) +
 292                                    spd->trc_min_lsb), spd->fine_trc_min);
 293         /* Min Refresh Recovery Delay Time */
 294         pdimm->trfc1_ps = ((spd->trfc1_min_msb << 8) | (spd->trfc1_min_lsb)) *
 295                        pdimm->mtb_ps;
 296         pdimm->trfc2_ps = ((spd->trfc2_min_msb << 8) | (spd->trfc2_min_lsb)) *
 297                        pdimm->mtb_ps;
 298         pdimm->trfc4_ps = ((spd->trfc4_min_msb << 8) | (spd->trfc4_min_lsb)) *
 299                         pdimm->mtb_ps;
 300         /* min four active window delay time */
 301         pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) *
 302                         pdimm->mtb_ps;
 303
 304         /* min row active to row active delay time, different bank group */
 305         pdimm->trrds_ps = spd_to_ps(spd->trrds_min, spd->fine_trrds_min);
 306         /* min row active to row active delay time, same bank group */
 307         pdimm->trrdl_ps = spd_to_ps(spd->trrdl_min, spd->fine_trrdl_min);
 308         /* min CAS to CAS Delay Time (tCCD_Lmin), same bank group */
 309         pdimm->tccdl_ps = spd_to_ps(spd->tccdl_min, spd->fine_tccdl_min);
 310
 311         /*
 312          * Average periodic refresh interval
 313          * tREFI = 7.8 us at normal temperature range
 314          */
 315         pdimm->refresh_rate_ps = 7800000;
 316
 317         for (i = 0; i < 18; i++)
 318                 pdimm->dq_mapping[i] = spd->mapping[i];
 319
 320         pdimm->dq_mapping_ors = ((spd->mapping[0] >> 6) & 0x3) == 0 ? 1 : 0;
 321
 322         return 0;
 323 }