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1 /*
2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7 /*
8 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
9 * Based on code from spd_sdram.c
10 * Author: James Yang [at freescale.com]
11 */
12
13 #include <common.h>
14 #include <i2c.h>
15 #include <fsl_ddr_sdram.h>
16 #include <fsl_ddr.h>
17
18 /*
19 * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
20 * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
21 * all Power SoCs. But it could be different for ARM SoCs. For example,
22 * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
23 * 0x00_8000_0000 ~ 0x00_ffff_ffff
24 * 0x80_8000_0000 ~ 0xff_ffff_ffff
25 */
26 #ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
27 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
28 #endif
29
30 #ifdef CONFIG_PPC
31 #include <asm/fsl_law.h>
32
33 void fsl_ddr_set_lawbar(
34 const common_timing_params_t *memctl_common_params,
35 unsigned int memctl_interleaved,
36 unsigned int ctrl_num);
37 #endif
38
39 void fsl_ddr_set_intl3r(const unsigned int granule_size);
40 #if defined(SPD_EEPROM_ADDRESS) || \
41 defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
42 defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
43 #if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
44 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
45 [0][0] = SPD_EEPROM_ADDRESS,
46 };
47 #elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
48 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
49 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
50 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
51 };
52 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
53 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
54 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
55 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
56 };
57 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
58 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
59 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
60 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
61 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
62 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
63 };
64 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
65 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
66 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
67 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
68 [2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */
69 };
70 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
71 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
72 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
73 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
74 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
75 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
76 [2][0] = SPD_EEPROM_ADDRESS5, /* controller 3 */
77 [2][1] = SPD_EEPROM_ADDRESS6, /* controller 3 */
78 };
79
80 #endif
81
82 #define SPD_SPA0_ADDRESS 0x36
83 #define SPD_SPA1_ADDRESS 0x37
84
85 static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
86 {
87 int ret;
88 #ifdef CONFIG_SYS_FSL_DDR4
89 uint8_t dummy = 0;
90 #endif
91
92 i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
93
94 #ifdef CONFIG_SYS_FSL_DDR4
95 /*
96 * DDR4 SPD has 384 to 512 bytes
97 * To access the lower 256 bytes, we need to set EE page address to 0
98 * To access the upper 256 bytes, we need to set EE page address to 1
99 * See Jedec standar No. 21-C for detail
100 */
101 i2c_write(SPD_SPA0_ADDRESS, 0, 1, &dummy, 1);
102 ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 256);
103 if (!ret) {
104 i2c_write(SPD_SPA1_ADDRESS, 0, 1, &dummy, 1);
105 ret = i2c_read(i2c_address, 0, 1,
106 (uchar *)((ulong)spd + 256),
107 min(256,
108 (int)sizeof(generic_spd_eeprom_t) - 256));
109 }
110 #else
111 ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
112 sizeof(generic_spd_eeprom_t));
113 #endif
114
115 if (ret) {
116 if (i2c_address ==
117 #ifdef SPD_EEPROM_ADDRESS
118 SPD_EEPROM_ADDRESS
119 #elif defined(SPD_EEPROM_ADDRESS1)
120 SPD_EEPROM_ADDRESS1
121 #endif
122 ) {
123 printf("DDR: failed to read SPD from address %u\n",
124 i2c_address);
125 } else {
126 debug("DDR: failed to read SPD from address %u\n",
127 i2c_address);
128 }
129 memset(spd, 0, sizeof(generic_spd_eeprom_t));
130 }
131 }
132
133 __attribute__((weak, alias("__get_spd")))
134 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
135
136 /* This function allows boards to update SPD address */
137 __weak void update_spd_address(unsigned int ctrl_num,
138 unsigned int slot,
139 unsigned int *addr)
140 {
141 }
142
143 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
144 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
145 {
146 unsigned int i;
147 unsigned int i2c_address = 0;
148
149 if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
150 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
151 return;
152 }
153
154 for (i = 0; i < dimm_slots_per_ctrl; i++) {
155 i2c_address = spd_i2c_addr[ctrl_num][i];
156 update_spd_address(ctrl_num, i, &i2c_address);
157 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
158 }
159 }
160 #else
161 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
162 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
163 {
164 }
165 #endif /* SPD_EEPROM_ADDRESSx */
166
167 /*
168 * ASSUMPTIONS:
169 * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
170 * - Same memory data bus width on all controllers
171 *
172 * NOTES:
173 *
174 * The memory controller and associated documentation use confusing
175 * terminology when referring to the orgranization of DRAM.
176 *
177 * Here is a terminology translation table:
178 *
179 * memory controller/documention |industry |this code |signals
180 * -------------------------------|-----------|-----------|-----------------
181 * physical bank/bank |rank |rank |chip select (CS)
182 * logical bank/sub-bank |bank |bank |bank address (BA)
183 * page/row |row |page |row address
184 * ??? |column |column |column address
185 *
186 * The naming confusion is further exacerbated by the descriptions of the
187 * memory controller interleaving feature, where accesses are interleaved
188 * _BETWEEN_ two seperate memory controllers. This is configured only in
189 * CS0_CONFIG[INTLV_CTL] of each memory controller.
190 *
191 * memory controller documentation | number of chip selects
192 * | per memory controller supported
193 * --------------------------------|-----------------------------------------
194 * cache line interleaving | 1 (CS0 only)
195 * page interleaving | 1 (CS0 only)
196 * bank interleaving | 1 (CS0 only)
197 * superbank interleraving | depends on bank (chip select)
198 * | interleraving [rank interleaving]
199 * | mode used on every memory controller
200 *
201 * Even further confusing is the existence of the interleaving feature
202 * _WITHIN_ each memory controller. The feature is referred to in
203 * documentation as chip select interleaving or bank interleaving,
204 * although it is configured in the DDR_SDRAM_CFG field.
205 *
206 * Name of field | documentation name | this code
207 * -----------------------------|-----------------------|------------------
208 * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving
209 * | interleaving
210 */
211
212 const char *step_string_tbl[] = {
213 "STEP_GET_SPD",
214 "STEP_COMPUTE_DIMM_PARMS",
215 "STEP_COMPUTE_COMMON_PARMS",
216 "STEP_GATHER_OPTS",
217 "STEP_ASSIGN_ADDRESSES",
218 "STEP_COMPUTE_REGS",
219 "STEP_PROGRAM_REGS",
220 "STEP_ALL"
221 };
222
223 const char * step_to_string(unsigned int step) {
224
225 unsigned int s = __ilog2(step);
226
227 if ((1 << s) != step)
228 return step_string_tbl[7];
229
230 if (s >= ARRAY_SIZE(step_string_tbl)) {
231 printf("Error for the step in %s\n", __func__);
232 s = 0;
233 }
234
235 return step_string_tbl[s];
236 }
237
238 static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
239 unsigned int dbw_cap_adj[])
240 {
241 unsigned int i, j;
242 unsigned long long total_mem, current_mem_base, total_ctlr_mem;
243 unsigned long long rank_density, ctlr_density = 0;
244 unsigned int first_ctrl = pinfo->first_ctrl;
245 unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
246
247 /*
248 * If a reduced data width is requested, but the SPD
249 * specifies a physically wider device, adjust the
250 * computed dimm capacities accordingly before
251 * assigning addresses.
252 */
253 for (i = first_ctrl; i <= last_ctrl; i++) {
254 unsigned int found = 0;
255
256 switch (pinfo->memctl_opts[i].data_bus_width) {
257 case 2:
258 /* 16-bit */
259 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
260 unsigned int dw;
261 if (!pinfo->dimm_params[i][j].n_ranks)
262 continue;
263 dw = pinfo->dimm_params[i][j].primary_sdram_width;
264 if ((dw == 72 || dw == 64)) {
265 dbw_cap_adj[i] = 2;
266 break;
267 } else if ((dw == 40 || dw == 32)) {
268 dbw_cap_adj[i] = 1;
269 break;
270 }
271 }
272 break;
273
274 case 1:
275 /* 32-bit */
276 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
277 unsigned int dw;
278 dw = pinfo->dimm_params[i][j].data_width;
279 if (pinfo->dimm_params[i][j].n_ranks
280 && (dw == 72 || dw == 64)) {
281 /*
282 * FIXME: can't really do it
283 * like this because this just
284 * further reduces the memory
285 */
286 found = 1;
287 break;
288 }
289 }
290 if (found) {
291 dbw_cap_adj[i] = 1;
292 }
293 break;
294
295 case 0:
296 /* 64-bit */
297 break;
298
299 default:
300 printf("unexpected data bus width "
301 "specified controller %u\n", i);
302 return 1;
303 }
304 debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
305 }
306
307 current_mem_base = pinfo->mem_base;
308 total_mem = 0;
309 if (pinfo->memctl_opts[first_ctrl].memctl_interleaving) {
310 rank_density = pinfo->dimm_params[first_ctrl][0].rank_density >>
311 dbw_cap_adj[first_ctrl];
312 switch (pinfo->memctl_opts[first_ctrl].ba_intlv_ctl &
313 FSL_DDR_CS0_CS1_CS2_CS3) {
314 case FSL_DDR_CS0_CS1_CS2_CS3:
315 ctlr_density = 4 * rank_density;
316 break;
317 case FSL_DDR_CS0_CS1:
318 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
319 ctlr_density = 2 * rank_density;
320 break;
321 case FSL_DDR_CS2_CS3:
322 default:
323 ctlr_density = rank_density;
324 break;
325 }
326 debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
327 rank_density, ctlr_density);
328 for (i = first_ctrl; i <= last_ctrl; i++) {
329 if (pinfo->memctl_opts[i].memctl_interleaving) {
330 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
331 case FSL_DDR_256B_INTERLEAVING:
332 case FSL_DDR_CACHE_LINE_INTERLEAVING:
333 case FSL_DDR_PAGE_INTERLEAVING:
334 case FSL_DDR_BANK_INTERLEAVING:
335 case FSL_DDR_SUPERBANK_INTERLEAVING:
336 total_ctlr_mem = 2 * ctlr_density;
337 break;
338 case FSL_DDR_3WAY_1KB_INTERLEAVING:
339 case FSL_DDR_3WAY_4KB_INTERLEAVING:
340 case FSL_DDR_3WAY_8KB_INTERLEAVING:
341 total_ctlr_mem = 3 * ctlr_density;
342 break;
343 case FSL_DDR_4WAY_1KB_INTERLEAVING:
344 case FSL_DDR_4WAY_4KB_INTERLEAVING:
345 case FSL_DDR_4WAY_8KB_INTERLEAVING:
346 total_ctlr_mem = 4 * ctlr_density;
347 break;
348 default:
349 panic("Unknown interleaving mode");
350 }
351 pinfo->common_timing_params[i].base_address =
352 current_mem_base;
353 pinfo->common_timing_params[i].total_mem =
354 total_ctlr_mem;
355 total_mem = current_mem_base + total_ctlr_mem;
356 debug("ctrl %d base 0x%llx\n", i, current_mem_base);
357 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
358 } else {
359 /* when 3rd controller not interleaved */
360 current_mem_base = total_mem;
361 total_ctlr_mem = 0;
362 pinfo->common_timing_params[i].base_address =
363 current_mem_base;
364 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
365 unsigned long long cap =
366 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
367 pinfo->dimm_params[i][j].base_address =
368 current_mem_base;
369 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
370 current_mem_base += cap;
371 total_ctlr_mem += cap;
372 }
373 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
374 pinfo->common_timing_params[i].total_mem =
375 total_ctlr_mem;
376 total_mem += total_ctlr_mem;
377 }
378 }
379 } else {
380 /*
381 * Simple linear assignment if memory
382 * controllers are not interleaved.
383 */
384 for (i = first_ctrl; i <= last_ctrl; i++) {
385 total_ctlr_mem = 0;
386 pinfo->common_timing_params[i].base_address =
387 current_mem_base;
388 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
389 /* Compute DIMM base addresses. */
390 unsigned long long cap =
391 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
392 pinfo->dimm_params[i][j].base_address =
393 current_mem_base;
394 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
395 current_mem_base += cap;
396 total_ctlr_mem += cap;
397 }
398 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
399 pinfo->common_timing_params[i].total_mem =
400 total_ctlr_mem;
401 total_mem += total_ctlr_mem;
402 }
403 }
404 debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
405
406 return total_mem;
407 }
408
409 /* Use weak function to allow board file to override the address assignment */
410 __attribute__((weak, alias("__step_assign_addresses")))
411 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
412 unsigned int dbw_cap_adj[]);
413
414 unsigned long long
415 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
416 unsigned int size_only)
417 {
418 unsigned int i, j;
419 unsigned long long total_mem = 0;
420 int assert_reset = 0;
421 unsigned int first_ctrl = pinfo->first_ctrl;
422 unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
423 __maybe_unused int retval;
424 __maybe_unused bool goodspd = false;
425 __maybe_unused int dimm_slots_per_ctrl = pinfo->dimm_slots_per_ctrl;
426
427 fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
428 common_timing_params_t *timing_params = pinfo->common_timing_params;
429 if (pinfo->board_need_mem_reset)
430 assert_reset = pinfo->board_need_mem_reset();
431
432 /* data bus width capacity adjust shift amount */
433 unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
434
435 for (i = first_ctrl; i <= last_ctrl; i++)
436 dbw_capacity_adjust[i] = 0;
437
438 debug("starting at step %u (%s)\n",
439 start_step, step_to_string(start_step));
440
441 switch (start_step) {
442 case STEP_GET_SPD:
443 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
444 /* STEP 1: Gather all DIMM SPD data */
445 for (i = first_ctrl; i <= last_ctrl; i++) {
446 fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i,
447 dimm_slots_per_ctrl);
448 }
449
450 case STEP_COMPUTE_DIMM_PARMS:
451 /* STEP 2: Compute DIMM parameters from SPD data */
452
453 for (i = first_ctrl; i <= last_ctrl; i++) {
454 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
455 generic_spd_eeprom_t *spd =
456 &(pinfo->spd_installed_dimms[i][j]);
457 dimm_params_t *pdimm =
458 &(pinfo->dimm_params[i][j]);
459 retval = compute_dimm_parameters(
460 i, spd, pdimm, j);
461 #ifdef CONFIG_SYS_DDR_RAW_TIMING
462 if (!j && retval) {
463 printf("SPD error on controller %d! "
464 "Trying fallback to raw timing "
465 "calculation\n", i);
466 retval = fsl_ddr_get_dimm_params(pdimm,
467 i, j);
468 }
469 #else
470 if (retval == 2) {
471 printf("Error: compute_dimm_parameters"
472 " non-zero returned FATAL value "
473 "for memctl=%u dimm=%u\n", i, j);
474 return 0;
475 }
476 #endif
477 if (retval) {
478 debug("Warning: compute_dimm_parameters"
479 " non-zero return value for memctl=%u "
480 "dimm=%u\n", i, j);
481 } else {
482 goodspd = true;
483 }
484 }
485 }
486 if (!goodspd) {
487 /*
488 * No valid SPD found
489 * Throw an error if this is for main memory, i.e.
490 * first_ctrl == 0. Otherwise, siliently return 0
491 * as the memory size.
492 */
493 if (first_ctrl == 0)
494 printf("Error: No valid SPD detected.\n");
495
496 return 0;
497 }
498 #elif defined(CONFIG_SYS_DDR_RAW_TIMING)
499 case STEP_COMPUTE_DIMM_PARMS:
500 for (i = first_ctrl; i <= last_ctrl; i++) {
501 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
502 dimm_params_t *pdimm =
503 &(pinfo->dimm_params[i][j]);
504 fsl_ddr_get_dimm_params(pdimm, i, j);
505 }
506 }
507 debug("Filling dimm parameters from board specific file\n");
508 #endif
509 case STEP_COMPUTE_COMMON_PARMS:
510 /*
511 * STEP 3: Compute a common set of timing parameters
512 * suitable for all of the DIMMs on each memory controller
513 */
514 for (i = first_ctrl; i <= last_ctrl; i++) {
515 debug("Computing lowest common DIMM"
516 " parameters for memctl=%u\n", i);
517 compute_lowest_common_dimm_parameters
518 (i,
519 pinfo->dimm_params[i],
520 &timing_params[i],
521 CONFIG_DIMM_SLOTS_PER_CTLR);
522 }
523
524 case STEP_GATHER_OPTS:
525 /* STEP 4: Gather configuration requirements from user */
526 for (i = first_ctrl; i <= last_ctrl; i++) {
527 debug("Reloading memory controller "
528 "configuration options for memctl=%u\n", i);
529 /*
530 * This "reloads" the memory controller options
531 * to defaults. If the user "edits" an option,
532 * next_step points to the step after this,
533 * which is currently STEP_ASSIGN_ADDRESSES.
534 */
535 populate_memctl_options(
536 &timing_params[i],
537 &pinfo->memctl_opts[i],
538 pinfo->dimm_params[i], i);
539 /*
540 * For RDIMMs, JEDEC spec requires clocks to be stable
541 * before reset signal is deasserted. For the boards
542 * using fixed parameters, this function should be
543 * be called from board init file.
544 */
545 if (timing_params[i].all_dimms_registered)
546 assert_reset = 1;
547 }
548 if (assert_reset && !size_only) {
549 if (pinfo->board_mem_reset) {
550 debug("Asserting mem reset\n");
551 pinfo->board_mem_reset();
552 } else {
553 debug("Asserting mem reset missing\n");
554 }
555 }
556
557 case STEP_ASSIGN_ADDRESSES:
558 /* STEP 5: Assign addresses to chip selects */
559 check_interleaving_options(pinfo);
560 total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
561 debug("Total mem %llu assigned\n", total_mem);
562
563 case STEP_COMPUTE_REGS:
564 /* STEP 6: compute controller register values */
565 debug("FSL Memory ctrl register computation\n");
566 for (i = first_ctrl; i <= last_ctrl; i++) {
567 if (timing_params[i].ndimms_present == 0) {
568 memset(&ddr_reg[i], 0,
569 sizeof(fsl_ddr_cfg_regs_t));
570 continue;
571 }
572
573 compute_fsl_memctl_config_regs
574 (i,
575 &pinfo->memctl_opts[i],
576 &ddr_reg[i], &timing_params[i],
577 pinfo->dimm_params[i],
578 dbw_capacity_adjust[i],
579 size_only);
580 }
581
582 default:
583 break;
584 }
585
586 {
587 /*
588 * Compute the amount of memory available just by
589 * looking for the highest valid CSn_BNDS value.
590 * This allows us to also experiment with using
591 * only CS0 when using dual-rank DIMMs.
592 */
593 unsigned int max_end = 0;
594
595 for (i = first_ctrl; i <= last_ctrl; i++) {
596 for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
597 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
598 if (reg->cs[j].config & 0x80000000) {
599 unsigned int end;
600 /*
601 * 0xfffffff is a special value we put
602 * for unused bnds
603 */
604 if (reg->cs[j].bnds == 0xffffffff)
605 continue;
606 end = reg->cs[j].bnds & 0xffff;
607 if (end > max_end) {
608 max_end = end;
609 }
610 }
611 }
612 }
613
614 total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
615 0xFFFFFFULL) - pinfo->mem_base;
616 }
617
618 return total_mem;
619 }
620
621 phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
622 {
623 unsigned int i, first_ctrl, last_ctrl;
624 #ifdef CONFIG_PPC
625 unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
626 #endif
627 unsigned long long total_memory;
628 int deassert_reset = 0;
629
630 first_ctrl = pinfo->first_ctrl;
631 last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
632
633 /* Compute it once normally. */
634 #ifdef CONFIG_FSL_DDR_INTERACTIVE
635 if (tstc() && (getc() == 'd')) { /* we got a key press of 'd' */
636 total_memory = fsl_ddr_interactive(pinfo, 0);
637 } else if (fsl_ddr_interactive_env_var_exists()) {
638 total_memory = fsl_ddr_interactive(pinfo, 1);
639 } else
640 #endif
641 total_memory = fsl_ddr_compute(pinfo, STEP_GET_SPD, 0);
642
643 /* setup 3-way interleaving before enabling DDRC */
644 switch (pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode) {
645 case FSL_DDR_3WAY_1KB_INTERLEAVING:
646 case FSL_DDR_3WAY_4KB_INTERLEAVING:
647 case FSL_DDR_3WAY_8KB_INTERLEAVING:
648 fsl_ddr_set_intl3r(
649 pinfo->memctl_opts[first_ctrl].
650 memctl_interleaving_mode);
651 break;
652 default:
653 break;
654 }
655
656 /*
657 * Program configuration registers.
658 * JEDEC specs requires clocks to be stable before deasserting reset
659 * for RDIMMs. Clocks start after chip select is enabled and clock
660 * control register is set. During step 1, all controllers have their
661 * registers set but not enabled. Step 2 proceeds after deasserting
662 * reset through board FPGA or GPIO.
663 * For non-registered DIMMs, initialization can go through but it is
664 * also OK to follow the same flow.
665 */
666 if (pinfo->board_need_mem_reset)
667 deassert_reset = pinfo->board_need_mem_reset();
668 for (i = first_ctrl; i <= last_ctrl; i++) {
669 if (pinfo->common_timing_params[i].all_dimms_registered)
670 deassert_reset = 1;
671 }
672 for (i = first_ctrl; i <= last_ctrl; i++) {
673 debug("Programming controller %u\n", i);
674 if (pinfo->common_timing_params[i].ndimms_present == 0) {
675 debug("No dimms present on controller %u; "
676 "skipping programming\n", i);
677 continue;
678 }
679 /*
680 * The following call with step = 1 returns before enabling
681 * the controller. It has to finish with step = 2 later.
682 */
683 fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), i,
684 deassert_reset ? 1 : 0);
685 }
686 if (deassert_reset) {
687 /* Use board FPGA or GPIO to deassert reset signal */
688 if (pinfo->board_mem_de_reset) {
689 debug("Deasserting mem reset\n");
690 pinfo->board_mem_de_reset();
691 } else {
692 debug("Deasserting mem reset missing\n");
693 }
694 for (i = first_ctrl; i <= last_ctrl; i++) {
695 /* Call with step = 2 to continue initialization */
696 fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]),
697 i, 2);
698 }
699 }
700
701 #ifdef CONFIG_FSL_DDR_SYNC_REFRESH
702 fsl_ddr_sync_memctl_refresh(first_ctrl, last_ctrl);
703 #endif
704
705 #ifdef CONFIG_PPC
706 /* program LAWs */
707 for (i = first_ctrl; i <= last_ctrl; i++) {
708 if (pinfo->memctl_opts[i].memctl_interleaving) {
709 switch (pinfo->memctl_opts[i].
710 memctl_interleaving_mode) {
711 case FSL_DDR_CACHE_LINE_INTERLEAVING:
712 case FSL_DDR_PAGE_INTERLEAVING:
713 case FSL_DDR_BANK_INTERLEAVING:
714 case FSL_DDR_SUPERBANK_INTERLEAVING:
715 if (i % 2)
716 break;
717 if (i == 0) {
718 law_memctl = LAW_TRGT_IF_DDR_INTRLV;
719 fsl_ddr_set_lawbar(
720 &pinfo->common_timing_params[i],
721 law_memctl, i);
722 }
723 #if CONFIG_NUM_DDR_CONTROLLERS > 3
724 else if (i == 2) {
725 law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
726 fsl_ddr_set_lawbar(
727 &pinfo->common_timing_params[i],
728 law_memctl, i);
729 }
730 #endif
731 break;
732 case FSL_DDR_3WAY_1KB_INTERLEAVING:
733 case FSL_DDR_3WAY_4KB_INTERLEAVING:
734 case FSL_DDR_3WAY_8KB_INTERLEAVING:
735 law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
736 if (i == 0) {
737 fsl_ddr_set_lawbar(
738 &pinfo->common_timing_params[i],
739 law_memctl, i);
740 }
741 break;
742 case FSL_DDR_4WAY_1KB_INTERLEAVING:
743 case FSL_DDR_4WAY_4KB_INTERLEAVING:
744 case FSL_DDR_4WAY_8KB_INTERLEAVING:
745 law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
746 if (i == 0)
747 fsl_ddr_set_lawbar(
748 &pinfo->common_timing_params[i],
749 law_memctl, i);
750 /* place holder for future 4-way interleaving */
751 break;
752 default:
753 break;
754 }
755 } else {
756 switch (i) {
757 case 0:
758 law_memctl = LAW_TRGT_IF_DDR_1;
759 break;
760 case 1:
761 law_memctl = LAW_TRGT_IF_DDR_2;
762 break;
763 case 2:
764 law_memctl = LAW_TRGT_IF_DDR_3;
765 break;
766 case 3:
767 law_memctl = LAW_TRGT_IF_DDR_4;
768 break;
769 default:
770 break;
771 }
772 fsl_ddr_set_lawbar(&pinfo->common_timing_params[i],
773 law_memctl, i);
774 }
775 }
776 #endif
777
778 debug("total_memory by %s = %llu\n", __func__, total_memory);
779
780 #if !defined(CONFIG_PHYS_64BIT)
781 /* Check for 4G or more. Bad. */
782 if ((first_ctrl == 0) && (total_memory >= (1ull << 32))) {
783 puts("Detected ");
784 print_size(total_memory, " of memory\n");
785 printf(" This U-Boot only supports < 4G of DDR\n");
786 printf(" You could rebuild it with CONFIG_PHYS_64BIT\n");
787 printf(" "); /* re-align to match init_func_ram print */
788 total_memory = CONFIG_MAX_MEM_MAPPED;
789 }
790 #endif
791
792 return total_memory;
793 }
794
795 /*
796 * fsl_ddr_sdram(void) -- this is the main function to be
797 * called by initdram() in the board file.
798 *
799 * It returns amount of memory configured in bytes.
800 */
801 phys_size_t fsl_ddr_sdram(void)
802 {
803 fsl_ddr_info_t info;
804
805 /* Reset info structure. */
806 memset(&info, 0, sizeof(fsl_ddr_info_t));
807 info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
808 info.first_ctrl = 0;
809 info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
810 info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
811 info.board_need_mem_reset = board_need_mem_reset;
812 info.board_mem_reset = board_assert_mem_reset;
813 info.board_mem_de_reset = board_deassert_mem_reset;
814 remove_unused_controllers(&info);
815
816 return __fsl_ddr_sdram(&info);
817 }
818
819 #ifdef CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
820 phys_size_t fsl_other_ddr_sdram(unsigned long long base,
821 unsigned int first_ctrl,
822 unsigned int num_ctrls,
823 unsigned int dimm_slots_per_ctrl,
824 int (*board_need_reset)(void),
825 void (*board_reset)(void),
826 void (*board_de_reset)(void))
827 {
828 fsl_ddr_info_t info;
829
830 /* Reset info structure. */
831 memset(&info, 0, sizeof(fsl_ddr_info_t));
832 info.mem_base = base;
833 info.first_ctrl = first_ctrl;
834 info.num_ctrls = num_ctrls;
835 info.dimm_slots_per_ctrl = dimm_slots_per_ctrl;
836 info.board_need_mem_reset = board_need_reset;
837 info.board_mem_reset = board_reset;
838 info.board_mem_de_reset = board_de_reset;
839
840 return __fsl_ddr_sdram(&info);
841 }
842 #endif
843
844 /*
845 * fsl_ddr_sdram_size(first_ctrl, last_intlv) - This function only returns the
846 * size of the total memory without setting ddr control registers.
847 */
848 phys_size_t
849 fsl_ddr_sdram_size(void)
850 {
851 fsl_ddr_info_t info;
852 unsigned long long total_memory = 0;
853
854 memset(&info, 0 , sizeof(fsl_ddr_info_t));
855 info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
856 info.first_ctrl = 0;
857 info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
858 info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
859 info.board_need_mem_reset = NULL;
860
861 /* Compute it once normally. */
862 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
863
864 return total_memory;
865 }
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