2 * Copyright 2008, 2010-2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <fsl_ddr_sdram.h>
14 * Use our own stack based buffer before relocation to allow accessing longer
15 * hwconfig strings that might be in the environment before we've relocated.
16 * This is pretty fragile on both the use of stack and if the buffer is big
17 * enough. However we will get a warning from getenv_f for the later.
20 /* Board-specific functions defined in each board's ddr.c */
21 extern void fsl_ddr_board_options(memctl_options_t
*popts
,
23 unsigned int ctrl_num
);
26 unsigned int odt_rd_cfg
;
27 unsigned int odt_wr_cfg
;
28 unsigned int odt_rtt_norm
;
29 unsigned int odt_rtt_wr
;
32 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
33 static const struct dynamic_odt single_Q
[4] = {
36 FSL_DDR_ODT_CS_AND_OTHER_DIMM
,
42 FSL_DDR_ODT_NEVER
, /* tied high */
48 FSL_DDR_ODT_CS_AND_OTHER_DIMM
,
54 FSL_DDR_ODT_NEVER
, /* tied high */
60 static const struct dynamic_odt single_D
[4] = {
77 static const struct dynamic_odt single_S
[4] = {
89 static const struct dynamic_odt dual_DD
[4] = {
92 FSL_DDR_ODT_SAME_DIMM
,
97 FSL_DDR_ODT_OTHER_DIMM
,
98 FSL_DDR_ODT_OTHER_DIMM
,
104 FSL_DDR_ODT_SAME_DIMM
,
109 FSL_DDR_ODT_OTHER_DIMM
,
110 FSL_DDR_ODT_OTHER_DIMM
,
116 static const struct dynamic_odt dual_DS
[4] = {
119 FSL_DDR_ODT_SAME_DIMM
,
124 FSL_DDR_ODT_OTHER_DIMM
,
125 FSL_DDR_ODT_OTHER_DIMM
,
130 FSL_DDR_ODT_OTHER_DIMM
,
137 static const struct dynamic_odt dual_SD
[4] = {
139 FSL_DDR_ODT_OTHER_DIMM
,
147 FSL_DDR_ODT_SAME_DIMM
,
152 FSL_DDR_ODT_OTHER_DIMM
,
153 FSL_DDR_ODT_OTHER_DIMM
,
159 static const struct dynamic_odt dual_SS
[4] = {
161 FSL_DDR_ODT_OTHER_DIMM
,
168 FSL_DDR_ODT_OTHER_DIMM
,
176 static const struct dynamic_odt dual_D0
[4] = {
179 FSL_DDR_ODT_SAME_DIMM
,
193 static const struct dynamic_odt dual_0D
[4] = {
198 FSL_DDR_ODT_SAME_DIMM
,
210 static const struct dynamic_odt dual_S0
[4] = {
223 static const struct dynamic_odt dual_0S
[4] = {
236 static const struct dynamic_odt odt_unknown
[4] = {
262 #else /* CONFIG_SYS_FSL_DDR3 || CONFIG_SYS_FSL_DDR4 */
263 static const struct dynamic_odt single_Q
[4] = {
270 static const struct dynamic_odt single_D
[4] = {
287 static const struct dynamic_odt single_S
[4] = {
299 static const struct dynamic_odt dual_DD
[4] = {
301 FSL_DDR_ODT_OTHER_DIMM
,
302 FSL_DDR_ODT_OTHER_DIMM
,
313 FSL_DDR_ODT_OTHER_DIMM
,
314 FSL_DDR_ODT_OTHER_DIMM
,
326 static const struct dynamic_odt dual_DS
[4] = {
328 FSL_DDR_ODT_OTHER_DIMM
,
329 FSL_DDR_ODT_OTHER_DIMM
,
340 FSL_DDR_ODT_OTHER_DIMM
,
341 FSL_DDR_ODT_OTHER_DIMM
,
348 static const struct dynamic_odt dual_SD
[4] = {
350 FSL_DDR_ODT_OTHER_DIMM
,
351 FSL_DDR_ODT_OTHER_DIMM
,
357 FSL_DDR_ODT_OTHER_DIMM
,
358 FSL_DDR_ODT_OTHER_DIMM
,
370 static const struct dynamic_odt dual_SS
[4] = {
372 FSL_DDR_ODT_OTHER_DIMM
,
373 FSL_DDR_ODT_OTHER_DIMM
,
379 FSL_DDR_ODT_OTHER_DIMM
,
380 FSL_DDR_ODT_OTHER_DIMM
,
387 static const struct dynamic_odt dual_D0
[4] = {
404 static const struct dynamic_odt dual_0D
[4] = {
421 static const struct dynamic_odt dual_S0
[4] = {
434 static const struct dynamic_odt dual_0S
[4] = {
447 static const struct dynamic_odt odt_unknown
[4] = {
476 * Automatically seleect bank interleaving mode based on DIMMs
477 * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null.
478 * This function only deal with one or two slots per controller.
480 static inline unsigned int auto_bank_intlv(dimm_params_t
*pdimm
)
482 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
483 if (pdimm
[0].n_ranks
== 4)
484 return FSL_DDR_CS0_CS1_CS2_CS3
;
485 else if (pdimm
[0].n_ranks
== 2)
486 return FSL_DDR_CS0_CS1
;
487 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
488 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
489 if (pdimm
[0].n_ranks
== 4)
490 return FSL_DDR_CS0_CS1_CS2_CS3
;
492 if (pdimm
[0].n_ranks
== 2) {
493 if (pdimm
[1].n_ranks
== 2)
494 return FSL_DDR_CS0_CS1_CS2_CS3
;
496 return FSL_DDR_CS0_CS1
;
502 unsigned int populate_memctl_options(int all_dimms_registered
,
503 memctl_options_t
*popts
,
504 dimm_params_t
*pdimm
,
505 unsigned int ctrl_num
)
508 char buffer
[HWCONFIG_BUFFER_SIZE
];
510 #if defined(CONFIG_SYS_FSL_DDR3) || \
511 defined(CONFIG_SYS_FSL_DDR2) || \
512 defined(CONFIG_SYS_FSL_DDR4)
513 const struct dynamic_odt
*pdodt
= odt_unknown
;
518 * Extract hwconfig from environment since we have not properly setup
519 * the environment but need it for ddr config params
521 if (getenv_f("hwconfig", buffer
, sizeof(buffer
)) > 0)
524 #if defined(CONFIG_SYS_FSL_DDR3) || \
525 defined(CONFIG_SYS_FSL_DDR2) || \
526 defined(CONFIG_SYS_FSL_DDR4)
527 /* Chip select options. */
528 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
529 switch (pdimm
[0].n_ranks
) {
540 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
541 switch (pdimm
[0].n_ranks
) {
542 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
545 if (pdimm
[1].n_ranks
)
546 printf("Error: Quad- and Dual-rank DIMMs cannot be used together\n");
550 switch (pdimm
[1].n_ranks
) {
563 switch (pdimm
[1].n_ranks
) {
576 switch (pdimm
[1].n_ranks
) {
586 #endif /* CONFIG_DIMM_SLOTS_PER_CTLR */
587 #endif /* CONFIG_SYS_FSL_DDR2, 3, 4 */
589 /* Pick chip-select local options. */
590 for (i
= 0; i
< CONFIG_CHIP_SELECTS_PER_CTRL
; i
++) {
591 #if defined(CONFIG_SYS_FSL_DDR3) || \
592 defined(CONFIG_SYS_FSL_DDR2) || \
593 defined(CONFIG_SYS_FSL_DDR4)
594 popts
->cs_local_opts
[i
].odt_rd_cfg
= pdodt
[i
].odt_rd_cfg
;
595 popts
->cs_local_opts
[i
].odt_wr_cfg
= pdodt
[i
].odt_wr_cfg
;
596 popts
->cs_local_opts
[i
].odt_rtt_norm
= pdodt
[i
].odt_rtt_norm
;
597 popts
->cs_local_opts
[i
].odt_rtt_wr
= pdodt
[i
].odt_rtt_wr
;
599 popts
->cs_local_opts
[i
].odt_rd_cfg
= FSL_DDR_ODT_NEVER
;
600 popts
->cs_local_opts
[i
].odt_wr_cfg
= FSL_DDR_ODT_CS
;
602 popts
->cs_local_opts
[i
].auto_precharge
= 0;
605 /* Pick interleaving mode. */
608 * 0 = no interleaving
609 * 1 = interleaving between 2 controllers
611 popts
->memctl_interleaving
= 0;
617 * 3 = superbank (only if CS interleaving is enabled)
619 popts
->memctl_interleaving_mode
= 0;
622 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
623 * 1: page: bit to the left of the column bits selects the memctl
624 * 2: bank: bit to the left of the bank bits selects the memctl
625 * 3: superbank: bit to the left of the chip select selects the memctl
627 * NOTE: ba_intlv (rank interleaving) is independent of memory
628 * controller interleaving; it is only within a memory controller.
629 * Must use superbank interleaving if rank interleaving is used and
630 * memory controller interleaving is enabled.
637 * 0x60 = CS0,CS1 + CS2,CS3
638 * 0x04 = CS0,CS1,CS2,CS3
640 popts
->ba_intlv_ctl
= 0;
642 /* Memory Organization Parameters */
643 popts
->registered_dimm_en
= all_dimms_registered
;
645 /* Operational Mode Paramters */
648 popts
->ecc_mode
= 0; /* 0 = disabled, 1 = enabled */
649 #ifdef CONFIG_DDR_ECC
650 if (hwconfig_sub_f("fsl_ddr", "ecc", buf
)) {
651 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf
))
656 popts
->ecc_init_using_memctl
= 1; /* 0 = use DMA, 1 = use memctl */
663 #if defined(CONFIG_SYS_FSL_DDR1)
664 popts
->dqs_config
= 0;
665 #elif defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
666 popts
->dqs_config
= 1;
669 /* Choose self-refresh during sleep. */
670 popts
->self_refresh_in_sleep
= 1;
672 /* Choose dynamic power management mode. */
673 popts
->dynamic_power
= 0;
676 * check first dimm for primary sdram width
677 * presuming all dimms are similar
678 * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
680 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
681 if (pdimm
[0].n_ranks
!= 0) {
682 if ((pdimm
[0].data_width
>= 64) && \
683 (pdimm
[0].data_width
<= 72))
684 popts
->data_bus_width
= 0;
685 else if ((pdimm
[0].data_width
>= 32) || \
686 (pdimm
[0].data_width
<= 40))
687 popts
->data_bus_width
= 1;
689 panic("Error: data width %u is invalid!\n",
690 pdimm
[0].data_width
);
694 if (pdimm
[0].n_ranks
!= 0) {
695 if (pdimm
[0].primary_sdram_width
== 64)
696 popts
->data_bus_width
= 0;
697 else if (pdimm
[0].primary_sdram_width
== 32)
698 popts
->data_bus_width
= 1;
699 else if (pdimm
[0].primary_sdram_width
== 16)
700 popts
->data_bus_width
= 2;
702 panic("Error: primary sdram width %u is invalid!\n",
703 pdimm
[0].primary_sdram_width
);
708 popts
->x4_en
= (pdimm
[0].device_width
== 4) ? 1 : 0;
710 /* Choose burst length. */
711 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
712 #if defined(CONFIG_E500MC)
713 popts
->otf_burst_chop_en
= 0; /* on-the-fly burst chop disable */
714 popts
->burst_length
= DDR_BL8
; /* Fixed 8-beat burst len */
716 if ((popts
->data_bus_width
== 1) || (popts
->data_bus_width
== 2)) {
717 /* 32-bit or 16-bit bus */
718 popts
->otf_burst_chop_en
= 0;
719 popts
->burst_length
= DDR_BL8
;
721 popts
->otf_burst_chop_en
= 1; /* on-the-fly burst chop */
722 popts
->burst_length
= DDR_OTF
; /* on-the-fly BC4 and BL8 */
726 popts
->burst_length
= DDR_BL4
; /* has to be 4 for DDR2 */
729 /* Choose ddr controller address mirror mode */
730 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
731 popts
->mirrored_dimm
= pdimm
[0].mirrored_dimm
;
734 /* Global Timing Parameters. */
735 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
737 /* Pick a caslat override. */
738 popts
->cas_latency_override
= 0;
739 popts
->cas_latency_override_value
= 3;
740 if (popts
->cas_latency_override
) {
741 debug("using caslat override value = %u\n",
742 popts
->cas_latency_override_value
);
745 /* Decide whether to use the computed derated latency */
746 popts
->use_derated_caslat
= 0;
748 /* Choose an additive latency. */
749 popts
->additive_latency_override
= 0;
750 popts
->additive_latency_override_value
= 3;
751 if (popts
->additive_latency_override
) {
752 debug("using additive latency override value = %u\n",
753 popts
->additive_latency_override_value
);
759 * Factors to consider for 2T_EN:
760 * - number of DIMMs installed
761 * - number of components, number of active ranks
762 * - how much time you want to spend playing around
765 popts
->threet_en
= 0;
767 /* for RDIMM, address parity enable */
771 * BSTTOPRE precharge interval
773 * Set this to 0 for global auto precharge
774 * The value of 0x100 has been used for DDR1, DDR2, DDR3.
775 * It is not wrong. Any value should be OK. The performance depends on
776 * applications. There is no one good value for all.
778 popts
->bstopre
= 0x100;
781 * Window for four activates -- tFAW
783 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
784 * FIXME: varies depending upon number of column addresses or data
785 * FIXME: width, was considering looking at pdimm->primary_sdram_width
787 #if defined(CONFIG_SYS_FSL_DDR1)
788 popts
->tfaw_window_four_activates_ps
= mclk_to_picos(1);
790 #elif defined(CONFIG_SYS_FSL_DDR2)
792 * x4/x8; some datasheets have 35000
793 * x16 wide columns only? Use 50000?
795 popts
->tfaw_window_four_activates_ps
= 37500;
798 popts
->tfaw_window_four_activates_ps
= pdimm
[0].tfaw_ps
;
802 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
804 * due to ddr3 dimm is fly-by topology
805 * we suggest to enable write leveling to
806 * meet the tQDSS under different loading.
810 popts
->wrlvl_override
= 0;
814 * Check interleaving configuration from environment.
815 * Please refer to doc/README.fsl-ddr for the detail.
817 * If memory controller interleaving is enabled, then the data
818 * bus widths must be programmed identically for all memory controllers.
820 * Attempt to set all controllers to the same chip select
821 * interleaving mode. It will do a best effort to get the
822 * requested ranks interleaved together such that the result
823 * should be a subset of the requested configuration.
825 * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving
826 * with 256 Byte is enabled.
828 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
829 if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf
))
830 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
835 if (pdimm
[0].n_ranks
== 0) {
836 printf("There is no rank on CS0 for controller %d.\n", ctrl_num
);
837 popts
->memctl_interleaving
= 0;
840 popts
->memctl_interleaving
= 1;
841 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
842 popts
->memctl_interleaving_mode
= FSL_DDR_256B_INTERLEAVING
;
843 popts
->memctl_interleaving
= 1;
844 debug("256 Byte interleaving\n");
847 * test null first. if CONFIG_HWCONFIG is not defined
848 * hwconfig_arg_cmp returns non-zero
850 if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
852 popts
->memctl_interleaving
= 0;
853 debug("memory controller interleaving disabled.\n");
854 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
857 popts
->memctl_interleaving_mode
=
858 ((CONFIG_NUM_DDR_CONTROLLERS
== 3) && ctrl_num
== 2) ?
859 0 : FSL_DDR_CACHE_LINE_INTERLEAVING
;
860 popts
->memctl_interleaving
=
861 ((CONFIG_NUM_DDR_CONTROLLERS
== 3) && ctrl_num
== 2) ?
863 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
866 popts
->memctl_interleaving_mode
=
867 ((CONFIG_NUM_DDR_CONTROLLERS
== 3) && ctrl_num
== 2) ?
868 0 : FSL_DDR_PAGE_INTERLEAVING
;
869 popts
->memctl_interleaving
=
870 ((CONFIG_NUM_DDR_CONTROLLERS
== 3) && ctrl_num
== 2) ?
872 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
875 popts
->memctl_interleaving_mode
=
876 ((CONFIG_NUM_DDR_CONTROLLERS
== 3) && ctrl_num
== 2) ?
877 0 : FSL_DDR_BANK_INTERLEAVING
;
878 popts
->memctl_interleaving
=
879 ((CONFIG_NUM_DDR_CONTROLLERS
== 3) && ctrl_num
== 2) ?
881 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
884 popts
->memctl_interleaving_mode
=
885 ((CONFIG_NUM_DDR_CONTROLLERS
== 3) && ctrl_num
== 2) ?
886 0 : FSL_DDR_SUPERBANK_INTERLEAVING
;
887 popts
->memctl_interleaving
=
888 ((CONFIG_NUM_DDR_CONTROLLERS
== 3) && ctrl_num
== 2) ?
890 #if (CONFIG_NUM_DDR_CONTROLLERS == 3)
891 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
894 popts
->memctl_interleaving_mode
=
895 FSL_DDR_3WAY_1KB_INTERLEAVING
;
896 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
899 popts
->memctl_interleaving_mode
=
900 FSL_DDR_3WAY_4KB_INTERLEAVING
;
901 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
904 popts
->memctl_interleaving_mode
=
905 FSL_DDR_3WAY_8KB_INTERLEAVING
;
906 #elif (CONFIG_NUM_DDR_CONTROLLERS == 4)
907 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
910 popts
->memctl_interleaving_mode
=
911 FSL_DDR_4WAY_1KB_INTERLEAVING
;
912 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
915 popts
->memctl_interleaving_mode
=
916 FSL_DDR_4WAY_4KB_INTERLEAVING
;
917 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
920 popts
->memctl_interleaving_mode
=
921 FSL_DDR_4WAY_8KB_INTERLEAVING
;
924 popts
->memctl_interleaving
= 0;
925 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
927 #endif /* CONFIG_SYS_FSL_DDR_INTLV_256B */
929 #endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
930 if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf
)) &&
931 (CONFIG_CHIP_SELECTS_PER_CTRL
> 1)) {
932 /* test null first. if CONFIG_HWCONFIG is not defined,
933 * hwconfig_subarg_cmp_f returns non-zero */
934 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
936 debug("bank interleaving disabled.\n");
937 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
939 popts
->ba_intlv_ctl
= FSL_DDR_CS0_CS1
;
940 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
942 popts
->ba_intlv_ctl
= FSL_DDR_CS2_CS3
;
943 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
944 "cs0_cs1_and_cs2_cs3", buf
))
945 popts
->ba_intlv_ctl
= FSL_DDR_CS0_CS1_AND_CS2_CS3
;
946 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
947 "cs0_cs1_cs2_cs3", buf
))
948 popts
->ba_intlv_ctl
= FSL_DDR_CS0_CS1_CS2_CS3
;
949 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
951 popts
->ba_intlv_ctl
= auto_bank_intlv(pdimm
);
953 printf("hwconfig has unrecognized parameter for bank_intlv.\n");
954 switch (popts
->ba_intlv_ctl
& FSL_DDR_CS0_CS1_CS2_CS3
) {
955 case FSL_DDR_CS0_CS1_CS2_CS3
:
956 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
957 if (pdimm
[0].n_ranks
< 4) {
958 popts
->ba_intlv_ctl
= 0;
959 printf("Not enough bank(chip-select) for "
960 "CS0+CS1+CS2+CS3 on controller %d, "
961 "interleaving disabled!\n", ctrl_num
);
963 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
964 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
965 if (pdimm
[0].n_ranks
== 4)
968 if ((pdimm
[0].n_ranks
< 2) && (pdimm
[1].n_ranks
< 2)) {
969 popts
->ba_intlv_ctl
= 0;
970 printf("Not enough bank(chip-select) for "
971 "CS0+CS1+CS2+CS3 on controller %d, "
972 "interleaving disabled!\n", ctrl_num
);
974 if (pdimm
[0].capacity
!= pdimm
[1].capacity
) {
975 popts
->ba_intlv_ctl
= 0;
976 printf("Not identical DIMM size for "
977 "CS0+CS1+CS2+CS3 on controller %d, "
978 "interleaving disabled!\n", ctrl_num
);
982 case FSL_DDR_CS0_CS1
:
983 if (pdimm
[0].n_ranks
< 2) {
984 popts
->ba_intlv_ctl
= 0;
985 printf("Not enough bank(chip-select) for "
986 "CS0+CS1 on controller %d, "
987 "interleaving disabled!\n", ctrl_num
);
990 case FSL_DDR_CS2_CS3
:
991 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
992 if (pdimm
[0].n_ranks
< 4) {
993 popts
->ba_intlv_ctl
= 0;
994 printf("Not enough bank(chip-select) for CS2+CS3 "
995 "on controller %d, interleaving disabled!\n", ctrl_num
);
997 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
998 if (pdimm
[1].n_ranks
< 2) {
999 popts
->ba_intlv_ctl
= 0;
1000 printf("Not enough bank(chip-select) for CS2+CS3 "
1001 "on controller %d, interleaving disabled!\n", ctrl_num
);
1005 case FSL_DDR_CS0_CS1_AND_CS2_CS3
:
1006 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
1007 if (pdimm
[0].n_ranks
< 4) {
1008 popts
->ba_intlv_ctl
= 0;
1009 printf("Not enough bank(CS) for CS0+CS1 and "
1010 "CS2+CS3 on controller %d, "
1011 "interleaving disabled!\n", ctrl_num
);
1013 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1014 if ((pdimm
[0].n_ranks
< 2) || (pdimm
[1].n_ranks
< 2)) {
1015 popts
->ba_intlv_ctl
= 0;
1016 printf("Not enough bank(CS) for CS0+CS1 and "
1017 "CS2+CS3 on controller %d, "
1018 "interleaving disabled!\n", ctrl_num
);
1023 popts
->ba_intlv_ctl
= 0;
1028 if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf
)) {
1029 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf
))
1030 popts
->addr_hash
= 0;
1031 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
1033 popts
->addr_hash
= 1;
1036 if (pdimm
[0].n_ranks
== 4)
1037 popts
->quad_rank_present
= 1;
1039 ddr_freq
= get_ddr_freq(0) / 1000000;
1040 if (popts
->registered_dimm_en
) {
1041 popts
->rcw_override
= 1;
1042 popts
->rcw_1
= 0x000a5a00;
1043 if (ddr_freq
<= 800)
1044 popts
->rcw_2
= 0x00000000;
1045 else if (ddr_freq
<= 1066)
1046 popts
->rcw_2
= 0x00100000;
1047 else if (ddr_freq
<= 1333)
1048 popts
->rcw_2
= 0x00200000;
1050 popts
->rcw_2
= 0x00300000;
1053 fsl_ddr_board_options(popts
, pdimm
, ctrl_num
);
1058 void check_interleaving_options(fsl_ddr_info_t
*pinfo
)
1060 int i
, j
, k
, check_n_ranks
, intlv_invalid
= 0;
1061 unsigned int check_intlv
, check_n_row_addr
, check_n_col_addr
;
1062 unsigned long long check_rank_density
;
1063 struct dimm_params_s
*dimm
;
1064 int first_ctrl
= pinfo
->first_ctrl
;
1065 int last_ctrl
= first_ctrl
+ pinfo
->num_ctrls
- 1;
1068 * Check if all controllers are configured for memory
1069 * controller interleaving. Identical dimms are recommended. At least
1070 * the size, row and col address should be checked.
1073 check_n_ranks
= pinfo
->dimm_params
[first_ctrl
][0].n_ranks
;
1074 check_rank_density
= pinfo
->dimm_params
[first_ctrl
][0].rank_density
;
1075 check_n_row_addr
= pinfo
->dimm_params
[first_ctrl
][0].n_row_addr
;
1076 check_n_col_addr
= pinfo
->dimm_params
[first_ctrl
][0].n_col_addr
;
1077 check_intlv
= pinfo
->memctl_opts
[first_ctrl
].memctl_interleaving_mode
;
1078 for (i
= first_ctrl
; i
<= last_ctrl
; i
++) {
1079 dimm
= &pinfo
->dimm_params
[i
][0];
1080 if (!pinfo
->memctl_opts
[i
].memctl_interleaving
) {
1082 } else if (((check_rank_density
!= dimm
->rank_density
) ||
1083 (check_n_ranks
!= dimm
->n_ranks
) ||
1084 (check_n_row_addr
!= dimm
->n_row_addr
) ||
1085 (check_n_col_addr
!= dimm
->n_col_addr
) ||
1087 pinfo
->memctl_opts
[i
].memctl_interleaving_mode
))){
1095 if (intlv_invalid
) {
1096 for (i
= first_ctrl
; i
<= last_ctrl
; i
++)
1097 pinfo
->memctl_opts
[i
].memctl_interleaving
= 0;
1098 printf("Not all DIMMs are identical. "
1099 "Memory controller interleaving disabled.\n");
1101 switch (check_intlv
) {
1102 case FSL_DDR_256B_INTERLEAVING
:
1103 case FSL_DDR_CACHE_LINE_INTERLEAVING
:
1104 case FSL_DDR_PAGE_INTERLEAVING
:
1105 case FSL_DDR_BANK_INTERLEAVING
:
1106 case FSL_DDR_SUPERBANK_INTERLEAVING
:
1107 #if (3 == CONFIG_NUM_DDR_CONTROLLERS)
1110 k
= CONFIG_NUM_DDR_CONTROLLERS
;
1113 case FSL_DDR_3WAY_1KB_INTERLEAVING
:
1114 case FSL_DDR_3WAY_4KB_INTERLEAVING
:
1115 case FSL_DDR_3WAY_8KB_INTERLEAVING
:
1116 case FSL_DDR_4WAY_1KB_INTERLEAVING
:
1117 case FSL_DDR_4WAY_4KB_INTERLEAVING
:
1118 case FSL_DDR_4WAY_8KB_INTERLEAVING
:
1120 k
= CONFIG_NUM_DDR_CONTROLLERS
;
1123 debug("%d of %d controllers are interleaving.\n", j
, k
);
1124 if (j
&& (j
!= k
)) {
1125 for (i
= first_ctrl
; i
<= last_ctrl
; i
++)
1126 pinfo
->memctl_opts
[i
].memctl_interleaving
= 0;
1127 if ((last_ctrl
- first_ctrl
) > 1)
1128 puts("Not all controllers have compatible interleaving mode. All disabled.\n");
1131 debug("Checking interleaving options completed\n");
1134 int fsl_use_spd(void)
1138 #ifdef CONFIG_DDR_SPD
1139 char buffer
[HWCONFIG_BUFFER_SIZE
];
1143 * Extract hwconfig from environment since we have not properly setup
1144 * the environment but need it for ddr config params
1146 if (getenv_f("hwconfig", buffer
, sizeof(buffer
)) > 0)
1149 /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
1150 if (hwconfig_sub_f("fsl_ddr", "sdram", buf
)) {
1151 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf
))
1153 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",