2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
11 #include <asm/fsl_law.h>
16 #include <fsl_immap.h>
19 /* To avoid 64-bit full-divides, we factor this here */
20 #define ULL_2E12 2000000000000ULL
21 #define UL_5POW12 244140625UL
22 #define UL_2POW13 (1UL << 13)
24 #define ULL_8FS 0xFFFFFFFFULL
26 u32
fsl_ddr_get_version(void)
28 struct ccsr_ddr __iomem
*ddr
;
29 u32 ver_major_minor_errata
;
31 ddr
= (void *)_DDR_ADDR
;
32 ver_major_minor_errata
= (ddr_in32(&ddr
->ip_rev1
) & 0xFFFF) << 8;
33 ver_major_minor_errata
|= (ddr_in32(&ddr
->ip_rev2
) & 0xFF00) >> 8;
35 return ver_major_minor_errata
;
39 * Round up mclk_ps to nearest 1 ps in memory controller code
40 * if the error is 0.5ps or more.
42 * If an imprecise data rate is too high due to rounding error
43 * propagation, compute a suitably rounded mclk_ps to compute
44 * a working memory controller configuration.
46 unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num
)
48 unsigned int data_rate
= get_ddr_freq(ctrl_num
);
51 /* Round to nearest 10ps, being careful about 64-bit multiply/divide */
52 unsigned long long rem
, mclk_ps
= ULL_2E12
;
54 /* Now perform the big divide, the result fits in 32-bits */
55 rem
= do_div(mclk_ps
, data_rate
);
56 result
= (rem
>= (data_rate
>> 1)) ? mclk_ps
+ 1 : mclk_ps
;
61 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
62 unsigned int picos_to_mclk(const unsigned int ctrl_num
, unsigned int picos
)
64 unsigned long long clks
, clks_rem
;
65 unsigned long data_rate
= get_ddr_freq(ctrl_num
);
67 /* Short circuit for zero picos */
71 /* First multiply the time by the data rate (32x32 => 64) */
72 clks
= picos
* (unsigned long long)data_rate
;
74 * Now divide by 5^12 and track the 32-bit remainder, then divide
75 * by 2*(2^12) using shifts (and updating the remainder).
77 clks_rem
= do_div(clks
, UL_5POW12
);
78 clks_rem
+= (clks
& (UL_2POW13
-1)) * UL_5POW12
;
81 /* If we had a remainder greater than the 1ps error, then round up */
82 if (clks_rem
> data_rate
)
85 /* Clamp to the maximum representable value */
88 return (unsigned int) clks
;
91 unsigned int mclk_to_picos(const unsigned int ctrl_num
, unsigned int mclk
)
93 return get_memory_clk_period_ps(ctrl_num
) * mclk
;
98 __fsl_ddr_set_lawbar(const common_timing_params_t
*memctl_common_params
,
99 unsigned int law_memctl
,
100 unsigned int ctrl_num
)
102 unsigned long long base
= memctl_common_params
->base_address
;
103 unsigned long long size
= memctl_common_params
->total_mem
;
106 * If no DIMMs on this controller, do not proceed any further.
108 if (!memctl_common_params
->ndimms_present
) {
112 #if !defined(CONFIG_PHYS_64BIT)
113 if (base
>= CONFIG_MAX_MEM_MAPPED
)
115 if ((base
+ size
) >= CONFIG_MAX_MEM_MAPPED
)
116 size
= CONFIG_MAX_MEM_MAPPED
- base
;
118 if (set_ddr_laws(base
, size
, law_memctl
) < 0) {
119 printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__
, ctrl_num
,
123 debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n",
124 base
, size
, law_memctl
);
127 __attribute__((weak
, alias("__fsl_ddr_set_lawbar"))) void
128 fsl_ddr_set_lawbar(const common_timing_params_t
*memctl_common_params
,
129 unsigned int memctl_interleaved
,
130 unsigned int ctrl_num
);
133 void fsl_ddr_set_intl3r(const unsigned int granule_size
)
136 u32
*mcintl3r
= (void *) (CONFIG_SYS_IMMR
+ 0x18004);
137 *mcintl3r
= 0x80000000 | (granule_size
& 0x1f);
138 debug("Enable MCINTL3R with granule size 0x%x\n", granule_size
);
142 u32
fsl_ddr_get_intl3r(void)
146 u32
*mcintl3r
= (void *) (CONFIG_SYS_IMMR
+ 0x18004);
152 void print_ddr_info(unsigned int start_ctrl
)
154 struct ccsr_ddr __iomem
*ddr
=
155 (struct ccsr_ddr __iomem
*)(CONFIG_SYS_FSL_DDR_ADDR
);
157 #if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3)
158 u32
*mcintl3r
= (void *) (CONFIG_SYS_IMMR
+ 0x18004);
160 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
161 uint32_t cs0_config
= ddr_in32(&ddr
->cs0_config
);
163 uint32_t sdram_cfg
= ddr_in32(&ddr
->sdram_cfg
);
166 #if CONFIG_NUM_DDR_CONTROLLERS >= 2
167 if ((!(sdram_cfg
& SDRAM_CFG_MEM_EN
)) ||
169 ddr
= (void __iomem
*)CONFIG_SYS_FSL_DDR2_ADDR
;
170 sdram_cfg
= ddr_in32(&ddr
->sdram_cfg
);
173 #if CONFIG_NUM_DDR_CONTROLLERS >= 3
174 if ((!(sdram_cfg
& SDRAM_CFG_MEM_EN
)) ||
176 ddr
= (void __iomem
*)CONFIG_SYS_FSL_DDR3_ADDR
;
177 sdram_cfg
= ddr_in32(&ddr
->sdram_cfg
);
181 if (!(sdram_cfg
& SDRAM_CFG_MEM_EN
)) {
182 puts(" (DDR not enabled)\n");
187 switch ((sdram_cfg
& SDRAM_CFG_SDRAM_TYPE_MASK
) >>
188 SDRAM_CFG_SDRAM_TYPE_SHIFT
) {
189 case SDRAM_TYPE_DDR1
:
192 case SDRAM_TYPE_DDR2
:
195 case SDRAM_TYPE_DDR3
:
198 case SDRAM_TYPE_DDR4
:
206 if (sdram_cfg
& SDRAM_CFG_32_BE
)
208 else if (sdram_cfg
& SDRAM_CFG_16_BE
)
213 /* Calculate CAS latency based on timing cfg values */
214 cas_lat
= ((ddr_in32(&ddr
->timing_cfg_1
) >> 16) & 0xf);
215 if (fsl_ddr_get_version() <= 0x40400)
219 cas_lat
+= ((ddr_in32(&ddr
->timing_cfg_3
) >> 12) & 3) << 4;
220 printf(", CL=%d", cas_lat
>> 1);
224 if (sdram_cfg
& SDRAM_CFG_ECC_EN
)
229 #if (CONFIG_NUM_DDR_CONTROLLERS == 3)
231 if (*mcintl3r
& 0x80000000) {
233 puts(" DDR Controller Interleaving Mode: ");
234 switch (*mcintl3r
& 0x1f) {
235 case FSL_DDR_3WAY_1KB_INTERLEAVING
:
238 case FSL_DDR_3WAY_4KB_INTERLEAVING
:
241 case FSL_DDR_3WAY_8KB_INTERLEAVING
:
245 puts("3-way UNKNOWN");
251 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
252 if ((cs0_config
& 0x20000000) && (start_ctrl
== 0)) {
254 puts(" DDR Controller Interleaving Mode: ");
256 switch ((cs0_config
>> 24) & 0xf) {
257 case FSL_DDR_256B_INTERLEAVING
:
260 case FSL_DDR_CACHE_LINE_INTERLEAVING
:
263 case FSL_DDR_PAGE_INTERLEAVING
:
266 case FSL_DDR_BANK_INTERLEAVING
:
269 case FSL_DDR_SUPERBANK_INTERLEAVING
:
279 if ((sdram_cfg
>> 8) & 0x7f) {
281 puts(" DDR Chip-Select Interleaving Mode: ");
282 switch(sdram_cfg
>> 8 & 0x7f) {
283 case FSL_DDR_CS0_CS1_CS2_CS3
:
284 puts("CS0+CS1+CS2+CS3");
286 case FSL_DDR_CS0_CS1
:
289 case FSL_DDR_CS2_CS3
:
292 case FSL_DDR_CS0_CS1_AND_CS2_CS3
:
293 puts("CS0+CS1 and CS2+CS3");
302 void __weak
detail_board_ddr_info(void)
307 void board_add_ram_info(int use_default
)
309 detail_board_ddr_info();
312 #ifdef CONFIG_FSL_DDR_SYNC_REFRESH
313 #define DDRC_DEBUG20_INIT_DONE 0x80000000
314 #define DDRC_DEBUG2_RF 0x00000040
315 void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl
,
316 unsigned int last_ctrl
)
320 u32 ddrc_debug2
[CONFIG_NUM_DDR_CONTROLLERS
] = {};
321 u32
*ddrc_debug2_p
[CONFIG_NUM_DDR_CONTROLLERS
] = {};
322 struct ccsr_ddr __iomem
*ddr
;
324 for (i
= first_ctrl
; i
<= last_ctrl
; i
++) {
327 ddr
= (void *)CONFIG_SYS_FSL_DDR_ADDR
;
329 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
331 ddr
= (void *)CONFIG_SYS_FSL_DDR2_ADDR
;
334 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
336 ddr
= (void *)CONFIG_SYS_FSL_DDR3_ADDR
;
339 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
341 ddr
= (void *)CONFIG_SYS_FSL_DDR4_ADDR
;
345 printf("%s unexpected ctrl = %u\n", __func__
, i
);
348 ddrc_debug20
= ddr_in32(&ddr
->debug
[19]);
349 ddrc_debug2_p
[i
] = &ddr
->debug
[1];
350 while (!(ddrc_debug20
& DDRC_DEBUG20_INIT_DONE
)) {
351 /* keep polling until DDRC init is done */
353 ddrc_debug20
= ddr_in32(&ddr
->debug
[19]);
355 ddrc_debug2
[i
] = ddr_in32(&ddr
->debug
[1]) | DDRC_DEBUG2_RF
;
359 * This is put together to make sure the refresh reqeusts are sent
360 * closely to each other.
362 for (i
= first_ctrl
; i
<= last_ctrl
; i
++)
363 ddr_out32(ddrc_debug2_p
[i
], ddrc_debug2
[i
]);
365 #endif /* CONFIG_FSL_DDR_SYNC_REFRESH */