drivers/ddr/marvell/axp/ddr3_hw_training.h

   1 /*
   2  * Copyright (C) Marvell International Ltd. and its affiliates
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #ifndef __DDR3_TRAINING_H
   8 #define __DDR3_TRAINING_H
   9
  10 #include "ddr3_init.h"
  11
  12 #ifdef MV88F78X60
  13 #include "ddr3_axp.h"
  14 #elif defined(MV88F67XX)
  15 #include "ddr3_a370.h"
  16 #elif defined(MV88F672X)
  17 #include "ddr3_a375.h"
  18 #endif
  19
  20 /* The following is a list of Marvell status    */
  21 #define MV_ERROR        (-1)
  22 #define MV_OK           (0x00)  /* Operation succeeded                   */
  23 #define MV_FAIL         (0x01)  /* Operation failed                      */
  24 #define MV_BAD_VALUE    (0x02)  /* Illegal value (general)               */
  25 #define MV_OUT_OF_RANGE (0x03)  /* The value is out of range             */
  26 #define MV_BAD_PARAM    (0x04)  /* Illegal parameter in function called  */
  27 #define MV_BAD_PTR      (0x05)  /* Illegal pointer value                 */
  28 #define MV_BAD_SIZE     (0x06)  /* Illegal size                          */
  29 #define MV_BAD_STATE    (0x07)  /* Illegal state of state machine        */
  30 #define MV_SET_ERROR    (0x08)  /* Set operation failed                  */
  31 #define MV_GET_ERROR    (0x09)  /* Get operation failed                  */
  32 #define MV_CREATE_ERROR (0x0A)  /* Fail while creating an item           */
  33 #define MV_NOT_FOUND    (0x0B)  /* Item not found                        */
  34 #define MV_NO_MORE      (0x0C)  /* No more items found                   */
  35 #define MV_NO_SUCH      (0x0D)  /* No such item                          */
  36 #define MV_TIMEOUT      (0x0E)  /* Time Out                              */
  37 #define MV_NO_CHANGE    (0x0F)  /* Parameter(s) is already in this value */
  38 #define MV_NOT_SUPPORTED (0x10) /* This request is not support           */
  39 #define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented*/
  40 #define MV_NOT_INITIALIZED (0x12) /* The item is not initialized          */
  41 #define MV_NO_RESOURCE  (0x13)  /* Resource not available (memory ...)   */
  42 #define MV_FULL         (0x14)  /* Item is full (Queue or table etc...)  */
  43 #define MV_EMPTY        (0x15)  /* Item is empty (Queue or table etc...) */
  44 #define MV_INIT_ERROR   (0x16)  /* Error occured while INIT process      */
  45 #define MV_HW_ERROR     (0x17)  /* Hardware error                        */
  46 #define MV_TX_ERROR     (0x18)  /* Transmit operation not succeeded      */
  47 #define MV_RX_ERROR     (0x19)  /* Recieve operation not succeeded       */
  48 #define MV_NOT_READY    (0x1A)  /* The other side is not ready yet       */
  49 #define MV_ALREADY_EXIST (0x1B) /* Tried to create existing item         */
  50 #define MV_OUT_OF_CPU_MEM   (0x1C) /* Cpu memory allocation failed.      */
  51 #define MV_NOT_STARTED  (0x1D)  /* Not started yet                       */
  52 #define MV_BUSY         (0x1E)  /* Item is busy.                         */
  53 #define MV_TERMINATE    (0x1F)  /* Item terminates it's work.            */
  54 #define MV_NOT_ALIGNED  (0x20)  /* Wrong alignment                       */
  55 #define MV_NOT_ALLOWED  (0x21)  /* Operation NOT allowed                 */
  56 #define MV_WRITE_PROTECT (0x22) /* Write protected                       */
  57
  58 #define MV_INVALID      (int)(-1)
  59
  60 /*
  61  * Debug (Enable/Disable modules) and Error report
  62  */
  63
  64 #ifdef BASIC_DEBUG
  65 #define MV_DEBUG_WL
  66 #define MV_DEBUG_RL
  67 #define MV_DEBUG_DQS_RESULTS
  68 #endif
  69
  70 #ifdef FULL_DEBUG
  71 #define MV_DEBUG_WL
  72 #define MV_DEBUG_RL
  73 #define MV_DEBUG_DQS
  74
  75 #define MV_DEBUG_PBS
  76 #define MV_DEBUG_DFS
  77 #define MV_DEBUG_MAIN_FULL
  78 #define MV_DEBUG_DFS_FULL
  79 #define MV_DEBUG_DQS_FULL
  80 #define MV_DEBUG_RL_FULL
  81 #define MV_DEBUG_WL_FULL
  82 #endif
  83
  84 /*
  85  * General Consts
  86  */
  87
  88 #define SDRAM_READ_WRITE_LEN_IN_WORDS           16
  89 #define SDRAM_READ_WRITE_LEN_IN_DOUBLE_WORDS    8
  90 #define CACHE_LINE_SIZE                         0x20
  91
  92 #define SDRAM_CS_BASE                           0x0
  93
  94 #define SRAM_BASE                               0x40000000
  95 #define SRAM_SIZE                               0xFFF
  96
  97 #define LEN_64BIT_STD_PATTERN                   16
  98 #define LEN_64BIT_KILLER_PATTERN                128
  99 #define LEN_64BIT_SPECIAL_PATTERN               128
 100 #define LEN_64BIT_PBS_PATTERN                   16
 101 #define LEN_WL_SUP_PATTERN                              32
 102
 103 #define LEN_16BIT_STD_PATTERN                   4
 104 #define LEN_16BIT_KILLER_PATTERN                128
 105 #define LEN_16BIT_SPECIAL_PATTERN               128
 106 #define LEN_16BIT_PBS_PATTERN                   4
 107
 108 #define CMP_BYTE_SHIFT                          8
 109 #define CMP_BYTE_MASK                           0xFF
 110 #define PUP_SIZE                                8
 111
 112 #define S 0
 113 #define C 1
 114 #define P 2
 115 #define D 3
 116 #define DQS 6
 117 #define PS 2
 118 #define DS 3
 119 #define PE 4
 120 #define DE 5
 121
 122 #define CS0                                     0
 123 #define MAX_DIMM_NUM                            2
 124 #define MAX_DELAY                               0x1F
 125
 126 /*
 127  * Invertion limit and phase1 limit are WA for the RL @ 1:1 design bug -
 128  * Armada 370 & AXP Z1
 129  */
 130 #define MAX_DELAY_INV_LIMIT                     0x5
 131 #define MIN_DELAY_PHASE_1_LIMIT                 0x10
 132
 133 #define MAX_DELAY_INV                           (0x3F - MAX_DELAY_INV_LIMIT)
 134 #define MIN_DELAY                               0
 135 #define MAX_PUP_NUM                             9
 136 #define ECC_PUP                                 8
 137 #define DQ_NUM                                  8
 138 #define DQS_DQ_NUM                              8
 139 #define INIT_WL_DELAY                           13
 140 #define INIT_RL_DELAY                           15
 141 #define TWLMRD_DELAY                            20
 142 #define TCLK_3_DELAY                            3
 143 #define ECC_BIT                                 8
 144 #define DMA_SIZE                                64
 145 #define MV_DMA_0                                0
 146 #define MAX_TRAINING_RETRY                      10
 147
 148 #define PUP_RL_MODE                             0x2
 149 #define PUP_WL_MODE                             0
 150 #define PUP_PBS_TX                              0x10
 151 #define PUP_PBS_TX_DM                           0x1A
 152 #define PUP_PBS_RX                              0x30
 153 #define PUP_DQS_WR                              0x1
 154 #define PUP_DQS_RD                              0x3
 155 #define PUP_BC                                  10
 156 #define PUP_DELAY_MASK                          0x1F
 157 #define PUP_PHASE_MASK                          0x7
 158 #define PUP_NUM_64BIT                           8
 159 #define PUP_NUM_32BIT                           4
 160 #define PUP_NUM_16BIT                           2
 161
 162 /* control PHY registers */
 163 #define CNTRL_PUP_DESKEW                        0x10
 164
 165 /* WL */
 166 #define COUNT_WL_HI_FREQ                        2
 167 #define COUNT_WL                                2
 168 #define COUNT_WL_RFRS                           9
 169 #define WL_HI_FREQ_SHIFT                        2
 170 #define WL_HI_FREQ_STATE                        1
 171 #define COUNT_HW_WL                             2
 172
 173 /* RL */
 174 /*
 175  * RL_MODE - this define uses the RL mode SW RL instead of the functional
 176  * window SW RL
 177  */
 178 #define RL_MODE
 179 #define RL_WINDOW_WA
 180 #define MAX_PHASE_1TO1                          2
 181 #define MAX_PHASE_2TO1                          4
 182
 183 #define MAX_PHASE_RL_UL_1TO1                    0
 184 #define MAX_PHASE_RL_L_1TO1                     4
 185 #define MAX_PHASE_RL_UL_2TO1                    3
 186 #define MAX_PHASE_RL_L_2TO1                     7
 187
 188 #define RL_UNLOCK_STATE                         0
 189 #define RL_WINDOW_STATE                         1
 190 #define RL_FINAL_STATE                          2
 191 #define RL_RETRY_COUNT                          2
 192 #define COUNT_HW_RL                             2
 193
 194 /* PBS */
 195 #define MAX_PBS                                 31
 196 #define MIN_PBS                                 0
 197 #define COUNT_PBS_PATTERN                       2
 198 #define COUNT_PBS_STARTOVER                     2
 199 #define COUNT_PBS_REPEAT                        3
 200 #define COUNT_PBS_COMP_RETRY_NUM                2
 201 #define PBS_DIFF_LIMIT                          31
 202 #define PATTERN_PBS_TX_A                        0x55555555
 203 #define PATTERN_PBS_TX_B                        0xAAAAAAAA
 204
 205 /* DQS */
 206 #define ADLL_ERROR                              0x55
 207 #define ADLL_MAX                                31
 208 #define ADLL_MIN                                0
 209 #define MIN_WIN_SIZE                            4
 210 #define VALID_WIN_THRS                          MIN_WIN_SIZE
 211
 212 #define MODE_2TO1                               1
 213 #define MODE_1TO1                               0
 214
 215 /*
 216  * Macros
 217  */
 218 #define IS_PUP_ACTIVE(_data_, _pup_)        (((_data_) >> (_pup_)) & 0x1)
 219
 220 /*
 221  * Internal ERROR codes
 222  */
 223 #define MV_DDR3_TRAINING_ERR_WR_LVL_HW              0xDD302001
 224 #define MV_DDR3_TRAINING_ERR_LOAD_PATTERNS          0xDD302002
 225 #define MV_DDR3_TRAINING_ERR_WR_LVL_HI_FREQ         0xDD302003
 226 #define MV_DDR3_TRAINING_ERR_DFS_H2L                0xDD302004
 227 #define MV_DDR3_TRAINING_ERR_DRAM_COMPARE           0xDD302005
 228 #define MV_DDR3_TRAINING_ERR_WIN_LIMITS             0xDD302006
 229 #define MV_DDR3_TRAINING_ERR_PUP_RANGE              0xDD302025
 230 #define MV_DDR3_TRAINING_ERR_DQS_LOW_LIMIT_SEARCH   0xDD302007
 231 #define MV_DDR3_TRAINING_ERR_DQS_HIGH_LIMIT_SEARCH  0xDD302008
 232 #define MV_DDR3_TRAINING_ERR_DQS_PATTERN            0xDD302009
 233 #define MV_DDR3_TRAINING_ERR_PBS_ADLL_SHR_1PHASE    0xDD302010
 234 #define MV_DDR3_TRAINING_ERR_PBS_TX_MAX_VAL         0xDD302011
 235 #define MV_DDR3_TRAINING_ERR_PBS_RX_PER_BIT         0xDD302012
 236 #define MV_DDR3_TRAINING_ERR_PBS_TX_PER_BIT         0xDD302013
 237 #define MV_DDR3_TRAINING_ERR_PBS_RX_MAX_VAL         0xDD302014
 238 #define MV_DDR3_TRAINING_ERR_PBS_SHIFT_QDS_SRAM_CMP 0xDD302015
 239 #define MV_DDR3_TRAINING_ERR_PBS_SHIFT_QDS_MAX_VAL  0xDD302016
 240 #define MV_DDR3_TRAINING_ERR_RD_LVL_RL_PATTERN      0xDD302017
 241 #define MV_DDR3_TRAINING_ERR_RD_LVL_RL_PUP_UNLOCK   0xDD302018
 242 #define MV_DDR3_TRAINING_ERR_RD_LVL_PUP_UNLOCK      0xDD302019
 243 #define MV_DDR3_TRAINING_ERR_WR_LVL_SW              0xDD302020
 244 #define MV_DDR3_TRAINING_ERR_PRBS_RX                0xDD302021
 245 #define MV_DDR3_TRAINING_ERR_DQS_RX                 0xDD302022
 246 #define MV_DDR3_TRAINING_ERR_PRBS_TX                0xDD302023
 247 #define MV_DDR3_TRAINING_ERR_DQS_TX                 0xDD302024
 248
 249 /*
 250  * DRAM information structure
 251  */
 252 typedef struct dram_info {
 253         u32 num_cs;
 254         u32 cs_ena;
 255         u32 num_of_std_pups;    /* Q value = ddrWidth/8 - Without ECC!! */
 256         u32 num_of_total_pups;  /* numOfStdPups + eccEna */
 257         u32 target_frequency;   /* DDR Frequency */
 258         u32 ddr_width;          /* 32/64 Bit or 16/32 Bit */
 259         u32 ecc_ena;            /* 0/1 */
 260         u32 wl_val[MAX_CS][MAX_PUP_NUM][7];
 261         u32 rl_val[MAX_CS][MAX_PUP_NUM][7];
 262         u32 rl_max_phase;
 263         u32 rl_min_phase;
 264         u32 wl_max_phase;
 265         u32 wl_min_phase;
 266         u32 rd_smpl_dly;
 267         u32 rd_rdy_dly;
 268         u32 cl;
 269         u32 cwl;
 270         u32 mode_2t;
 271         int rl400_bug;
 272         int multi_cs_mr_support;
 273         int reg_dimm;
 274 } MV_DRAM_INFO;
 275
 276 enum training_modes  {
 277         DQS_WR_MODE,
 278         WL_MODE_,
 279         RL_MODE_,
 280         DQS_RD_MODE,
 281         PBS_TX_DM_MODE,
 282         PBS_TX_MODE,
 283         PBS_RX_MODE,
 284         MAX_TRAINING_MODE,
 285 };
 286
 287 typedef struct dram_training_init {
 288         u32 reg_addr;
 289         u32 reg_value;
 290 } MV_DRAM_TRAINING_INIT;
 291
 292 typedef struct dram_mv_init {
 293         u32 reg_addr;
 294         u32 reg_value;
 295 } MV_DRAM_MC_INIT;
 296
 297 /* Board/Soc revisions define */
 298 enum board_rev {
 299         Z1,
 300         Z1_PCAC,
 301         Z1_RD_SLED,
 302         A0,
 303         A0_AMC
 304 };
 305
 306 typedef struct dram_modes {
 307         char *mode_name;
 308         u8 cpu_freq;
 309         u8 fab_freq;
 310         u8 chip_id;
 311         int chip_board_rev;
 312         MV_DRAM_MC_INIT *regs;
 313         MV_DRAM_TRAINING_INIT *vals;
 314 } MV_DRAM_MODES;
 315
 316 /*
 317  * Function Declarations
 318  */
 319
 320 u32 cache_inv(u32 addr);
 321 void flush_l1_v7(u32 line);
 322 void flush_l1_v6(u32 line);
 323
 324 u32 ddr3_cl_to_valid_cl(u32 cl);
 325 u32 ddr3_valid_cl_to_cl(u32 ui_valid_cl);
 326
 327 void ddr3_write_pup_reg(u32 mode, u32 cs, u32 pup, u32 phase, u32 delay);
 328 u32 ddr3_read_pup_reg(u32 mode, u32 cs, u32 pup);
 329
 330 int ddr3_sdram_pbs_compare(MV_DRAM_INFO *dram_info, u32 pup_locked, int is_tx,
 331                            u32 pbs_pattern_idx, u32 pbs_curr_val,
 332                            u32 pbs_lock_val, u32 *skew_array,
 333                            u8 *unlock_pup_dq_array, u32 ecc);
 334
 335 int ddr3_sdram_dqs_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
 336                            u32 *new_locked_pup, u32 *pattern,
 337                            u32 pattern_len, u32 sdram_offset, int write,
 338                            int mask, u32 *mask_pattern, int b_special_compare);
 339
 340 int ddr3_sdram_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
 341                        u32 *new_locked_pup, u32 *pattern, u32 pattern_len,
 342                        u32 sdram_offset, int write, int mask,
 343                        u32 *mask_pattern, int b_special_compare);
 344
 345 int ddr3_sdram_direct_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
 346                               u32 *new_locked_pup, u32 *pattern,
 347                               u32 pattern_len, u32 sdram_offset, int write,
 348                               int mask, u32 *mask_pattern);
 349
 350 int ddr3_sdram_dm_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
 351                           u32 *new_locked_pup, u32 *pattern,
 352                           u32 sdram_offset);
 353 int ddr3_dram_sram_read(u32 src, u32 dst, u32 len);
 354 int ddr3_load_patterns(MV_DRAM_INFO *dram_info, int resume);
 355
 356 int ddr3_read_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info);
 357 int ddr3_read_leveling_sw(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info);
 358
 359 int ddr3_write_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info);
 360 int ddr3_write_leveling_sw(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info);
 361 int ddr3_write_leveling_hw_reg_dimm(u32 freq, MV_DRAM_INFO *dram_info);
 362 int ddr3_wl_supplement(MV_DRAM_INFO *dram_info);
 363
 364 int ddr3_dfs_high_2_low(u32 freq, MV_DRAM_INFO *dram_info);
 365 int ddr3_dfs_low_2_high(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info);
 366
 367 int ddr3_pbs_tx(MV_DRAM_INFO *dram_info);
 368 int ddr3_pbs_rx(MV_DRAM_INFO *dram_info);
 369 int ddr3_load_pbs_patterns(MV_DRAM_INFO *dram_info);
 370
 371 int ddr3_dqs_centralization_rx(MV_DRAM_INFO *dram_info);
 372 int ddr3_dqs_centralization_tx(MV_DRAM_INFO *dram_info);
 373 int ddr3_load_dqs_patterns(MV_DRAM_INFO *dram_info);
 374
 375 void ddr3_static_training_init(void);
 376
 377 u8 ddr3_get_eprom_fabric(void);
 378 void ddr3_set_performance_params(MV_DRAM_INFO *dram_info);
 379 int ddr3_dram_sram_burst(u32 src, u32 dst, u32 len);
 380 void ddr3_save_training(MV_DRAM_INFO *dram_info);
 381 int ddr3_read_training_results(void);
 382 int ddr3_training_suspend_resume(MV_DRAM_INFO *dram_info);
 383 int ddr3_get_min_max_read_sample_delay(u32 cs_enable, u32 reg, u32 *min,
 384                                        u32 *max, u32 *cs_max);
 385 int ddr3_get_min_max_rl_phase(MV_DRAM_INFO *dram_info, u32 *min, u32 *max,
 386                               u32 cs);
 387 int ddr3_odt_activate(int activate);
 388 int ddr3_odt_read_dynamic_config(MV_DRAM_INFO *dram_info);
 389 void ddr3_print_freq(u32 freq);
 390 void ddr3_reset_phy_read_fifo(void);
 391
 392 #endif /* __DDR3_TRAINING_H */