drivers/dma/fsl_dma.c

   1 /*
   2  * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
   3  * (C) Copyright 2002, 2003 Motorola Inc.
   4  * Xianghua Xiao (X.Xiao@motorola.com)
   5  *
   6  * (C) Copyright 2000
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <config.h>
  29 #include <common.h>
  30 #include <asm/io.h>
  31 #include <asm/fsl_dma.h>
  32
  33 /* Controller can only transfer 2^26 - 1 bytes at a time */
  34 #define FSL_DMA_MAX_SIZE        (0x3ffffff)
  35
  36 #if defined(CONFIG_MPC83xx)
  37 #define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_CTM_DIRECT | FSL_DMA_MR_DMSEN)
  38 #else
  39 #define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT)
  40 #endif
  41
  42
  43 #if defined(CONFIG_MPC83xx)
  44 dma83xx_t *dma_base = (void *)(CONFIG_SYS_MPC83xx_DMA_ADDR);
  45 #elif defined(CONFIG_MPC85xx)
  46 ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
  47 #elif defined(CONFIG_MPC86xx)
  48 ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
  49 #else
  50 #error "Freescale DMA engine not supported on your processor"
  51 #endif
  52
  53 static void dma_sync(void)
  54 {
  55 #if defined(CONFIG_MPC85xx)
  56         asm("sync; isync; msync");
  57 #elif defined(CONFIG_MPC86xx)
  58         asm("sync; isync");
  59 #endif
  60 }
  61
  62 static void out_dma32(volatile unsigned *addr, int val)
  63 {
  64 #if defined(CONFIG_MPC83xx)
  65         out_le32(addr, val);
  66 #else
  67         out_be32(addr, val);
  68 #endif
  69 }
  70
  71 static uint in_dma32(volatile unsigned *addr)
  72 {
  73 #if defined(CONFIG_MPC83xx)
  74         return in_le32(addr);
  75 #else
  76         return in_be32(addr);
  77 #endif
  78 }
  79
  80 static uint dma_check(void) {
  81         volatile fsl_dma_t *dma = &dma_base->dma[0];
  82         uint status;
  83
  84         /* While the channel is busy, spin */
  85         do {
  86                 status = in_dma32(&dma->sr);
  87         } while (status & FSL_DMA_SR_CB);
  88
  89         /* clear MR[CS] channel start bit */
  90         out_dma32(&dma->mr, in_dma32(&dma->mr) & ~FSL_DMA_MR_CS);
  91         dma_sync();
  92
  93         if (status != 0)
  94                 printf ("DMA Error: status = %x\n", status);
  95
  96         return status;
  97 }
  98
  99 #if !defined(CONFIG_MPC83xx)
 100 void dma_init(void) {
 101         volatile fsl_dma_t *dma = &dma_base->dma[0];
 102
 103         out_dma32(&dma->satr, FSL_DMA_SATR_SREAD_SNOOP);
 104         out_dma32(&dma->datr, FSL_DMA_DATR_DWRITE_SNOOP);
 105         out_dma32(&dma->sr, 0xffffffff); /* clear any errors */
 106         dma_sync();
 107 }
 108 #endif
 109
 110 int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) {
 111         volatile fsl_dma_t *dma = &dma_base->dma[0];
 112         uint xfer_size;
 113
 114         while (count) {
 115                 xfer_size = MIN(FSL_DMA_MAX_SIZE, count);
 116
 117                 out_dma32(&dma->dar, (u32) (dest & 0xFFFFFFFF));
 118                 out_dma32(&dma->sar, (u32) (src & 0xFFFFFFFF));
 119                 out_dma32(&dma->satr,
 120                         in_dma32(&dma->satr) | (u32)((u64)src >> 32));
 121                 out_dma32(&dma->datr,
 122                         in_dma32(&dma->datr) | (u32)((u64)dest >> 32));
 123                 out_dma32(&dma->bcr, xfer_size);
 124                 dma_sync();
 125
 126                 /* Prepare mode register */
 127                 out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT);
 128                 dma_sync();
 129
 130                 /* Start the transfer */
 131                 out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT | FSL_DMA_MR_CS);
 132
 133                 count -= xfer_size;
 134                 src += xfer_size;
 135                 dest += xfer_size;
 136
 137                 dma_sync();
 138
 139                 if (dma_check())
 140                         return -1;
 141         }
 142
 143         return 0;
 144 }
 145
 146 /*
 147  * 85xx/86xx use dma to initialize SDRAM when !CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 148  * while 83xx uses dma to initialize SDRAM when CONFIG_DDR_ECC_INIT_VIA_DMA
 149  */
 150 #if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) &&     \
 151         !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) ||         \
 152         (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)))
 153 void dma_meminit(uint val, uint size)
 154 {
 155         uint *p = 0;
 156         uint i = 0;
 157
 158         for (*p = 0; p < (uint *)(8 * 1024); p++) {
 159                 if (((uint)p & 0x1f) == 0)
 160                         ppcDcbz((ulong)p);
 161
 162                 *p = (uint)CONFIG_MEM_INIT_VALUE;
 163
 164                 if (((uint)p & 0x1c) == 0x1c)
 165                         ppcDcbf((ulong)p);
 166         }
 167
 168         dmacpy(0x002000, 0, 0x002000); /* 8K */
 169         dmacpy(0x004000, 0, 0x004000); /* 16K */
 170         dmacpy(0x008000, 0, 0x008000); /* 32K */
 171         dmacpy(0x010000, 0, 0x010000); /* 64K */
 172         dmacpy(0x020000, 0, 0x020000); /* 128K */
 173         dmacpy(0x040000, 0, 0x040000); /* 256K */
 174         dmacpy(0x080000, 0, 0x080000); /* 512K */
 175         dmacpy(0x100000, 0, 0x100000); /* 1M */
 176         dmacpy(0x200000, 0, 0x200000); /* 2M */
 177         dmacpy(0x400000, 0, 0x400000); /* 4M */
 178
 179         for (i = 1; i < size / 0x800000; i++)
 180                 dmacpy((0x800000 * i), 0, 0x800000);
 181 }
 182 #endif