3 * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
6 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
8 * SPDX-License-Identifier: GPL-2.0+
11 #include <common.h> /* core U-Boot definitions */
13 #include <ACEX1K.h> /* ACEX device family */
15 /* Define FPGA_DEBUG to get debug printf's */
17 #define PRINTF(fmt,args...) printf (fmt ,##args)
19 #define PRINTF(fmt,args...)
22 /* Note: The assumption is that we cannot possibly run fast enough to
23 * overrun the device (the Slave Parallel mode can free run at 50MHz).
24 * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
25 * the board config file to slow things down.
27 #ifndef CONFIG_FPGA_DELAY
28 #define CONFIG_FPGA_DELAY()
31 #ifndef CONFIG_SYS_FPGA_WAIT
32 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */
35 static int ACEX1K_ps_load(Altera_desc
*desc
, const void *buf
, size_t bsize
);
36 static int ACEX1K_ps_dump(Altera_desc
*desc
, const void *buf
, size_t bsize
);
37 /* static int ACEX1K_ps_info(Altera_desc *desc); */
39 /* ------------------------------------------------------------------------- */
40 /* ACEX1K Generic Implementation */
41 int ACEX1K_load(Altera_desc
*desc
, const void *buf
, size_t bsize
)
43 int ret_val
= FPGA_FAIL
;
45 switch (desc
->iface
) {
47 PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__
);
48 ret_val
= ACEX1K_ps_load (desc
, buf
, bsize
);
51 /* Add new interface types here */
54 printf ("%s: Unsupported interface type, %d\n",
55 __FUNCTION__
, desc
->iface
);
61 int ACEX1K_dump(Altera_desc
*desc
, const void *buf
, size_t bsize
)
63 int ret_val
= FPGA_FAIL
;
65 switch (desc
->iface
) {
67 PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__
);
68 ret_val
= ACEX1K_ps_dump (desc
, buf
, bsize
);
71 /* Add new interface types here */
74 printf ("%s: Unsupported interface type, %d\n",
75 __FUNCTION__
, desc
->iface
);
81 int ACEX1K_info( Altera_desc
*desc
)
87 /* ------------------------------------------------------------------------- */
88 /* ACEX1K Passive Serial Generic Implementation */
90 static int ACEX1K_ps_load(Altera_desc
*desc
, const void *buf
, size_t bsize
)
92 int ret_val
= FPGA_FAIL
; /* assume the worst */
93 Altera_ACEX1K_Passive_Serial_fns
*fn
= desc
->iface_fns
;
96 PRINTF ("%s: start with interface functions @ 0x%p\n",
100 size_t bytecount
= 0;
101 unsigned char *data
= (unsigned char *) buf
;
102 int cookie
= desc
->cookie
; /* make a local copy */
103 unsigned long ts
; /* timestamp */
105 PRINTF ("%s: Function Table:\n"
113 __FUNCTION__
, &fn
, fn
, fn
->config
, fn
->status
,
114 fn
->clk
, fn
->data
, fn
->done
);
115 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
116 printf ("Loading FPGA Device %d...", cookie
);
120 * Run the pre configuration function if there is one.
126 /* Establish the initial state */
127 (*fn
->config
) (true, true, cookie
); /* Assert nCONFIG */
129 udelay(2); /* T_cfg > 2us */
131 /* nSTATUS should be asserted now */
132 (*fn
->done
) (cookie
);
133 if ( !(*fn
->status
) (cookie
) ) {
134 puts ("** nSTATUS is not asserted.\n");
135 (*fn
->abort
) (cookie
);
139 (*fn
->config
) (false, true, cookie
); /* Deassert nCONFIG */
140 udelay(2); /* T_cf2st1 < 4us */
142 /* Wait for nSTATUS to be released (i.e. deasserted) */
143 ts
= get_timer (0); /* get current time */
145 CONFIG_FPGA_DELAY ();
146 if (get_timer (ts
) > CONFIG_SYS_FPGA_WAIT
) { /* check the time */
147 puts ("** Timeout waiting for STATUS to go high.\n");
148 (*fn
->abort
) (cookie
);
151 (*fn
->done
) (cookie
);
152 } while ((*fn
->status
) (cookie
));
154 /* Get ready for the burn */
155 CONFIG_FPGA_DELAY ();
158 while (bytecount
< bsize
) {
160 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
162 (*fn
->abort
) (cookie
);
166 /* Altera detects an error if INIT goes low (active)
167 while DONE is low (inactive) */
168 #if 0 /* not yet implemented */
169 if ((*fn
->done
) (cookie
) == 0 && (*fn
->init
) (cookie
)) {
170 puts ("** CRC error during FPGA load.\n");
171 (*fn
->abort
) (cookie
);
175 val
= data
[bytecount
++ ];
178 /* Deassert the clock */
179 (*fn
->clk
) (false, true, cookie
);
180 CONFIG_FPGA_DELAY ();
182 (*fn
->data
) ((val
& 0x01), true, cookie
);
183 CONFIG_FPGA_DELAY ();
184 /* Assert the clock */
185 (*fn
->clk
) (true, true, cookie
);
186 CONFIG_FPGA_DELAY ();
191 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
192 if (bytecount
% (bsize
/ 40) == 0)
193 putc ('.'); /* let them know we are alive */
197 CONFIG_FPGA_DELAY ();
199 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
200 putc (' '); /* terminate the dotted line */
204 * Checking FPGA's CONF_DONE signal - correctly booted ?
207 if ( ! (*fn
->done
) (cookie
) ) {
208 puts ("** Booting failed! CONF_DONE is still deasserted.\n");
209 (*fn
->abort
) (cookie
);
214 * "DCLK must be clocked an additional 10 times fpr ACEX 1K..."
217 for (i
= 0; i
< 12; i
++) {
218 CONFIG_FPGA_DELAY ();
219 (*fn
->clk
) (true, true, cookie
); /* Assert the clock pin */
220 CONFIG_FPGA_DELAY ();
221 (*fn
->clk
) (false, true, cookie
); /* Deassert the clock pin */
224 ret_val
= FPGA_SUCCESS
;
226 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
227 if (ret_val
== FPGA_SUCCESS
) {
234 (*fn
->post
) (cookie
);
237 printf ("%s: NULL Interface function table!\n", __FUNCTION__
);
243 static int ACEX1K_ps_dump(Altera_desc
*desc
, const void *buf
, size_t bsize
)
245 /* Readback is only available through the Slave Parallel and */
246 /* boundary-scan interfaces. */
247 printf ("%s: Passive Serial Dumping is unavailable\n",