2 * Copyright (C) 2017 Intel Corporation <www.intel.com>
4 * SPDX-License-Identifier: GPL-2.0
8 #include <asm/arch/fpga_manager.h>
9 #include <asm/arch/reset_manager.h>
10 #include <asm/arch/system_manager.h>
11 #include <asm/arch/sdram.h>
12 #include <asm/arch/misc.h>
20 #define MIN_BITSTREAM_SIZECHECK 230
21 #define ENCRYPTION_OFFSET 69
22 #define COMPRESSION_OFFSET 229
23 #define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
24 #define FPGA_TIMEOUT_CNT 0x1000000
26 DECLARE_GLOBAL_DATA_PTR
;
28 static const struct socfpga_fpga_manager
*fpga_manager_base
=
29 (void *)SOCFPGA_FPGAMGRREGS_ADDRESS
;
31 static const struct socfpga_system_manager
*system_manager_base
=
32 (void *)SOCFPGA_SYSMGR_ADDRESS
;
34 static void fpgamgr_set_cd_ratio(unsigned long ratio
);
36 static uint32_t fpgamgr_get_msel(void)
40 reg
= readl(&fpga_manager_base
->imgcfg_stat
);
41 reg
= (reg
& ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD
) >>
42 ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB
;
47 static void fpgamgr_set_cfgwdth(int width
)
50 setbits_le32(&fpga_manager_base
->imgcfg_ctrl_02
,
51 ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK
);
53 clrbits_le32(&fpga_manager_base
->imgcfg_ctrl_02
,
54 ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK
);
57 int is_fpgamgr_user_mode(void)
59 return (readl(&fpga_manager_base
->imgcfg_stat
) &
60 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK
) != 0;
63 static int wait_for_user_mode(void)
65 return wait_for_bit(__func__
,
66 &fpga_manager_base
->imgcfg_stat
,
67 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK
,
68 1, FPGA_TIMEOUT_MSEC
, false);
71 static int is_fpgamgr_early_user_mode(void)
73 return (readl(&fpga_manager_base
->imgcfg_stat
) &
74 ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK
) != 0;
77 int fpgamgr_wait_early_user_mode(void)
79 u32 sync_data
= 0xffffffff;
81 unsigned start
= get_timer(0);
82 unsigned long cd_ratio
;
84 /* Getting existing CDRATIO */
85 cd_ratio
= (readl(&fpga_manager_base
->imgcfg_ctrl_02
) &
86 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK
) >>
87 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB
;
89 /* Using CDRATIO_X1 for better compatibility */
90 fpgamgr_set_cd_ratio(CDRATIO_x1
);
92 while (!is_fpgamgr_early_user_mode()) {
93 if (get_timer(start
) > FPGA_TIMEOUT_MSEC
)
95 fpgamgr_program_write((const long unsigned int *)&sync_data
,
97 udelay(FPGA_TIMEOUT_MSEC
);
101 debug("Additional %i sync word needed\n", i
);
103 /* restoring original CDRATIO */
104 fpgamgr_set_cd_ratio(cd_ratio
);
109 /* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
110 static int wait_for_nconfig_pin_and_nstatus_pin(void)
112 unsigned long mask
= ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK
|
113 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK
;
115 /* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted,
118 return wait_for_bit(__func__
,
119 &fpga_manager_base
->imgcfg_stat
,
121 false, FPGA_TIMEOUT_MSEC
, false);
124 static int wait_for_f2s_nstatus_pin(unsigned long value
)
126 /* Poll until f2s to specific value, timeout at 1000ms */
127 return wait_for_bit(__func__
,
128 &fpga_manager_base
->imgcfg_stat
,
129 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK
,
130 value
, FPGA_TIMEOUT_MSEC
, false);
134 static void fpgamgr_set_cd_ratio(unsigned long ratio
)
136 clrbits_le32(&fpga_manager_base
->imgcfg_ctrl_02
,
137 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK
);
139 setbits_le32(&fpga_manager_base
->imgcfg_ctrl_02
,
140 (ratio
<< ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB
) &
141 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK
);
144 /* get the MSEL value, verify we are set for FPP configuration mode */
145 static int fpgamgr_verify_msel(void)
147 u32 msel
= fpgamgr_get_msel();
149 if (msel
& ~BIT(0)) {
150 printf("Fail: read msel=%d\n", msel
);
158 * Write cdratio and cdwidth based on whether the bitstream is compressed
161 static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width
, u32
*rbf_data
,
164 unsigned int cd_ratio
;
165 bool encrypt
, compress
;
168 * According to the bitstream specification,
169 * both encryption and compression status are
170 * in location before offset 230 of the buffer.
172 if (rbf_size
< MIN_BITSTREAM_SIZECHECK
)
175 encrypt
= (rbf_data
[ENCRYPTION_OFFSET
] >> 2) & 3;
176 encrypt
= encrypt
!= 0;
178 compress
= (rbf_data
[COMPRESSION_OFFSET
] >> 1) & 1;
179 compress
= !compress
;
181 debug("header word %d = %08x\n", 69, rbf_data
[69]);
182 debug("header word %d = %08x\n", 229, rbf_data
[229]);
183 debug("read from rbf header: encrypt=%d compress=%d\n", encrypt
, compress
);
186 * from the register map description of cdratio in imgcfg_ctrl_02:
187 * Normal Configuration : 32bit Passive Parallel
188 * Partial Reconfiguration : 16bit Passive Parallel
192 * cd ratio is dependent on cfg width and whether the bitstream
193 * is encrypted and/or compressed.
195 * | width | encr. | compr. | cd ratio |
205 if (!compress
&& !encrypt
) {
206 cd_ratio
= CDRATIO_x1
;
209 cd_ratio
= CDRATIO_x4
;
211 cd_ratio
= CDRATIO_x2
;
213 /* if 32 bit, double the cd ratio (so register
214 field setting is incremented) */
215 if (cfg_width
== CFGWDTH_32
)
219 fpgamgr_set_cfgwdth(cfg_width
);
220 fpgamgr_set_cd_ratio(cd_ratio
);
225 static int fpgamgr_reset(void)
229 /* S2F_NCONFIG = 0 */
230 clrbits_le32(&fpga_manager_base
->imgcfg_ctrl_00
,
231 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK
);
233 /* Wait for f2s_nstatus == 0 */
234 if (wait_for_f2s_nstatus_pin(0))
237 /* S2F_NCONFIG = 1 */
238 setbits_le32(&fpga_manager_base
->imgcfg_ctrl_00
,
239 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK
);
241 /* Wait for f2s_nstatus == 1 */
242 if (wait_for_f2s_nstatus_pin(1))
245 /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
246 reg
= readl(&fpga_manager_base
->imgcfg_stat
);
247 if ((reg
& ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK
) != 0)
250 if ((reg
& ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK
) == 0)
256 /* Start the FPGA programming by initialize the FPGA Manager */
257 int fpgamgr_program_init(u32
* rbf_data
, size_t rbf_size
)
262 if (fpgamgr_verify_msel())
266 if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32
, rbf_data
, rbf_size
))
271 * Make sure no other external devices are trying to interfere with
274 if (wait_for_nconfig_pin_and_nstatus_pin())
279 * Deassert the signal drives from HPS
289 setbits_le32(&fpga_manager_base
->imgcfg_ctrl_01
,
290 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK
);
292 clrbits_le32(&fpga_manager_base
->imgcfg_ctrl_01
,
293 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK
);
295 clrbits_le32(&fpga_manager_base
->imgcfg_ctrl_02
,
296 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK
|
297 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK
);
299 setbits_le32(&fpga_manager_base
->imgcfg_ctrl_00
,
300 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK
);
302 clrbits_le32(&fpga_manager_base
->imgcfg_ctrl_00
,
303 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK
|
304 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK
);
309 * S2F_NENABLE_CONFIG = 0
310 * S2F_NENABLE_NCONFIG = 0
312 clrbits_le32(&fpga_manager_base
->imgcfg_ctrl_01
,
313 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK
);
314 clrbits_le32(&fpga_manager_base
->imgcfg_ctrl_00
,
315 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK
);
318 * Disable driving signals that HPS doesn't need to drive.
319 * S2F_NENABLE_NSTATUS = 1
320 * S2F_NENABLE_CONDONE = 1
322 setbits_le32(&fpga_manager_base
->imgcfg_ctrl_00
,
323 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK
|
324 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK
);
328 * Drive chip select S2F_NCE = 0
330 clrbits_le32(&fpga_manager_base
->imgcfg_ctrl_01
,
331 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK
);
334 if (wait_for_nconfig_pin_and_nstatus_pin())
338 ret
= fpgamgr_reset();
345 * EN_CFG_CTRL and EN_CFG_DATA = 1
347 setbits_le32(&fpga_manager_base
->imgcfg_ctrl_02
,
348 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK
|
349 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK
);
354 /* Ensure the FPGA entering config done */
355 static int fpgamgr_program_poll_cd(void)
357 unsigned long reg
, i
;
359 for (i
= 0; i
< FPGA_TIMEOUT_CNT
; i
++) {
360 reg
= readl(&fpga_manager_base
->imgcfg_stat
);
361 if (reg
& ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK
)
364 if ((reg
& ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK
) == 0) {
365 printf("nstatus == 0 while waiting for condone\n");
370 if (i
== FPGA_TIMEOUT_CNT
)
376 /* Ensure the FPGA entering user mode */
377 static int fpgamgr_program_poll_usermode(void)
382 if (fpgamgr_dclkcnt_set(0xf))
385 ret
= wait_for_user_mode();
387 printf("%s: Failed to enter user mode with ", __func__
);
388 printf("error code %d\n", ret
);
394 * Stop DATA path and Dclk
395 * EN_CFG_CTRL and EN_CFG_DATA = 0
397 clrbits_le32(&fpga_manager_base
->imgcfg_ctrl_02
,
398 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK
|
399 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK
);
404 * S2F_NENABLE_CONFIG = 1
405 * S2F_NENABLE_NCONFIG = 1
407 setbits_le32(&fpga_manager_base
->imgcfg_ctrl_01
,
408 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK
);
409 setbits_le32(&fpga_manager_base
->imgcfg_ctrl_00
,
410 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK
);
412 /* Disable chip select S2F_NCE = 1 */
413 setbits_le32(&fpga_manager_base
->imgcfg_ctrl_01
,
414 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK
);
420 reg
= readl(&fpga_manager_base
->imgcfg_stat
);
421 if (((reg
& ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK
) !=
422 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK
) ||
423 ((reg
& ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK
) !=
424 ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK
) ||
425 ((reg
& ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK
) !=
426 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK
))
432 int fpgamgr_program_finish(void)
434 /* Ensure the FPGA entering config done */
435 int status
= fpgamgr_program_poll_cd();
438 printf("FPGA: Poll CD failed with error code %d\n", status
);
443 /* Ensure the FPGA entering user mode */
444 status
= fpgamgr_program_poll_usermode();
446 printf("FPGA: Poll usermode failed with error code %d\n",
451 printf("Full Configuration Succeeded.\n");
457 * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
458 * Return 0 for sucess, non-zero for error.
460 int socfpga_load(Altera_desc
*desc
, const void *rbf_data
, size_t rbf_size
)
462 unsigned long status
;
464 /* disable all signals from hps peripheral controller to fpga */
465 writel(0, &system_manager_base
->fpgaintf_en_global
);
467 /* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
468 socfpga_bridges_reset();
470 /* Initialize the FPGA Manager */
471 status
= fpgamgr_program_init((u32
*)rbf_data
, rbf_size
);
475 /* Write the RBF data to FPGA Manager */
476 fpgamgr_program_write(rbf_data
, rbf_size
);
478 return fpgamgr_program_finish();