drivers/gpio/tegra_gpio.c

   1 /*
   2  * NVIDIA Tegra20 GPIO handling.
   3  *  (C) Copyright 2010-2012,2015
   4  *  NVIDIA Corporation <www.nvidia.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /*
  10  * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver.
  11  * Tom Warren (twarren@nvidia.com)
  12  */
  13
  14 #include <common.h>
  15 #include <dm.h>
  16 #include <malloc.h>
  17 #include <errno.h>
  18 #include <fdtdec.h>
  19 #include <asm/io.h>
  20 #include <asm/bitops.h>
  21 #include <asm/arch/tegra.h>
  22 #include <asm/gpio.h>
  23 #include <dm/device-internal.h>
  24 #include <dt-bindings/gpio/gpio.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 static const int CONFIG_SFIO = 0;
  29 static const int CONFIG_GPIO = 1;
  30 static const int DIRECTION_INPUT = 0;
  31 static const int DIRECTION_OUTPUT = 1;
  32
  33 struct tegra_gpio_platdata {
  34         struct gpio_ctlr_bank *bank;
  35         const char *port_name;  /* Name of port, e.g. "B" */
  36         int base_gpio;          /* Port number for this port (0, 1,.., n-1) */
  37 };
  38
  39 /* Information about each port at run-time */
  40 struct tegra_port_info {
  41         struct gpio_ctlr_bank *bank;
  42         int base_gpio;          /* Port number for this port (0, 1,.., n-1) */
  43 };
  44
  45 /* Return config of pin 'gpio' as GPIO (1) or SFIO (0) */
  46 static int get_config(unsigned gpio)
  47 {
  48         struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
  49         struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
  50         u32 u;
  51         int type;
  52
  53         u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
  54         type = (u >> GPIO_BIT(gpio)) & 1;
  55
  56         debug("get_config: port = %d, bit = %d is %s\n",
  57                 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
  58
  59         return type ? CONFIG_GPIO : CONFIG_SFIO;
  60 }
  61
  62 /* Config pin 'gpio' as GPIO or SFIO, based on 'type' */
  63 static void set_config(unsigned gpio, int type)
  64 {
  65         struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
  66         struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
  67         u32 u;
  68
  69         debug("set_config: port = %d, bit = %d, %s\n",
  70                 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
  71
  72         u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
  73         if (type != CONFIG_SFIO)
  74                 u |= 1 << GPIO_BIT(gpio);
  75         else
  76                 u &= ~(1 << GPIO_BIT(gpio));
  77         writel(u, &bank->gpio_config[GPIO_PORT(gpio)]);
  78 }
  79
  80 /* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
  81 static int get_direction(unsigned gpio)
  82 {
  83         struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
  84         struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
  85         u32 u;
  86         int dir;
  87
  88         u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
  89         dir =  (u >> GPIO_BIT(gpio)) & 1;
  90
  91         debug("get_direction: port = %d, bit = %d, %s\n",
  92                 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN");
  93
  94         return dir ? DIRECTION_OUTPUT : DIRECTION_INPUT;
  95 }
  96
  97 /* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
  98 static void set_direction(unsigned gpio, int output)
  99 {
 100         struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
 101         struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
 102         u32 u;
 103
 104         debug("set_direction: port = %d, bit = %d, %s\n",
 105                 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN");
 106
 107         u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
 108         if (output != DIRECTION_INPUT)
 109                 u |= 1 << GPIO_BIT(gpio);
 110         else
 111                 u &= ~(1 << GPIO_BIT(gpio));
 112         writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]);
 113 }
 114
 115 /* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
 116 static void set_level(unsigned gpio, int high)
 117 {
 118         struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
 119         struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
 120         u32 u;
 121
 122         debug("set_level: port = %d, bit %d == %d\n",
 123                 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high);
 124
 125         u = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
 126         if (high)
 127                 u |= 1 << GPIO_BIT(gpio);
 128         else
 129                 u &= ~(1 << GPIO_BIT(gpio));
 130         writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
 131 }
 132
 133 /*
 134  * Generic_GPIO primitives.
 135  */
 136
 137 /* set GPIO pin 'gpio' as an input */
 138 static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset)
 139 {
 140         struct tegra_port_info *state = dev_get_priv(dev);
 141
 142         /* Configure GPIO direction as input. */
 143         set_direction(state->base_gpio + offset, DIRECTION_INPUT);
 144
 145         /* Enable the pin as a GPIO */
 146         set_config(state->base_gpio + offset, 1);
 147
 148         return 0;
 149 }
 150
 151 /* set GPIO pin 'gpio' as an output, with polarity 'value' */
 152 static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset,
 153                                        int value)
 154 {
 155         struct tegra_port_info *state = dev_get_priv(dev);
 156         int gpio = state->base_gpio + offset;
 157
 158         /* Configure GPIO output value. */
 159         set_level(gpio, value);
 160
 161         /* Configure GPIO direction as output. */
 162         set_direction(gpio, DIRECTION_OUTPUT);
 163
 164         /* Enable the pin as a GPIO */
 165         set_config(state->base_gpio + offset, 1);
 166
 167         return 0;
 168 }
 169
 170 /* read GPIO IN value of pin 'gpio' */
 171 static int tegra_gpio_get_value(struct udevice *dev, unsigned offset)
 172 {
 173         struct tegra_port_info *state = dev_get_priv(dev);
 174         int gpio = state->base_gpio + offset;
 175         int val;
 176
 177         debug("%s: pin = %d (port %d:bit %d)\n", __func__,
 178               gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
 179
 180         if (get_direction(gpio) == DIRECTION_INPUT)
 181                 val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]);
 182         else
 183                 val = readl(&state->bank->gpio_out[GPIO_PORT(gpio)]);
 184
 185         return (val >> GPIO_BIT(gpio)) & 1;
 186 }
 187
 188 /* write GPIO OUT value to pin 'gpio' */
 189 static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value)
 190 {
 191         struct tegra_port_info *state = dev_get_priv(dev);
 192         int gpio = state->base_gpio + offset;
 193
 194         debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
 195               gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value);
 196
 197         /* Configure GPIO output value. */
 198         set_level(gpio, value);
 199
 200         return 0;
 201 }
 202
 203 void gpio_config_table(const struct tegra_gpio_config *config, int len)
 204 {
 205         int i;
 206
 207         for (i = 0; i < len; i++) {
 208                 switch (config[i].init) {
 209                 case TEGRA_GPIO_INIT_IN:
 210                         set_direction(config[i].gpio, DIRECTION_INPUT);
 211                         break;
 212                 case TEGRA_GPIO_INIT_OUT0:
 213                         set_level(config[i].gpio, 0);
 214                         set_direction(config[i].gpio, DIRECTION_OUTPUT);
 215                         break;
 216                 case TEGRA_GPIO_INIT_OUT1:
 217                         set_level(config[i].gpio, 1);
 218                         set_direction(config[i].gpio, DIRECTION_OUTPUT);
 219                         break;
 220                 }
 221                 set_config(config[i].gpio, CONFIG_GPIO);
 222         }
 223 }
 224
 225 static int tegra_gpio_get_function(struct udevice *dev, unsigned offset)
 226 {
 227         struct tegra_port_info *state = dev_get_priv(dev);
 228         int gpio = state->base_gpio + offset;
 229
 230         if (!get_config(gpio))
 231                 return GPIOF_FUNC;
 232         else if (get_direction(gpio))
 233                 return GPIOF_OUTPUT;
 234         else
 235                 return GPIOF_INPUT;
 236 }
 237
 238 static int tegra_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
 239                             struct fdtdec_phandle_args *args)
 240 {
 241         int gpio, port, ret;
 242
 243         gpio = args->args[0];
 244         port = gpio / TEGRA_GPIOS_PER_PORT;
 245         ret = device_get_child(dev, port, &desc->dev);
 246         if (ret)
 247                 return ret;
 248         desc->offset = gpio % TEGRA_GPIOS_PER_PORT;
 249         desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
 250
 251         return 0;
 252 }
 253
 254 static const struct dm_gpio_ops gpio_tegra_ops = {
 255         .direction_input        = tegra_gpio_direction_input,
 256         .direction_output       = tegra_gpio_direction_output,
 257         .get_value              = tegra_gpio_get_value,
 258         .set_value              = tegra_gpio_set_value,
 259         .get_function           = tegra_gpio_get_function,
 260         .xlate                  = tegra_gpio_xlate,
 261 };
 262
 263 /**
 264  * Returns the name of a GPIO port
 265  *
 266  * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ...
 267  *
 268  * @base_port: Base port number (0, 1..n-1)
 269  * @return allocated string containing the name
 270  */
 271 static char *gpio_port_name(int base_port)
 272 {
 273         char *name, *s;
 274
 275         name = malloc(3);
 276         if (name) {
 277                 s = name;
 278                 *s++ = 'A' + (base_port % 26);
 279                 if (base_port >= 26)
 280                         *s++ = *name;
 281                 *s = '\0';
 282         }
 283
 284         return name;
 285 }
 286
 287 static const struct udevice_id tegra_gpio_ids[] = {
 288         { .compatible = "nvidia,tegra30-gpio" },
 289         { .compatible = "nvidia,tegra20-gpio" },
 290         { }
 291 };
 292
 293 static int gpio_tegra_probe(struct udevice *dev)
 294 {
 295         struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 296         struct tegra_port_info *priv = dev->priv;
 297         struct tegra_gpio_platdata *plat = dev->platdata;
 298
 299         /* Only child devices have ports */
 300         if (!plat)
 301                 return 0;
 302
 303         priv->bank = plat->bank;
 304         priv->base_gpio = plat->base_gpio;
 305
 306         uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT;
 307         uc_priv->bank_name = plat->port_name;
 308
 309         return 0;
 310 }
 311
 312 /**
 313  * We have a top-level GPIO device with no actual GPIOs. It has a child
 314  * device for each Tegra port.
 315  */
 316 static int gpio_tegra_bind(struct udevice *parent)
 317 {
 318         struct tegra_gpio_platdata *plat = parent->platdata;
 319         struct gpio_ctlr *ctlr;
 320         int bank_count;
 321         int bank;
 322         int ret;
 323
 324         /* If this is a child device, there is nothing to do here */
 325         if (plat)
 326                 return 0;
 327
 328         /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
 329 #ifdef CONFIG_SPL_BUILD
 330         ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
 331         bank_count = TEGRA_GPIO_BANKS;
 332 #else
 333         {
 334         int len;
 335
 336         /*
 337          * This driver does not make use of interrupts, other than to figure
 338          * out the number of GPIO banks
 339          */
 340         if (!fdt_getprop(gd->fdt_blob, dev_of_offset(parent), "interrupts",
 341                          &len))
 342                 return -EINVAL;
 343         bank_count = len / 3 / sizeof(u32);
 344         ctlr = (struct gpio_ctlr *)dev_get_addr(parent);
 345         }
 346 #endif
 347         for (bank = 0; bank < bank_count; bank++) {
 348                 int port;
 349
 350                 for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) {
 351                         struct tegra_gpio_platdata *plat;
 352                         struct udevice *dev;
 353                         int base_port;
 354
 355                         plat = calloc(1, sizeof(*plat));
 356                         if (!plat)
 357                                 return -ENOMEM;
 358                         plat->bank = &ctlr->gpio_bank[bank];
 359                         base_port = bank * TEGRA_PORTS_PER_BANK + port;
 360                         plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port;
 361                         plat->port_name = gpio_port_name(base_port);
 362
 363                         ret = device_bind(parent, parent->driver,
 364                                           plat->port_name, plat, -1, &dev);
 365                         if (ret)
 366                                 return ret;
 367                         dev_set_of_offset(dev, dev_of_offset(parent));
 368                 }
 369         }
 370
 371         return 0;
 372 }
 373
 374 U_BOOT_DRIVER(gpio_tegra) = {
 375         .name   = "gpio_tegra",
 376         .id     = UCLASS_GPIO,
 377         .of_match = tegra_gpio_ids,
 378         .bind   = gpio_tegra_bind,
 379         .probe = gpio_tegra_probe,
 380         .priv_auto_alloc_size = sizeof(struct tegra_port_info),
 381         .ops    = &gpio_tegra_ops,
 382         .flags  = DM_FLAG_PRE_RELOC,
 383 };