3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
5 * SPDX-License-Identifier: GPL-2.0+
13 #include "designware_i2c.h"
15 struct dw_scl_sda_cfg
{
24 /* BayTrail HCNT/LCNT/SDA hold time */
25 static struct dw_scl_sda_cfg byt_config
= {
35 struct i2c_regs
*regs
;
36 struct dw_scl_sda_cfg
*scl_sda_cfg
;
39 static void dw_i2c_enable(struct i2c_regs
*i2c_base
, bool enable
)
41 u32 ena
= enable
? IC_ENABLE_0B
: 0;
45 writel(ena
, &i2c_base
->ic_enable
);
46 if ((readl(&i2c_base
->ic_enable_status
) & IC_ENABLE_0B
) == ena
)
50 * Wait 10 times the signaling period of the highest I2C
51 * transfer supported by the driver (for 400KHz this is
52 * 25us) as described in the DesignWare I2C databook.
57 printf("timeout in %sabling I2C adapter\n", enable
? "en" : "dis");
61 * i2c_set_bus_speed - Set the i2c speed
62 * @speed: required i2c speed
66 static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs
*i2c_base
,
67 struct dw_scl_sda_cfg
*scl_sda_cfg
,
71 unsigned int hcnt
, lcnt
;
74 if (speed
>= I2C_MAX_SPEED
)
75 i2c_spd
= IC_SPEED_MODE_MAX
;
76 else if (speed
>= I2C_FAST_SPEED
)
77 i2c_spd
= IC_SPEED_MODE_FAST
;
79 i2c_spd
= IC_SPEED_MODE_STANDARD
;
81 /* to set speed cltr must be disabled */
82 dw_i2c_enable(i2c_base
, false);
84 cntl
= (readl(&i2c_base
->ic_con
) & (~IC_CON_SPD_MSK
));
87 #ifndef CONFIG_X86 /* No High-speed for BayTrail yet */
88 case IC_SPEED_MODE_MAX
:
89 cntl
|= IC_CON_SPD_SS
;
91 hcnt
= scl_sda_cfg
->fs_hcnt
;
92 lcnt
= scl_sda_cfg
->fs_lcnt
;
94 hcnt
= (IC_CLK
* MIN_HS_SCL_HIGHTIME
) / NANO_TO_MICRO
;
95 lcnt
= (IC_CLK
* MIN_HS_SCL_LOWTIME
) / NANO_TO_MICRO
;
97 writel(hcnt
, &i2c_base
->ic_hs_scl_hcnt
);
98 writel(lcnt
, &i2c_base
->ic_hs_scl_lcnt
);
102 case IC_SPEED_MODE_STANDARD
:
103 cntl
|= IC_CON_SPD_SS
;
105 hcnt
= scl_sda_cfg
->ss_hcnt
;
106 lcnt
= scl_sda_cfg
->ss_lcnt
;
108 hcnt
= (IC_CLK
* MIN_SS_SCL_HIGHTIME
) / NANO_TO_MICRO
;
109 lcnt
= (IC_CLK
* MIN_SS_SCL_LOWTIME
) / NANO_TO_MICRO
;
111 writel(hcnt
, &i2c_base
->ic_ss_scl_hcnt
);
112 writel(lcnt
, &i2c_base
->ic_ss_scl_lcnt
);
115 case IC_SPEED_MODE_FAST
:
117 cntl
|= IC_CON_SPD_FS
;
119 hcnt
= scl_sda_cfg
->fs_hcnt
;
120 lcnt
= scl_sda_cfg
->fs_lcnt
;
122 hcnt
= (IC_CLK
* MIN_FS_SCL_HIGHTIME
) / NANO_TO_MICRO
;
123 lcnt
= (IC_CLK
* MIN_FS_SCL_LOWTIME
) / NANO_TO_MICRO
;
125 writel(hcnt
, &i2c_base
->ic_fs_scl_hcnt
);
126 writel(lcnt
, &i2c_base
->ic_fs_scl_lcnt
);
130 writel(cntl
, &i2c_base
->ic_con
);
132 /* Configure SDA Hold Time if required */
134 writel(scl_sda_cfg
->sda_hold
, &i2c_base
->ic_sda_hold
);
136 /* Enable back i2c now speed set */
137 dw_i2c_enable(i2c_base
, true);
143 * i2c_setaddress - Sets the target slave address
144 * @i2c_addr: target i2c address
146 * Sets the target slave address.
148 static void i2c_setaddress(struct i2c_regs
*i2c_base
, unsigned int i2c_addr
)
151 dw_i2c_enable(i2c_base
, false);
153 writel(i2c_addr
, &i2c_base
->ic_tar
);
156 dw_i2c_enable(i2c_base
, true);
160 * i2c_flush_rxfifo - Flushes the i2c RX FIFO
162 * Flushes the i2c RX FIFO
164 static void i2c_flush_rxfifo(struct i2c_regs
*i2c_base
)
166 while (readl(&i2c_base
->ic_status
) & IC_STATUS_RFNE
)
167 readl(&i2c_base
->ic_cmd_data
);
171 * i2c_wait_for_bb - Waits for bus busy
175 static int i2c_wait_for_bb(struct i2c_regs
*i2c_base
)
177 unsigned long start_time_bb
= get_timer(0);
179 while ((readl(&i2c_base
->ic_status
) & IC_STATUS_MA
) ||
180 !(readl(&i2c_base
->ic_status
) & IC_STATUS_TFE
)) {
182 /* Evaluate timeout */
183 if (get_timer(start_time_bb
) > (unsigned long)(I2C_BYTE_TO_BB
))
190 static int i2c_xfer_init(struct i2c_regs
*i2c_base
, uchar chip
, uint addr
,
193 if (i2c_wait_for_bb(i2c_base
))
196 i2c_setaddress(i2c_base
, chip
);
199 /* high byte address going out first */
200 writel((addr
>> (alen
* 8)) & 0xff,
201 &i2c_base
->ic_cmd_data
);
206 static int i2c_xfer_finish(struct i2c_regs
*i2c_base
)
208 ulong start_stop_det
= get_timer(0);
211 if ((readl(&i2c_base
->ic_raw_intr_stat
) & IC_STOP_DET
)) {
212 readl(&i2c_base
->ic_clr_stop_det
);
214 } else if (get_timer(start_stop_det
) > I2C_STOPDET_TO
) {
219 if (i2c_wait_for_bb(i2c_base
)) {
220 printf("Timed out waiting for bus\n");
224 i2c_flush_rxfifo(i2c_base
);
230 * i2c_read - Read from i2c memory
231 * @chip: target i2c address
232 * @addr: address to read from
234 * @buffer: buffer for read data
235 * @len: no of bytes to be read
237 * Read from i2c memory.
239 static int __dw_i2c_read(struct i2c_regs
*i2c_base
, u8 dev
, uint addr
,
240 int alen
, u8
*buffer
, int len
)
242 unsigned long start_time_rx
;
244 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
246 * EEPROM chips that implement "address overflow" are ones
247 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
248 * address and the extra bits end up in the "chip address"
249 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
250 * four 256 byte chips.
252 * Note that we consider the length of the address field to
253 * still be one byte because the extra address bits are
254 * hidden in the chip address.
256 dev
|= ((addr
>> (alen
* 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
);
257 addr
&= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
<< (alen
* 8));
259 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__
, dev
,
263 if (i2c_xfer_init(i2c_base
, dev
, addr
, alen
))
266 start_time_rx
= get_timer(0);
269 writel(IC_CMD
| IC_STOP
, &i2c_base
->ic_cmd_data
);
271 writel(IC_CMD
, &i2c_base
->ic_cmd_data
);
273 if (readl(&i2c_base
->ic_status
) & IC_STATUS_RFNE
) {
274 *buffer
++ = (uchar
)readl(&i2c_base
->ic_cmd_data
);
276 start_time_rx
= get_timer(0);
278 } else if (get_timer(start_time_rx
) > I2C_BYTE_TO
) {
283 return i2c_xfer_finish(i2c_base
);
287 * i2c_write - Write to i2c memory
288 * @chip: target i2c address
289 * @addr: address to read from
291 * @buffer: buffer for read data
292 * @len: no of bytes to be read
294 * Write to i2c memory.
296 static int __dw_i2c_write(struct i2c_regs
*i2c_base
, u8 dev
, uint addr
,
297 int alen
, u8
*buffer
, int len
)
300 unsigned long start_time_tx
;
302 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
304 * EEPROM chips that implement "address overflow" are ones
305 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
306 * address and the extra bits end up in the "chip address"
307 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
308 * four 256 byte chips.
310 * Note that we consider the length of the address field to
311 * still be one byte because the extra address bits are
312 * hidden in the chip address.
314 dev
|= ((addr
>> (alen
* 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
);
315 addr
&= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
<< (alen
* 8));
317 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__
, dev
,
321 if (i2c_xfer_init(i2c_base
, dev
, addr
, alen
))
324 start_time_tx
= get_timer(0);
326 if (readl(&i2c_base
->ic_status
) & IC_STATUS_TFNF
) {
328 writel(*buffer
| IC_STOP
,
329 &i2c_base
->ic_cmd_data
);
331 writel(*buffer
, &i2c_base
->ic_cmd_data
);
334 start_time_tx
= get_timer(0);
336 } else if (get_timer(start_time_tx
) > (nb
* I2C_BYTE_TO
)) {
337 printf("Timed out. i2c write Failed\n");
342 return i2c_xfer_finish(i2c_base
);
346 * __dw_i2c_init - Init function
347 * @speed: required i2c speed
348 * @slaveaddr: slave address for the device
350 * Initialization function.
352 static void __dw_i2c_init(struct i2c_regs
*i2c_base
, int speed
, int slaveaddr
)
355 dw_i2c_enable(i2c_base
, false);
357 writel((IC_CON_SD
| IC_CON_SPD_FS
| IC_CON_MM
), &i2c_base
->ic_con
);
358 writel(IC_RX_TL
, &i2c_base
->ic_rx_tl
);
359 writel(IC_TX_TL
, &i2c_base
->ic_tx_tl
);
360 writel(IC_STOP_DET
, &i2c_base
->ic_intr_mask
);
361 #ifndef CONFIG_DM_I2C
362 __dw_i2c_set_bus_speed(i2c_base
, NULL
, speed
);
363 writel(slaveaddr
, &i2c_base
->ic_sar
);
367 dw_i2c_enable(i2c_base
, true);
370 #ifndef CONFIG_DM_I2C
372 * The legacy I2C functions. These need to get removed once
373 * all users of this driver are converted to DM.
375 static struct i2c_regs
*i2c_get_base(struct i2c_adapter
*adap
)
377 switch (adap
->hwadapnr
) {
378 #if CONFIG_SYS_I2C_BUS_MAX >= 4
380 return (struct i2c_regs
*)CONFIG_SYS_I2C_BASE3
;
382 #if CONFIG_SYS_I2C_BUS_MAX >= 3
384 return (struct i2c_regs
*)CONFIG_SYS_I2C_BASE2
;
386 #if CONFIG_SYS_I2C_BUS_MAX >= 2
388 return (struct i2c_regs
*)CONFIG_SYS_I2C_BASE1
;
391 return (struct i2c_regs
*)CONFIG_SYS_I2C_BASE
;
393 printf("Wrong I2C-adapter number %d\n", adap
->hwadapnr
);
399 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter
*adap
,
403 return __dw_i2c_set_bus_speed(i2c_get_base(adap
), NULL
, speed
);
406 static void dw_i2c_init(struct i2c_adapter
*adap
, int speed
, int slaveaddr
)
408 __dw_i2c_init(i2c_get_base(adap
), speed
, slaveaddr
);
411 static int dw_i2c_read(struct i2c_adapter
*adap
, u8 dev
, uint addr
,
412 int alen
, u8
*buffer
, int len
)
414 return __dw_i2c_read(i2c_get_base(adap
), dev
, addr
, alen
, buffer
, len
);
417 static int dw_i2c_write(struct i2c_adapter
*adap
, u8 dev
, uint addr
,
418 int alen
, u8
*buffer
, int len
)
420 return __dw_i2c_write(i2c_get_base(adap
), dev
, addr
, alen
, buffer
, len
);
423 /* dw_i2c_probe - Probe the i2c chip */
424 static int dw_i2c_probe(struct i2c_adapter
*adap
, u8 dev
)
426 struct i2c_regs
*i2c_base
= i2c_get_base(adap
);
431 * Try to read the first location of the chip.
433 ret
= __dw_i2c_read(i2c_base
, dev
, 0, 1, (uchar
*)&tmp
, 1);
435 dw_i2c_init(adap
, adap
->speed
, adap
->slaveaddr
);
440 U_BOOT_I2C_ADAP_COMPLETE(dw_0
, dw_i2c_init
, dw_i2c_probe
, dw_i2c_read
,
441 dw_i2c_write
, dw_i2c_set_bus_speed
,
442 CONFIG_SYS_I2C_SPEED
, CONFIG_SYS_I2C_SLAVE
, 0)
444 #if CONFIG_SYS_I2C_BUS_MAX >= 2
445 U_BOOT_I2C_ADAP_COMPLETE(dw_1
, dw_i2c_init
, dw_i2c_probe
, dw_i2c_read
,
446 dw_i2c_write
, dw_i2c_set_bus_speed
,
447 CONFIG_SYS_I2C_SPEED1
, CONFIG_SYS_I2C_SLAVE1
, 1)
450 #if CONFIG_SYS_I2C_BUS_MAX >= 3
451 U_BOOT_I2C_ADAP_COMPLETE(dw_2
, dw_i2c_init
, dw_i2c_probe
, dw_i2c_read
,
452 dw_i2c_write
, dw_i2c_set_bus_speed
,
453 CONFIG_SYS_I2C_SPEED2
, CONFIG_SYS_I2C_SLAVE2
, 2)
456 #if CONFIG_SYS_I2C_BUS_MAX >= 4
457 U_BOOT_I2C_ADAP_COMPLETE(dw_3
, dw_i2c_init
, dw_i2c_probe
, dw_i2c_read
,
458 dw_i2c_write
, dw_i2c_set_bus_speed
,
459 CONFIG_SYS_I2C_SPEED3
, CONFIG_SYS_I2C_SLAVE3
, 3)
462 #else /* CONFIG_DM_I2C */
463 /* The DM I2C functions */
465 static int designware_i2c_xfer(struct udevice
*bus
, struct i2c_msg
*msg
,
468 struct dw_i2c
*i2c
= dev_get_priv(bus
);
471 debug("i2c_xfer: %d messages\n", nmsgs
);
472 for (; nmsgs
> 0; nmsgs
--, msg
++) {
473 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg
->addr
, msg
->len
);
474 if (msg
->flags
& I2C_M_RD
) {
475 ret
= __dw_i2c_read(i2c
->regs
, msg
->addr
, 0, 0,
478 ret
= __dw_i2c_write(i2c
->regs
, msg
->addr
, 0, 0,
482 debug("i2c_write: error sending\n");
490 static int designware_i2c_set_bus_speed(struct udevice
*bus
, unsigned int speed
)
492 struct dw_i2c
*i2c
= dev_get_priv(bus
);
494 return __dw_i2c_set_bus_speed(i2c
->regs
, i2c
->scl_sda_cfg
, speed
);
497 static int designware_i2c_probe_chip(struct udevice
*bus
, uint chip_addr
,
500 struct dw_i2c
*i2c
= dev_get_priv(bus
);
501 struct i2c_regs
*i2c_base
= i2c
->regs
;
505 /* Try to read the first location of the chip */
506 ret
= __dw_i2c_read(i2c_base
, chip_addr
, 0, 1, (uchar
*)&tmp
, 1);
508 __dw_i2c_init(i2c_base
, 0, 0);
513 static int designware_i2c_probe(struct udevice
*bus
)
515 struct dw_i2c
*priv
= dev_get_priv(bus
);
517 if (device_is_on_pci_bus(bus
)) {
519 /* Save base address from PCI BAR */
520 priv
->regs
= (struct i2c_regs
*)
521 dm_pci_map_bar(bus
, PCI_BASE_ADDRESS_0
, PCI_REGION_MEM
);
523 /* Use BayTrail specific timing values */
524 priv
->scl_sda_cfg
= &byt_config
;
528 priv
->regs
= (struct i2c_regs
*)dev_get_addr_ptr(bus
);
531 __dw_i2c_init(priv
->regs
, 0, 0);
536 static int designware_i2c_bind(struct udevice
*dev
)
538 static int num_cards
;
541 /* Create a unique device name for PCI type devices */
542 if (device_is_on_pci_bus(dev
)) {
545 * Setting req_seq in the driver is probably not recommended.
546 * But without a DT alias the number is not configured. And
547 * using this driver is impossible for PCIe I2C devices.
548 * This can be removed, once a better (correct) way for this
549 * is found and implemented.
551 dev
->req_seq
= num_cards
;
552 sprintf(name
, "i2c_designware#%u", num_cards
++);
553 device_set_name(dev
, name
);
559 static const struct dm_i2c_ops designware_i2c_ops
= {
560 .xfer
= designware_i2c_xfer
,
561 .probe_chip
= designware_i2c_probe_chip
,
562 .set_bus_speed
= designware_i2c_set_bus_speed
,
565 static const struct udevice_id designware_i2c_ids
[] = {
566 { .compatible
= "snps,designware-i2c" },
570 U_BOOT_DRIVER(i2c_designware
) = {
571 .name
= "i2c_designware",
573 .of_match
= designware_i2c_ids
,
574 .bind
= designware_i2c_bind
,
575 .probe
= designware_i2c_probe
,
576 .priv_auto_alloc_size
= sizeof(struct dw_i2c
),
577 .ops
= &designware_i2c_ops
,
581 static struct pci_device_id designware_pci_supported
[] = {
582 /* Intel BayTrail has 7 I2C controller located on the PCI bus */
583 { PCI_VDEVICE(INTEL
, 0x0f41) },
584 { PCI_VDEVICE(INTEL
, 0x0f42) },
585 { PCI_VDEVICE(INTEL
, 0x0f43) },
586 { PCI_VDEVICE(INTEL
, 0x0f44) },
587 { PCI_VDEVICE(INTEL
, 0x0f45) },
588 { PCI_VDEVICE(INTEL
, 0x0f46) },
589 { PCI_VDEVICE(INTEL
, 0x0f47) },
593 U_BOOT_PCI_DEVICE(i2c_designware
, designware_pci_supported
);
596 #endif /* CONFIG_DM_I2C */