drivers/i2c/fsl_i2c.c

   1 /*
   2  * Copyright 2006 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  16  * MA 02111-1307 USA
  17  */
  18
  19 #include <common.h>
  20
  21 #ifdef CONFIG_FSL_I2C
  22 #ifdef CONFIG_HARD_I2C
  23
  24 #include <command.h>
  25 #include <i2c.h>                /* Functional interface */
  26
  27 #include <asm/io.h>
  28 #include <asm/fsl_i2c.h>        /* HW definitions */
  29
  30 #define I2C_TIMEOUT     (CFG_HZ / 4)
  31
  32 #define I2C_READ_BIT  1
  33 #define I2C_WRITE_BIT 0
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 /* Initialize the bus pointer to whatever one the SPD EEPROM is on.
  38  * Default is bus 0.  This is necessary because the DDR initialization
  39  * runs from ROM, and we can't switch buses because we can't modify
  40  * the global variables.
  41  */
  42 #ifdef CFG_SPD_BUS_NUM
  43 static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM;
  44 #else
  45 static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0;
  46 #endif
  47
  48 static unsigned int i2c_bus_speed[2] = {CFG_I2C_SPEED, CFG_I2C_SPEED};
  49
  50 static const struct fsl_i2c *i2c_dev[2] = {
  51         (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET),
  52 #ifdef CFG_I2C2_OFFSET
  53         (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET)
  54 #endif
  55 };
  56
  57 /* I2C speed map for a DFSR value of 1 */
  58
  59 /*
  60  * Map I2C frequency dividers to FDR and DFSR values
  61  *
  62  * This structure is used to define the elements of a table that maps I2C
  63  * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
  64  * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
  65  * Sampling Rate (DFSR) registers.
  66  *
  67  * The actual table should be defined in the board file, and it must be called
  68  * fsl_i2c_speed_map[].
  69  *
  70  * The last entry of the table must have a value of {-1, X}, where X is same
  71  * FDR/DFSR values as the second-to-last entry.  This guarantees that any
  72  * search through the array will always find a match.
  73  *
  74  * The values of the divider must be in increasing numerical order, i.e.
  75  * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
  76  *
  77  * For this table, the values are based on a value of 1 for the DFSR
  78  * register.  See the application note AN2919 "Determining the I2C Frequency
  79  * Divider Ratio for SCL"
  80  */
  81 static const struct {
  82         unsigned short divider;
  83         u8 dfsr;
  84         u8 fdr;
  85 } fsl_i2c_speed_map[] = {
  86         {160, 1, 32}, {192, 1, 33}, {224, 1, 34}, {256, 1, 35},
  87         {288, 1, 0}, {320, 1, 1}, {352, 6, 1}, {384, 1, 2}, {416, 6, 2},
  88         {448, 1, 38}, {480, 1, 3}, {512, 1, 39}, {544, 11, 3}, {576, 1, 4},
  89         {608, 22, 3}, {640, 1, 5}, {672, 32, 3}, {704, 11, 5}, {736, 43, 3},
  90         {768, 1, 6}, {800, 54, 3}, {832, 11, 6}, {896, 1, 42}, {960, 1, 7},
  91         {1024, 1, 43}, {1088, 22, 7}, {1152, 1, 8}, {1216, 43, 7}, {1280, 1, 9},
  92         {1408, 22, 9}, {1536, 1, 10}, {1664, 22, 10}, {1792, 1, 46},
  93         {1920, 1, 11}, {2048, 1, 47}, {2176, 43, 11}, {2304, 1, 12},
  94         {2560, 1, 13}, {2816, 43, 13}, {3072, 1, 14}, {3328, 43, 14},
  95         {3584, 1, 50}, {3840, 1, 15}, {4096, 1, 51}, {4608, 1, 16},
  96         {5120, 1, 17}, {6144, 1, 18}, {7168, 1, 54}, {7680, 1, 19},
  97         {8192, 1, 55}, {9216, 1, 20}, {10240, 1, 21}, {12288, 1, 22},
  98         {14336, 1, 58}, {15360, 1, 23}, {16384, 1, 59}, {18432, 1, 24},
  99         {20480, 1, 25}, {24576, 1, 26}, {28672, 1, 62}, {30720, 1, 27},
 100         {32768, 1, 63}, {36864, 1, 28}, {40960, 1, 29}, {49152, 1, 30},
 101         {61440, 1, 31}, {-1, 1, 31}
 102 };
 103
 104 /**
 105  * Set the I2C bus speed for a given I2C device
 106  *
 107  * @param dev: the I2C device
 108  * @i2c_clk: I2C bus clock frequency
 109  * @speed: the desired speed of the bus
 110  *
 111  * The I2C device must be stopped before calling this function.
 112  *
 113  * The return value is the actual bus speed that is set.
 114  */
 115 static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
 116         unsigned int i2c_clk, unsigned int speed)
 117 {
 118         unsigned short divider = min(i2c_clk / speed, (unsigned short) -1);
 119         unsigned int i;
 120
 121         /*
 122          * We want to choose an FDR/DFSR that generates an I2C bus speed that
 123          * is equal to or lower than the requested speed.  That means that we
 124          * want the first divider that is equal to or greater than the
 125          * calculated divider.
 126          */
 127
 128         for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
 129                 if (fsl_i2c_speed_map[i].divider >= divider) {
 130                         u8 fdr, dfsr;
 131                         dfsr = fsl_i2c_speed_map[i].dfsr;
 132                         fdr = fsl_i2c_speed_map[i].fdr;
 133                         speed = i2c_clk / fsl_i2c_speed_map[i].divider;
 134                         writeb(fdr, &dev->fdr);         /* set bus speed */
 135                         writeb(dfsr, &dev->dfsrr);      /* set default filter */
 136                         break;
 137                 }
 138
 139         return speed;
 140 }
 141
 142 void
 143 i2c_init(int speed, int slaveadd)
 144 {
 145         struct fsl_i2c *dev;
 146         unsigned int temp;
 147
 148         dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET);
 149
 150         writeb(0, &dev->cr);                    /* stop I2C controller */
 151         udelay(5);                              /* let it shutdown in peace */
 152         temp = set_i2c_bus_speed(dev, gd->i2c1_clk, speed);
 153         if (gd->flags & GD_FLG_RELOC)
 154                 i2c_bus_speed[0] = temp;
 155         writeb(slaveadd << 1, &dev->adr);       /* write slave address */
 156         writeb(0x0, &dev->sr);                  /* clear status register */
 157         writeb(I2C_CR_MEN, &dev->cr);           /* start I2C controller */
 158
 159 #ifdef  CFG_I2C2_OFFSET
 160         dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET);
 161
 162         writeb(0, &dev->cr);                    /* stop I2C controller */
 163         udelay(5);                              /* let it shutdown in peace */
 164         temp = set_i2c_bus_speed(dev, gd->i2c2_clk, speed);
 165         if (gd->flags & GD_FLG_RELOC)
 166                 i2c_bus_speed[1] = temp;
 167         writeb(slaveadd << 1, &dev->adr);       /* write slave address */
 168         writeb(0x0, &dev->sr);                  /* clear status register */
 169         writeb(I2C_CR_MEN, &dev->cr);           /* start I2C controller */
 170 #endif
 171 }
 172
 173 static __inline__ int
 174 i2c_wait4bus(void)
 175 {
 176         unsigned long long timeval = get_ticks();
 177
 178         while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) {
 179                 if ((get_ticks() - timeval) > usec2ticks(I2C_TIMEOUT))
 180                         return -1;
 181         }
 182
 183         return 0;
 184 }
 185
 186 static __inline__ int
 187 i2c_wait(int write)
 188 {
 189         u32 csr;
 190         unsigned long long timeval = get_ticks();
 191
 192         do {
 193                 csr = readb(&i2c_dev[i2c_bus_num]->sr);
 194                 if (!(csr & I2C_SR_MIF))
 195                         continue;
 196
 197                 writeb(0x0, &i2c_dev[i2c_bus_num]->sr);
 198
 199                 if (csr & I2C_SR_MAL) {
 200                         debug("i2c_wait: MAL\n");
 201                         return -1;
 202                 }
 203
 204                 if (!(csr & I2C_SR_MCF))        {
 205                         debug("i2c_wait: unfinished\n");
 206                         return -1;
 207                 }
 208
 209                 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
 210                         debug("i2c_wait: No RXACK\n");
 211                         return -1;
 212                 }
 213
 214                 return 0;
 215         } while ((get_ticks() - timeval) < usec2ticks(I2C_TIMEOUT));
 216
 217         debug("i2c_wait: timed out\n");
 218         return -1;
 219 }
 220
 221 static __inline__ int
 222 i2c_write_addr (u8 dev, u8 dir, int rsta)
 223 {
 224         writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
 225                | (rsta ? I2C_CR_RSTA : 0),
 226                &i2c_dev[i2c_bus_num]->cr);
 227
 228         writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr);
 229
 230         if (i2c_wait(I2C_WRITE_BIT) < 0)
 231                 return 0;
 232
 233         return 1;
 234 }
 235
 236 static __inline__ int
 237 __i2c_write(u8 *data, int length)
 238 {
 239         int i;
 240
 241         writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
 242                &i2c_dev[i2c_bus_num]->cr);
 243
 244         for (i = 0; i < length; i++) {
 245                 writeb(data[i], &i2c_dev[i2c_bus_num]->dr);
 246
 247                 if (i2c_wait(I2C_WRITE_BIT) < 0)
 248                         break;
 249         }
 250
 251         return i;
 252 }
 253
 254 static __inline__ int
 255 __i2c_read(u8 *data, int length)
 256 {
 257         int i;
 258
 259         writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
 260                &i2c_dev[i2c_bus_num]->cr);
 261
 262         /* dummy read */
 263         readb(&i2c_dev[i2c_bus_num]->dr);
 264
 265         for (i = 0; i < length; i++) {
 266                 if (i2c_wait(I2C_READ_BIT) < 0)
 267                         break;
 268
 269                 /* Generate ack on last next to last byte */
 270                 if (i == length - 2)
 271                         writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
 272                                &i2c_dev[i2c_bus_num]->cr);
 273
 274                 /* Generate stop on last byte */
 275                 if (i == length - 1)
 276                         writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr);
 277
 278                 data[i] = readb(&i2c_dev[i2c_bus_num]->dr);
 279         }
 280
 281         return i;
 282 }
 283
 284 int
 285 i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
 286 {
 287         int i = -1; /* signal error */
 288         u8 *a = (u8*)&addr;
 289
 290         if (i2c_wait4bus() >= 0
 291             && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
 292             && __i2c_write(&a[4 - alen], alen) == alen)
 293                 i = 0; /* No error so far */
 294
 295         if (length
 296             && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0)
 297                 i = __i2c_read(data, length);
 298
 299         writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
 300
 301         if (i == length)
 302             return 0;
 303
 304         return -1;
 305 }
 306
 307 int
 308 i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
 309 {
 310         int i = -1; /* signal error */
 311         u8 *a = (u8*)&addr;
 312
 313         if (i2c_wait4bus() >= 0
 314             && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
 315             && __i2c_write(&a[4 - alen], alen) == alen) {
 316                 i = __i2c_write(data, length);
 317         }
 318
 319         writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
 320
 321         if (i == length)
 322             return 0;
 323
 324         return -1;
 325 }
 326
 327 int
 328 i2c_probe(uchar chip)
 329 {
 330         /* For unknow reason the controller will ACK when
 331          * probing for a slave with the same address, so skip
 332          * it.
 333          */
 334         if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1))
 335                 return -1;
 336
 337         return i2c_read(chip, 0, 0, NULL, 0);
 338 }
 339
 340 uchar
 341 i2c_reg_read(uchar i2c_addr, uchar reg)
 342 {
 343         uchar buf[1];
 344
 345         i2c_read(i2c_addr, reg, 1, buf, 1);
 346
 347         return buf[0];
 348 }
 349
 350 void
 351 i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
 352 {
 353         i2c_write(i2c_addr, reg, 1, &val, 1);
 354 }
 355
 356 int i2c_set_bus_num(unsigned int bus)
 357 {
 358 #ifdef CFG_I2C2_OFFSET
 359         if (bus > 1) {
 360 #else
 361         if (bus > 0) {
 362 #endif
 363                 return -1;
 364         }
 365
 366         i2c_bus_num = bus;
 367
 368         return 0;
 369 }
 370
 371 int i2c_set_bus_speed(unsigned int speed)
 372 {
 373         unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk;
 374
 375         writeb(0, &i2c_dev[i2c_bus_num]->cr);           /* stop controller */
 376         i2c_bus_speed[i2c_bus_num] =
 377                 set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed);
 378         writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);  /* start controller */
 379
 380         return 0;
 381 }
 382
 383 unsigned int i2c_get_bus_num(void)
 384 {
 385         return i2c_bus_num;
 386 }
 387
 388 unsigned int i2c_get_bus_speed(void)
 389 {
 390         return i2c_bus_speed[i2c_bus_num];
 391 }
 392
 393 #endif /* CONFIG_HARD_I2C */
 394 #endif /* CONFIG_FSL_I2C */