drivers/i2c/i2c-uniphier-f.c

   1 /*
   2  * Copyright (C) 2014      Panasonic Corporation
   3  * Copyright (C) 2015-2016 Socionext Inc.
   4  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <linux/types.h>
  11 #include <linux/io.h>
  12 #include <linux/sizes.h>
  13 #include <linux/errno.h>
  14 #include <dm/device.h>
  15 #include <i2c.h>
  16 #include <fdtdec.h>
  17
  18 struct uniphier_fi2c_regs {
  19         u32 cr;                         /* control register */
  20 #define I2C_CR_MST      (1 << 3)        /* master mode */
  21 #define I2C_CR_STA      (1 << 2)        /* start condition */
  22 #define I2C_CR_STO      (1 << 1)        /* stop condition */
  23 #define I2C_CR_NACK     (1 << 0)        /* not ACK */
  24         u32 dttx;                       /* send FIFO (write-only) */
  25 #define dtrx            dttx            /* receive FIFO (read-only) */
  26 #define I2C_DTTX_CMD    (1 << 8)        /* send command (slave addr) */
  27 #define I2C_DTTX_RD     (1 << 0)        /* read */
  28         u32 __reserved;                 /* no register at offset 0x08 */
  29         u32 slad;                       /* slave address */
  30         u32 cyc;                        /* clock cycle control */
  31         u32 lctl;                       /* clock low period control */
  32         u32 ssut;                       /* restart/stop setup time control */
  33         u32 dsut;                       /* data setup time control */
  34         u32 intr;                       /* interrupt status */
  35         u32 ie;                         /* interrupt enable */
  36         u32 ic;                         /* interrupt clear */
  37 #define I2C_INT_TE      (1 << 9)        /* TX FIFO empty */
  38 #define I2C_INT_RB      (1 << 4)        /* received specified bytes */
  39 #define I2C_INT_NA      (1 << 2)        /* no answer */
  40 #define I2C_INT_AL      (1 << 1)        /* arbitration lost */
  41         u32 sr;                         /* status register */
  42 #define I2C_SR_DB       (1 << 12)       /* device busy */
  43 #define I2C_SR_BB       (1 << 8)        /* bus busy */
  44 #define I2C_SR_RFF      (1 << 3)        /* Rx FIFO full */
  45 #define I2C_SR_RNE      (1 << 2)        /* Rx FIFO not empty */
  46 #define I2C_SR_TNF      (1 << 1)        /* Tx FIFO not full */
  47 #define I2C_SR_TFE      (1 << 0)        /* Tx FIFO empty */
  48         u32 __reserved2;                /* no register at offset 0x30 */
  49         u32 rst;                        /* reset control */
  50 #define I2C_RST_TBRST   (1 << 2)        /* clear Tx FIFO */
  51 #define I2C_RST_RBRST   (1 << 1)        /* clear Rx FIFO */
  52 #define I2C_RST_RST     (1 << 0)        /* forcible bus reset */
  53         u32 bm;                         /* bus monitor */
  54         u32 noise;                      /* noise filter control */
  55         u32 tbc;                        /* Tx byte count setting */
  56         u32 rbc;                        /* Rx byte count setting */
  57         u32 tbcm;                       /* Tx byte count monitor */
  58         u32 rbcm;                       /* Rx byte count monitor */
  59         u32 brst;                       /* bus reset */
  60 #define I2C_BRST_FOEN   (1 << 1)        /* normal operation */
  61 #define I2C_BRST_RSCLO  (1 << 0)        /* release SCL low fixing */
  62 };
  63
  64 #define FIOCLK  50000000
  65
  66 struct uniphier_fi2c_dev {
  67         struct uniphier_fi2c_regs __iomem *regs;        /* register base */
  68         unsigned long fioclk;                   /* internal operation clock */
  69         unsigned long timeout;                  /* time out (us) */
  70 };
  71
  72 static int poll_status(u32 __iomem *reg, u32 flag)
  73 {
  74         int wait = 1000000; /* 1 sec is long enough */
  75
  76         while (readl(reg) & flag) {
  77                 if (wait-- < 0)
  78                         return -EREMOTEIO;
  79                 udelay(1);
  80         }
  81
  82         return 0;
  83 }
  84
  85 static int reset_bus(struct uniphier_fi2c_regs __iomem *regs)
  86 {
  87         int ret;
  88
  89         /* bus forcible reset */
  90         writel(I2C_RST_RST, &regs->rst);
  91         ret = poll_status(&regs->rst, I2C_RST_RST);
  92         if (ret < 0)
  93                 debug("error: fail to reset I2C controller\n");
  94
  95         return ret;
  96 }
  97
  98 static int check_device_busy(struct uniphier_fi2c_regs __iomem *regs)
  99 {
 100         int ret;
 101
 102         ret = poll_status(&regs->sr, I2C_SR_DB);
 103         if (ret < 0) {
 104                 debug("error: device busy too long. reset...\n");
 105                 ret = reset_bus(regs);
 106         }
 107
 108         return ret;
 109 }
 110
 111 static int uniphier_fi2c_probe(struct udevice *dev)
 112 {
 113         fdt_addr_t addr;
 114         struct uniphier_fi2c_dev *priv = dev_get_priv(dev);
 115         int ret;
 116
 117         addr = dev_get_addr(dev);
 118         if (addr == FDT_ADDR_T_NONE)
 119                 return -EINVAL;
 120
 121         priv->regs = devm_ioremap(dev, addr, SZ_128);
 122         if (!priv->regs)
 123                 return -ENOMEM;
 124
 125         priv->fioclk = FIOCLK;
 126
 127         /* bus forcible reset */
 128         ret = reset_bus(priv->regs);
 129         if (ret < 0)
 130                 return ret;
 131
 132         writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, &priv->regs->brst);
 133
 134         return 0;
 135 }
 136
 137 static int wait_for_irq(struct uniphier_fi2c_dev *dev, u32 flags,
 138                         bool *stop)
 139 {
 140         u32 irq;
 141         unsigned long wait = dev->timeout;
 142         int ret = -EREMOTEIO;
 143
 144         do {
 145                 udelay(1);
 146                 irq = readl(&dev->regs->intr);
 147         } while (!(irq & flags) && wait--);
 148
 149         if (wait < 0) {
 150                 debug("error: time out\n");
 151                 return ret;
 152         }
 153
 154         if (irq & I2C_INT_AL) {
 155                 debug("error: arbitration lost\n");
 156                 *stop = false;
 157                 return ret;
 158         }
 159
 160         if (irq & I2C_INT_NA) {
 161                 debug("error: no answer\n");
 162                 return ret;
 163         }
 164
 165         return 0;
 166 }
 167
 168 static int issue_stop(struct uniphier_fi2c_dev *dev, int old_ret)
 169 {
 170         int ret;
 171
 172         debug("stop condition\n");
 173         writel(I2C_CR_MST | I2C_CR_STO, &dev->regs->cr);
 174
 175         ret = poll_status(&dev->regs->sr, I2C_SR_DB);
 176         if (ret < 0)
 177                 debug("error: device busy after operation\n");
 178
 179         return old_ret ? old_ret : ret;
 180 }
 181
 182 static int uniphier_fi2c_transmit(struct uniphier_fi2c_dev *dev, uint addr,
 183                                   uint len, const u8 *buf, bool *stop)
 184 {
 185         int ret;
 186         const u32 irq_flags = I2C_INT_TE | I2C_INT_NA | I2C_INT_AL;
 187         struct uniphier_fi2c_regs __iomem *regs = dev->regs;
 188
 189         debug("%s: addr = %x, len = %d\n", __func__, addr, len);
 190
 191         writel(I2C_DTTX_CMD | addr << 1, &regs->dttx);
 192
 193         writel(irq_flags, &regs->ie);
 194         writel(irq_flags, &regs->ic);
 195
 196         debug("start condition\n");
 197         writel(I2C_CR_MST | I2C_CR_STA, &regs->cr);
 198
 199         ret = wait_for_irq(dev, irq_flags, stop);
 200         if (ret < 0)
 201                 goto error;
 202
 203         while (len--) {
 204                 debug("sending %x\n", *buf);
 205                 writel(*buf++, &regs->dttx);
 206
 207                 writel(irq_flags, &regs->ic);
 208
 209                 ret = wait_for_irq(dev, irq_flags, stop);
 210                 if (ret < 0)
 211                         goto error;
 212         }
 213
 214 error:
 215         writel(irq_flags, &regs->ic);
 216
 217         if (*stop)
 218                 ret = issue_stop(dev, ret);
 219
 220         return ret;
 221 }
 222
 223 static int uniphier_fi2c_receive(struct uniphier_fi2c_dev *dev, uint addr,
 224                                  uint len, u8 *buf, bool *stop)
 225 {
 226         int ret = 0;
 227         const u32 irq_flags = I2C_INT_RB | I2C_INT_NA | I2C_INT_AL;
 228         struct uniphier_fi2c_regs __iomem *regs = dev->regs;
 229
 230         debug("%s: addr = %x, len = %d\n", __func__, addr, len);
 231
 232         /*
 233          * In case 'len == 0', only the slave address should be sent
 234          * for probing, which is covered by the transmit function.
 235          */
 236         if (len == 0)
 237                 return uniphier_fi2c_transmit(dev, addr, len, buf, stop);
 238
 239         writel(I2C_DTTX_CMD | I2C_DTTX_RD | addr << 1, &regs->dttx);
 240
 241         writel(0, &regs->rbc);
 242         writel(irq_flags, &regs->ie);
 243         writel(irq_flags, &regs->ic);
 244
 245         debug("start condition\n");
 246         writel(I2C_CR_MST | I2C_CR_STA | (len == 1 ? I2C_CR_NACK : 0),
 247                &regs->cr);
 248
 249         while (len--) {
 250                 ret = wait_for_irq(dev, irq_flags, stop);
 251                 if (ret < 0)
 252                         goto error;
 253
 254                 *buf++ = readl(&regs->dtrx);
 255                 debug("received %x\n", *(buf - 1));
 256
 257                 if (len == 1)
 258                         writel(I2C_CR_MST | I2C_CR_NACK, &regs->cr);
 259
 260                 writel(irq_flags, &regs->ic);
 261         }
 262
 263 error:
 264         writel(irq_flags, &regs->ic);
 265
 266         if (*stop)
 267                 ret = issue_stop(dev, ret);
 268
 269         return ret;
 270 }
 271
 272 static int uniphier_fi2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 273                              int nmsgs)
 274 {
 275         int ret;
 276         struct uniphier_fi2c_dev *dev = dev_get_priv(bus);
 277         bool stop;
 278
 279         ret = check_device_busy(dev->regs);
 280         if (ret < 0)
 281                 return ret;
 282
 283         for (; nmsgs > 0; nmsgs--, msg++) {
 284                 /* If next message is read, skip the stop condition */
 285                 stop = nmsgs > 1 && msg[1].flags & I2C_M_RD ? false : true;
 286
 287                 if (msg->flags & I2C_M_RD)
 288                         ret = uniphier_fi2c_receive(dev, msg->addr, msg->len,
 289                                                     msg->buf, &stop);
 290                 else
 291                         ret = uniphier_fi2c_transmit(dev, msg->addr, msg->len,
 292                                                      msg->buf, &stop);
 293
 294                 if (ret < 0)
 295                         break;
 296         }
 297
 298         return ret;
 299 }
 300
 301 static int uniphier_fi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 302 {
 303         int ret;
 304         unsigned int clk_count;
 305         struct uniphier_fi2c_dev *dev = dev_get_priv(bus);
 306         struct uniphier_fi2c_regs __iomem *regs = dev->regs;
 307
 308         /* max supported frequency is 400 kHz */
 309         if (speed > 400000)
 310                 return -EINVAL;
 311
 312         ret = check_device_busy(dev->regs);
 313         if (ret < 0)
 314                 return ret;
 315
 316         /* make sure the bus is idle when changing the frequency */
 317         writel(I2C_BRST_RSCLO, &regs->brst);
 318
 319         clk_count = dev->fioclk / speed;
 320
 321         writel(clk_count, &regs->cyc);
 322         writel(clk_count / 2, &regs->lctl);
 323         writel(clk_count / 2, &regs->ssut);
 324         writel(clk_count / 16, &regs->dsut);
 325
 326         writel(I2C_BRST_FOEN | I2C_BRST_RSCLO, &regs->brst);
 327
 328         /*
 329          * Theoretically, each byte can be transferred in
 330          * 1000000 * 9 / speed usec.
 331          * This time out value is long enough.
 332          */
 333         dev->timeout = 100000000L / speed;
 334
 335         return 0;
 336 }
 337
 338 static const struct dm_i2c_ops uniphier_fi2c_ops = {
 339         .xfer = uniphier_fi2c_xfer,
 340         .set_bus_speed = uniphier_fi2c_set_bus_speed,
 341 };
 342
 343 static const struct udevice_id uniphier_fi2c_of_match[] = {
 344         { .compatible = "socionext,uniphier-fi2c" },
 345         { /* sentinel */ }
 346 };
 347
 348 U_BOOT_DRIVER(uniphier_fi2c) = {
 349         .name = "uniphier-fi2c",
 350         .id = UCLASS_I2C,
 351         .of_match = uniphier_fi2c_of_match,
 352         .probe = uniphier_fi2c_probe,
 353         .priv_auto_alloc_size = sizeof(struct uniphier_fi2c_dev),
 354         .ops = &uniphier_fi2c_ops,
 355 };