drivers/i2c/mv_i2c.h

   1 /*
   2  * (C) Copyright 2011
   3  * Marvell Inc, <www.marvell.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _MV_I2C_H_
   9 #define _MV_I2C_H_
  10 extern void i2c_clk_enable(void);
  11
  12 /* Shall the current transfer have a start/stop condition? */
  13 #define I2C_COND_NORMAL         0
  14 #define I2C_COND_START          1
  15 #define I2C_COND_STOP           2
  16
  17 /* Shall the current transfer be ack/nacked or being waited for it? */
  18 #define I2C_ACKNAK_WAITACK      1
  19 #define I2C_ACKNAK_SENDACK      2
  20 #define I2C_ACKNAK_SENDNAK      4
  21
  22 /* Specify who shall transfer the data (master or slave) */
  23 #define I2C_READ                0
  24 #define I2C_WRITE               1
  25
  26 #if (CONFIG_SYS_I2C_SPEED == 400000)
  27 #define I2C_ICR_INIT    (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD \
  28                 | ICR_SCLE)
  29 #else
  30 #define I2C_ICR_INIT    (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
  31 #endif
  32
  33 #define I2C_ISR_INIT            0x7FF
  34 /* ----- Control register bits ---------------------------------------- */
  35
  36 #define ICR_START       0x1             /* start bit */
  37 #define ICR_STOP        0x2             /* stop bit */
  38 #define ICR_ACKNAK      0x4             /* send ACK(0) or NAK(1) */
  39 #define ICR_TB          0x8             /* transfer byte bit */
  40 #define ICR_MA          0x10            /* master abort */
  41 #define ICR_SCLE        0x20            /* master clock enable, mona SCLEA */
  42 #define ICR_IUE         0x40            /* unit enable */
  43 #define ICR_GCD         0x80            /* general call disable */
  44 #define ICR_ITEIE       0x100           /* enable tx interrupts */
  45 #define ICR_IRFIE       0x200           /* enable rx interrupts, mona: DRFIE */
  46 #define ICR_BEIE        0x400           /* enable bus error ints */
  47 #define ICR_SSDIE       0x800           /* slave STOP detected int enable */
  48 #define ICR_ALDIE       0x1000          /* enable arbitration interrupt */
  49 #define ICR_SADIE       0x2000          /* slave address detected int enable */
  50 #define ICR_UR          0x4000          /* unit reset */
  51 #define ICR_FM          0x8000          /* Fast Mode */
  52
  53 /* ----- Status register bits ----------------------------------------- */
  54
  55 #define ISR_RWM         0x1             /* read/write mode */
  56 #define ISR_ACKNAK      0x2             /* ack/nak status */
  57 #define ISR_UB          0x4             /* unit busy */
  58 #define ISR_IBB         0x8             /* bus busy */
  59 #define ISR_SSD         0x10            /* slave stop detected */
  60 #define ISR_ALD         0x20            /* arbitration loss detected */
  61 #define ISR_ITE         0x40            /* tx buffer empty */
  62 #define ISR_IRF         0x80            /* rx buffer full */
  63 #define ISR_GCAD        0x100           /* general call address detected */
  64 #define ISR_SAD         0x200           /* slave address detected */
  65 #define ISR_BED         0x400           /* bus error no ACK/NAK */
  66
  67 #endif