2 * Driver for the TWSI (i2c) controller found on the Marvell
3 * orion5x and kirkwood SoC families.
5 * Author: Albert Aribaud <albert.u.boot@aribaud.net>
6 * Copyright (c) 2010 Albert Aribaud.
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/errno.h>
17 * include a file that will provide CONFIG_I2C_MVTWSI_BASE
18 * and possibly other settings
21 #if defined(CONFIG_ORION5X)
22 #include <asm/arch/orion5x.h>
23 #elif defined(CONFIG_KIRKWOOD)
24 #include <asm/arch/kirkwood.h>
26 #error Driver mvtwsi not supported by SoC or board
30 * TWSI register structure
33 struct mvtwsi_registers
{
38 u32 status
; /* when reading */
39 u32 baudrate
; /* when writing */
47 * Control register fields
50 #define MVTWSI_CONTROL_ACK 0x00000004
51 #define MVTWSI_CONTROL_IFLG 0x00000008
52 #define MVTWSI_CONTROL_STOP 0x00000010
53 #define MVTWSI_CONTROL_START 0x00000020
54 #define MVTWSI_CONTROL_TWSIEN 0x00000040
55 #define MVTWSI_CONTROL_INTEN 0x00000080
58 * Status register values -- only those expected in normal master
59 * operation on non-10-bit-address devices; whatever status we don't
60 * expect in nominal conditions (bus errors, arbitration losses,
61 * missing ACKs...) we just pass back to the caller as an error
65 #define MVTWSI_STATUS_START 0x08
66 #define MVTWSI_STATUS_REPEATED_START 0x10
67 #define MVTWSI_STATUS_ADDR_W_ACK 0x18
68 #define MVTWSI_STATUS_DATA_W_ACK 0x28
69 #define MVTWSI_STATUS_ADDR_R_ACK 0x40
70 #define MVTWSI_STATUS_ADDR_R_NAK 0x48
71 #define MVTWSI_STATUS_DATA_R_ACK 0x50
72 #define MVTWSI_STATUS_DATA_R_NAK 0x58
73 #define MVTWSI_STATUS_IDLE 0xF8
76 * The single instance of the controller we'll be dealing with
79 static struct mvtwsi_registers
*twsi
=
80 (struct mvtwsi_registers
*) CONFIG_I2C_MVTWSI_BASE
;
83 * Returned statuses are 0 for success and nonzero otherwise.
84 * Currently, cmd_i2c and cmd_eeprom do not interpret an error status.
85 * Thus to ease debugging, the return status contains some debug info:
86 * - bits 31..24 are error class: 1 is timeout, 2 is 'status mismatch'.
87 * - bits 23..16 are the last value of the control register.
88 * - bits 15..8 are the last value of the status register.
89 * - bits 7..0 are the expected value of the status register.
92 #define MVTWSI_ERROR_WRONG_STATUS 0x01
93 #define MVTWSI_ERROR_TIMEOUT 0x02
95 #define MVTWSI_ERROR(ec, lc, ls, es) (((ec << 24) & 0xFF000000) | \
96 ((lc << 16) & 0x00FF0000) | ((ls<<8) & 0x0000FF00) | (es & 0xFF))
99 * Wait for IFLG to raise, or return 'timeout'; then if status is as expected,
100 * return 0 (ok) or return 'wrong status'.
102 static int twsi_wait(int expected_status
)
108 control
= readl(&twsi
->control
);
109 if (control
& MVTWSI_CONTROL_IFLG
) {
110 status
= readl(&twsi
->status
);
111 if (status
== expected_status
)
115 MVTWSI_ERROR_WRONG_STATUS
,
116 control
, status
, expected_status
);
118 udelay(10); /* one clock cycle at 100 kHz */
120 status
= readl(&twsi
->status
);
122 MVTWSI_ERROR_TIMEOUT
, control
, status
, expected_status
);
126 * These flags are ORed to any write to the control register
127 * They allow global setting of TWSIEN and ACK.
128 * By default none are set.
129 * twsi_start() sets TWSIEN (in case the controller was disabled)
130 * twsi_recv() sets ACK or resets it depending on expected status.
132 static u8 twsi_control_flags
= MVTWSI_CONTROL_TWSIEN
;
135 * Assert the START condition, either in a single I2C transaction
136 * or inside back-to-back ones (repeated starts).
138 static int twsi_start(int expected_status
)
140 /* globally set TWSIEN in case it was not */
141 twsi_control_flags
|= MVTWSI_CONTROL_TWSIEN
;
143 writel(twsi_control_flags
| MVTWSI_CONTROL_START
, &twsi
->control
);
144 /* wait for controller to process START */
145 return twsi_wait(expected_status
);
149 * Send a byte (i2c address or data).
151 static int twsi_send(u8 byte
, int expected_status
)
153 /* put byte in data register for sending */
154 writel(byte
, &twsi
->data
);
155 /* clear any pending interrupt -- that'll cause sending */
156 writel(twsi_control_flags
, &twsi
->control
);
157 /* wait for controller to receive byte and check ACK */
158 return twsi_wait(expected_status
);
163 * Global mvtwsi_control_flags variable says if we should ack or nak.
165 static int twsi_recv(u8
*byte
)
167 int expected_status
, status
;
169 /* compute expected status based on ACK bit in global control flags */
170 if (twsi_control_flags
& MVTWSI_CONTROL_ACK
)
171 expected_status
= MVTWSI_STATUS_DATA_R_ACK
;
173 expected_status
= MVTWSI_STATUS_DATA_R_NAK
;
174 /* acknowledge *previous state* and launch receive */
175 writel(twsi_control_flags
, &twsi
->control
);
176 /* wait for controller to receive byte and assert ACK or NAK */
177 status
= twsi_wait(expected_status
);
178 /* if we did receive expected byte then store it */
180 *byte
= readl(&twsi
->data
);
186 * Assert the STOP condition.
187 * This is also used to force the bus back in idle (SDA=SCL=1).
189 static int twsi_stop(int status
)
191 int control
, stop_status
;
195 control
= MVTWSI_CONTROL_TWSIEN
| MVTWSI_CONTROL_STOP
;
196 writel(control
, &twsi
->control
);
197 /* wait for IDLE; IFLG won't rise so twsi_wait() is no use. */
199 stop_status
= readl(&twsi
->status
);
200 if (stop_status
== MVTWSI_STATUS_IDLE
)
202 udelay(10); /* one clock cycle at 100 kHz */
204 control
= readl(&twsi
->control
);
205 if (stop_status
!= MVTWSI_STATUS_IDLE
)
207 status
= MVTWSI_ERROR(
208 MVTWSI_ERROR_TIMEOUT
,
209 control
, status
, MVTWSI_STATUS_IDLE
);
214 * Ugly formula to convert m and n values to a frequency comes from
215 * TWSI specifications
218 #define TWSI_FREQUENCY(m, n) \
219 ((u8) (CONFIG_SYS_TCLK / (10 * (m + 1) * 2 * (1 << n))))
222 * These are required to be reprogrammed before enabling the controller
223 * because a reset loses them.
224 * Default values come from the spec, but a twsi_reset will change them.
225 * twsi_slave_address left uninitialized lest checkpatch.pl complains.
228 /* Baudrate generator: m (bits 7..4) =4, n (bits 3..0) =4 */
229 static u8 twsi_baud_rate
= 0x44; /* baudrate at controller reset */
230 /* Default frequency corresponding to default m=4, n=4 */
231 static u8 twsi_actual_speed
= TWSI_FREQUENCY(4, 4);
232 /* Default slave address is 0 (so is an uninitialized static) */
233 static u8 twsi_slave_address
;
237 * Called at end of i2c_init unsuccessful i2c transactions.
238 * Controller reset also resets the baud rate and slave address, so
241 static void twsi_reset(void)
243 /* ensure controller will be enabled by any twsi*() function */
244 twsi_control_flags
= MVTWSI_CONTROL_TWSIEN
;
245 /* reset controller */
246 writel(0, &twsi
->soft_reset
);
247 /* wait 2 ms -- this is what the Marvell LSP does */
250 writel(twsi_baud_rate
, &twsi
->baudrate
);
251 /* set slave address even though we don't use it */
252 writel(twsi_slave_address
, &twsi
->slave_address
);
253 writel(0, &twsi
->xtnd_slave_addr
);
254 /* assert STOP but don't care for the result */
259 * I2C init called by cmd_i2c when doing 'i2c reset'.
260 * Sets baud to the highest possible value not exceeding requested one.
262 void i2c_init(int requested_speed
, int slaveadd
)
264 int tmp_speed
, highest_speed
, n
, m
;
265 int baud
= 0x44; /* baudrate at controller reset */
267 /* use actual speed to collect progressively higher values */
269 /* compute m, n setting for highest speed not above requested speed */
270 for (n
= 0; n
< 8; n
++) {
271 for (m
= 0; m
< 16; m
++) {
272 tmp_speed
= TWSI_FREQUENCY(m
, n
);
273 if ((tmp_speed
<= requested_speed
)
274 && (tmp_speed
> highest_speed
)) {
275 highest_speed
= tmp_speed
;
280 /* save baud rate and slave for later calls to twsi_reset */
281 twsi_baud_rate
= baud
;
282 twsi_actual_speed
= highest_speed
;
283 twsi_slave_address
= slaveadd
;
284 /* reset controller */
289 * Begin I2C transaction with expected start status, at given address.
290 * Common to i2c_probe, i2c_read and i2c_write.
291 * Expected address status will derive from direction bit (bit 0) in addr.
293 static int i2c_begin(int expected_start_status
, u8 addr
)
295 int status
, expected_addr_status
;
297 /* compute expected address status from direction bit in addr */
298 if (addr
& 1) /* reading */
299 expected_addr_status
= MVTWSI_STATUS_ADDR_R_ACK
;
301 expected_addr_status
= MVTWSI_STATUS_ADDR_W_ACK
;
303 status
= twsi_start(expected_start_status
);
304 /* send out the address if the start went well */
306 status
= twsi_send(addr
, expected_addr_status
);
307 /* return ok or status of first failure to caller */
312 * I2C probe called by cmd_i2c when doing 'i2c probe'.
313 * Begin read, nak data byte, end.
315 int i2c_probe(uchar chip
)
321 status
= i2c_begin(MVTWSI_STATUS_START
, (chip
<< 1) | 1);
322 /* dummy read was accepted: receive byte but NAK it. */
324 status
= twsi_recv(&dummy_byte
);
325 /* Stop transaction */
327 /* return 0 or status of first failure */
332 * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
333 * Begin write, send address byte(s), begin read, receive data bytes, end.
335 * NOTE: some EEPROMS want a stop right before the second start, while
336 * some will choke if it is there. Deciding which we should do is eeprom
337 * stuff, not i2c, but at the moment the APIs won't let us put it in
338 * cmd_eeprom, so we have to choose here, and for the moment that'll be
339 * a repeated start without a preceding stop.
341 int i2c_read(u8 dev
, uint addr
, int alen
, u8
*data
, int length
)
345 /* begin i2c write to send the address bytes */
346 status
= i2c_begin(MVTWSI_STATUS_START
, (dev
<< 1));
347 /* send addr bytes */
348 while ((status
== 0) && alen
--)
349 status
= twsi_send(addr
>> (8*alen
),
350 MVTWSI_STATUS_DATA_W_ACK
);
351 /* begin i2c read to receive eeprom data bytes */
354 MVTWSI_STATUS_REPEATED_START
, (dev
<< 1) | 1);
355 /* prepare ACK if at least one byte must be received */
357 twsi_control_flags
|= MVTWSI_CONTROL_ACK
;
358 /* now receive actual bytes */
359 while ((status
== 0) && length
--) {
360 /* reset NAK if we if no more to read now */
362 twsi_control_flags
&= ~MVTWSI_CONTROL_ACK
;
363 /* read current byte */
364 status
= twsi_recv(data
++);
366 /* Stop transaction */
367 status
= twsi_stop(status
);
368 /* return 0 or status of first failure */
373 * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
374 * Begin write, send address byte(s), send data bytes, end.
376 int i2c_write(u8 dev
, uint addr
, int alen
, u8
*data
, int length
)
380 /* begin i2c write to send the eeprom adress bytes then data bytes */
381 status
= i2c_begin(MVTWSI_STATUS_START
, (dev
<< 1));
382 /* send addr bytes */
383 while ((status
== 0) && alen
--)
384 status
= twsi_send(addr
>> (8*alen
),
385 MVTWSI_STATUS_DATA_W_ACK
);
386 /* send data bytes */
387 while ((status
== 0) && (length
-- > 0))
388 status
= twsi_send(*(data
++), MVTWSI_STATUS_DATA_W_ACK
);
389 /* Stop transaction */
390 status
= twsi_stop(status
);
391 /* return 0 or status of first failure */
396 * Bus set routine: we only support bus 0.
398 int i2c_set_bus_num(unsigned int bus
)
407 * Bus get routine: hard-return bus 0.
409 unsigned int i2c_get_bus_num(void)