drivers/i2c/mvtwsi.c

   1 /*
   2  * Driver for the TWSI (i2c) controller found on the Marvell
   3  * orion5x and kirkwood SoC families.
   4  *
   5  * Author: Albert Aribaud <albert.u.boot@aribaud.net>
   6  * Copyright (c) 2010 Albert Aribaud.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <i2c.h>
  13 #include <asm/errno.h>
  14 #include <asm/io.h>
  15
  16 /*
  17  * Include a file that will provide CONFIG_I2C_MVTWSI_BASE*, and possibly other
  18  * settings
  19  */
  20
  21 #if defined(CONFIG_ORION5X)
  22 #include <asm/arch/orion5x.h>
  23 #elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU))
  24 #include <asm/arch/soc.h>
  25 #elif defined(CONFIG_SUNXI)
  26 #include <asm/arch/i2c.h>
  27 #else
  28 #error Driver mvtwsi not supported by SoC or board
  29 #endif
  30
  31 /*
  32  * TWSI register structure
  33  */
  34
  35 #ifdef CONFIG_SUNXI
  36
  37 struct  mvtwsi_registers {
  38         u32 slave_address;
  39         u32 xtnd_slave_addr;
  40         u32 data;
  41         u32 control;
  42         u32 status;
  43         u32 baudrate;
  44         u32 soft_reset;
  45 };
  46
  47 #else
  48
  49 struct  mvtwsi_registers {
  50         u32 slave_address;
  51         u32 data;
  52         u32 control;
  53         union {
  54                 u32 status;     /* When reading */
  55                 u32 baudrate;   /* When writing */
  56         };
  57         u32 xtnd_slave_addr;
  58         u32 reserved[2];
  59         u32 soft_reset;
  60 };
  61
  62 #endif
  63
  64 /*
  65  * enum mvtwsi_ctrl_register_fields - Bit masks for flags in the control
  66  * register
  67  */
  68 enum mvtwsi_ctrl_register_fields {
  69         /* Acknowledge bit */
  70         MVTWSI_CONTROL_ACK      = 0x00000004,
  71         /* Interrupt flag */
  72         MVTWSI_CONTROL_IFLG     = 0x00000008,
  73         /* Stop bit */
  74         MVTWSI_CONTROL_STOP     = 0x00000010,
  75         /* Start bit */
  76         MVTWSI_CONTROL_START    = 0x00000020,
  77         /* I2C enable */
  78         MVTWSI_CONTROL_TWSIEN   = 0x00000040,
  79         /* Interrupt enable */
  80         MVTWSI_CONTROL_INTEN    = 0x00000080,
  81 };
  82
  83 /*
  84  * On sun6i and newer, IFLG is a write-clear bit, which is cleared by writing 1;
  85  * on other platforms, it is a normal r/w bit, which is cleared by writing 0.
  86  */
  87
  88 #ifdef CONFIG_SUNXI_GEN_SUN6I
  89 #define MVTWSI_CONTROL_CLEAR_IFLG       0x00000008
  90 #else
  91 #define MVTWSI_CONTROL_CLEAR_IFLG       0x00000000
  92 #endif
  93
  94 /*
  95  * enum mvstwsi_status_values - Possible values of I2C controller's status
  96  * register
  97  *
  98  * Only those statuses expected in normal master operation on
  99  * non-10-bit-address devices are specified.
 100  *
 101  * Every status that's unexpected during normal operation (bus errors,
 102  * arbitration losses, missing ACKs...) is passed back to the caller as an error
 103  * code.
 104  */
 105 enum mvstwsi_status_values {
 106         /* START condition transmitted */
 107         MVTWSI_STATUS_START             = 0x08,
 108         /* Repeated START condition transmitted */
 109         MVTWSI_STATUS_REPEATED_START    = 0x10,
 110         /* Address + write bit transmitted, ACK received */
 111         MVTWSI_STATUS_ADDR_W_ACK        = 0x18,
 112         /* Data transmitted, ACK received */
 113         MVTWSI_STATUS_DATA_W_ACK        = 0x28,
 114         /* Address + read bit transmitted, ACK received */
 115         MVTWSI_STATUS_ADDR_R_ACK        = 0x40,
 116         /* Address + read bit transmitted, ACK not received */
 117         MVTWSI_STATUS_ADDR_R_NAK        = 0x48,
 118         /* Data received, ACK transmitted */
 119         MVTWSI_STATUS_DATA_R_ACK        = 0x50,
 120         /* Data received, ACK not transmitted */
 121         MVTWSI_STATUS_DATA_R_NAK        = 0x58,
 122         /* No relevant status */
 123         MVTWSI_STATUS_IDLE              = 0xF8,
 124 };
 125
 126 /*
 127  * enum mvstwsi_ack_flags - Determine whether a read byte should be
 128  * acknowledged or not.
 129  */
 130 enum mvtwsi_ack_flags {
 131         /* Send NAK after received byte */
 132         MVTWSI_READ_NAK = 0,
 133         /* Send ACK after received byte */
 134         MVTWSI_READ_ACK = 1,
 135 };
 136
 137 /*
 138  * MVTWSI controller base
 139  */
 140
 141 static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap)
 142 {
 143         switch (adap->hwadapnr) {
 144 #ifdef CONFIG_I2C_MVTWSI_BASE0
 145         case 0:
 146                 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE0;
 147 #endif
 148 #ifdef CONFIG_I2C_MVTWSI_BASE1
 149         case 1:
 150                 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE1;
 151 #endif
 152 #ifdef CONFIG_I2C_MVTWSI_BASE2
 153         case 2:
 154                 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE2;
 155 #endif
 156 #ifdef CONFIG_I2C_MVTWSI_BASE3
 157         case 3:
 158                 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE3;
 159 #endif
 160 #ifdef CONFIG_I2C_MVTWSI_BASE4
 161         case 4:
 162                 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE4;
 163 #endif
 164 #ifdef CONFIG_I2C_MVTWSI_BASE5
 165         case 5:
 166                 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE5;
 167 #endif
 168         default:
 169                 printf("Missing mvtwsi controller %d base\n", adap->hwadapnr);
 170                 break;
 171         }
 172
 173         return NULL;
 174 }
 175
 176 /*
 177  * enum mvtwsi_error_class - types of I2C errors
 178  */
 179 enum mvtwsi_error_class {
 180         /* The controller returned a different status than expected */
 181         MVTWSI_ERROR_WRONG_STATUS       = 0x01,
 182         /* The controller timed out */
 183         MVTWSI_ERROR_TIMEOUT            = 0x02,
 184 };
 185
 186 /*
 187  * mvtwsi_error() - Build I2C return code from error information
 188  *
 189  * For debugging purposes, this function packs some information of an occurred
 190  * error into a return code. These error codes are returned from I2C API
 191  * functions (i2c_{read,write}, dm_i2c_{read,write}, etc.).
 192  *
 193  * @ec:         The error class of the error (enum mvtwsi_error_class).
 194  * @lc:         The last value of the control register.
 195  * @ls:         The last value of the status register.
 196  * @es:         The expected value of the status register.
 197  * @return The generated error code.
 198  */
 199 inline uint mvtwsi_error(uint ec, uint lc, uint ls, uint es)
 200 {
 201         return ((ec << 24) & 0xFF000000)
 202                | ((lc << 16) & 0x00FF0000)
 203                | ((ls << 8) & 0x0000FF00)
 204                | (es & 0xFF);
 205 }
 206
 207 /*
 208  * Wait for IFLG to raise, or return 'timeout.' Then, if the status is as
 209  * expected, return 0 (ok) or 'wrong status' otherwise.
 210  */
 211 static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status)
 212 {
 213         int control, status;
 214         int timeout = 1000;
 215
 216         do {
 217                 control = readl(&twsi->control);
 218                 if (control & MVTWSI_CONTROL_IFLG) {
 219                         status = readl(&twsi->status);
 220                         if (status == expected_status)
 221                                 return 0;
 222                         else
 223                                 return mvtwsi_error(
 224                                         MVTWSI_ERROR_WRONG_STATUS,
 225                                         control, status, expected_status);
 226                 }
 227                 udelay(10); /* One clock cycle at 100 kHz */
 228         } while (timeout--);
 229         status = readl(&twsi->status);
 230         return mvtwsi_error(MVTWSI_ERROR_TIMEOUT, control, status,
 231                             expected_status);
 232 }
 233
 234 /*
 235  * Assert the START condition, either in a single I2C transaction
 236  * or inside back-to-back ones (repeated starts).
 237  */
 238 static int twsi_start(struct mvtwsi_registers *twsi, int expected_status)
 239 {
 240         /* Assert START */
 241         writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_START |
 242                MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
 243         /* Wait for controller to process START */
 244         return twsi_wait(twsi, expected_status);
 245 }
 246
 247 /*
 248  * Send a byte (i2c address or data).
 249  */
 250 static int twsi_send(struct mvtwsi_registers *twsi, u8 byte,
 251                      int expected_status)
 252 {
 253         /* Write byte to data register for sending */
 254         writel(byte, &twsi->data);
 255         /* Clear any pending interrupt -- that will cause sending */
 256         writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_CLEAR_IFLG,
 257                &twsi->control);
 258         /* Wait for controller to receive byte, and check ACK */
 259         return twsi_wait(twsi, expected_status);
 260 }
 261
 262 /*
 263  * Receive a byte.
 264  */
 265 static int twsi_recv(struct mvtwsi_registers *twsi, u8 *byte, int ack_flag)
 266 {
 267         int expected_status, status, control;
 268
 269         /* Compute expected status based on passed ACK flag */
 270         expected_status = ack_flag ? MVTWSI_STATUS_DATA_R_ACK :
 271                           MVTWSI_STATUS_DATA_R_NAK;
 272         /* Acknowledge *previous state*, and launch receive */
 273         control = MVTWSI_CONTROL_TWSIEN;
 274         control |= ack_flag == MVTWSI_READ_ACK ? MVTWSI_CONTROL_ACK : 0;
 275         writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
 276         /* Wait for controller to receive byte, and assert ACK or NAK */
 277         status = twsi_wait(twsi, expected_status);
 278         /* If we did receive the expected byte, store it */
 279         if (status == 0)
 280                 *byte = readl(&twsi->data);
 281         return status;
 282 }
 283
 284 /*
 285  * Assert the STOP condition.
 286  * This is also used to force the bus back to idle (SDA = SCL = 1).
 287  */
 288 static int twsi_stop(struct mvtwsi_registers *twsi)
 289 {
 290         int control, stop_status;
 291         int status = 0;
 292         int timeout = 1000;
 293
 294         /* Assert STOP */
 295         control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP;
 296         writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
 297         /* Wait for IDLE; IFLG won't rise, so we can't use twsi_wait() */
 298         do {
 299                 stop_status = readl(&twsi->status);
 300                 if (stop_status == MVTWSI_STATUS_IDLE)
 301                         break;
 302                 udelay(10); /* One clock cycle at 100 kHz */
 303         } while (timeout--);
 304         control = readl(&twsi->control);
 305         if (stop_status != MVTWSI_STATUS_IDLE)
 306                 status = mvtwsi_error(MVTWSI_ERROR_TIMEOUT,
 307                                       control, status, MVTWSI_STATUS_IDLE);
 308         return status;
 309 }
 310
 311 static uint twsi_calc_freq(const int n, const int m)
 312 {
 313 #ifdef CONFIG_SUNXI
 314         return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n));
 315 #else
 316         return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n));
 317 #endif
 318 }
 319
 320 /*
 321  * Reset controller.
 322  * Controller reset also resets the baud rate and slave address, so
 323  * they must be re-established afterwards.
 324  */
 325 static void twsi_reset(struct mvtwsi_registers *twsi)
 326 {
 327         /* Reset controller */
 328         writel(0, &twsi->soft_reset);
 329         /* Wait 2 ms -- this is what the Marvell LSP does */
 330         udelay(20000);
 331 }
 332
 333 /*
 334  * Sets baud to the highest possible value not exceeding the requested one.
 335  */
 336 static uint __twsi_i2c_set_bus_speed(struct mvtwsi_registers *twsi,
 337                                      uint requested_speed)
 338 {
 339         uint tmp_speed, highest_speed, n, m;
 340         uint baud = 0x44; /* Baud rate after controller reset */
 341
 342         highest_speed = 0;
 343         /* Successively try m, n combinations, and use the combination
 344          * resulting in the largest speed that's not above the requested
 345          * speed */
 346         for (n = 0; n < 8; n++) {
 347                 for (m = 0; m < 16; m++) {
 348                         tmp_speed = twsi_calc_freq(n, m);
 349                         if ((tmp_speed <= requested_speed) &&
 350                             (tmp_speed > highest_speed)) {
 351                                 highest_speed = tmp_speed;
 352                                 baud = (m << 3) | n;
 353                         }
 354                 }
 355         }
 356         writel(baud, &twsi->baudrate);
 357         return 0;
 358 }
 359
 360 static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed,
 361                           int slaveadd)
 362 {
 363         /* Reset controller */
 364         twsi_reset(twsi);
 365         /* Set speed */
 366         __twsi_i2c_set_bus_speed(twsi, speed);
 367         /* Set slave address; even though we don't use it */
 368         writel(slaveadd, &twsi->slave_address);
 369         writel(0, &twsi->xtnd_slave_addr);
 370         /* Assert STOP, but don't care for the result */
 371         (void) twsi_stop(twsi);
 372 }
 373
 374 /*
 375  * Begin I2C transaction with expected start status, at given address.
 376  * Expected address status will derive from direction bit (bit 0) in addr.
 377  */
 378 static int i2c_begin(struct mvtwsi_registers *twsi, int expected_start_status,
 379                      u8 addr)
 380 {
 381         int status, expected_addr_status;
 382
 383         /* Compute the expected address status from the direction bit in
 384          * the address byte */
 385         if (addr & 1) /* Reading */
 386                 expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK;
 387         else /* Writing */
 388                 expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK;
 389         /* Assert START */
 390         status = twsi_start(twsi, expected_start_status);
 391         /* Send out the address if the start went well */
 392         if (status == 0)
 393                 status = twsi_send(twsi, addr, expected_addr_status);
 394         /* Return 0, or the status of the first failure */
 395         return status;
 396 }
 397
 398 /*
 399  * Begin read, nak data byte, end.
 400  */
 401 static int __twsi_i2c_probe_chip(struct mvtwsi_registers *twsi, uchar chip)
 402 {
 403         u8 dummy_byte;
 404         int status;
 405
 406         /* Begin i2c read */
 407         status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1) | 1);
 408         /* Dummy read was accepted: receive byte, but NAK it. */
 409         if (status == 0)
 410                 status = twsi_recv(twsi, &dummy_byte, MVTWSI_READ_NAK);
 411         /* Stop transaction */
 412         twsi_stop(twsi);
 413         /* Return 0, or the status of the first failure */
 414         return status;
 415 }
 416
 417 /*
 418  * Begin write, send address byte(s), begin read, receive data bytes, end.
 419  *
 420  * NOTE: Some devices want a stop right before the second start, while some
 421  * will choke if it is there. Since deciding this is not yet supported in
 422  * higher level APIs, we need to make a decision here, and for the moment that
 423  * will be a repeated start without a preceding stop.
 424  */
 425 static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip,
 426                            uint addr, int alen, uchar *data, int length)
 427 {
 428         int status = 0;
 429         int stop_status;
 430
 431         /* Begin i2c write to send the address bytes */
 432         status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1));
 433         /* Send address bytes */
 434         while ((status == 0) && alen--)
 435                 status = twsi_send(twsi, addr >> (8*alen),
 436                         MVTWSI_STATUS_DATA_W_ACK);
 437         /* Begin i2c read to receive data bytes */
 438         if (status == 0)
 439                 status = i2c_begin(twsi, MVTWSI_STATUS_REPEATED_START,
 440                                    (chip << 1) | 1);
 441         /* Receive actual data bytes; set NAK if we if we have nothing more to
 442          * read */
 443         while ((status == 0) && length--)
 444                 status = twsi_recv(twsi, data++,
 445                                    length > 0 ?
 446                                    MVTWSI_READ_ACK : MVTWSI_READ_NAK);
 447         /* Stop transaction */
 448         stop_status = twsi_stop(twsi);
 449         /* Return 0, or the status of the first failure */
 450         return status != 0 ? status : stop_status;
 451 }
 452
 453 /*
 454  * Begin write, send address byte(s), send data bytes, end.
 455  */
 456 static int __twsi_i2c_write(struct mvtwsi_registers *twsi, uchar chip,
 457                             uint addr, int alen, uchar *data, int length)
 458 {
 459         int status, stop_status;
 460
 461         /* Begin i2c write to send first the address bytes, then the
 462          * data bytes */
 463         status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1));
 464         /* Send address bytes */
 465         while ((status == 0) && alen--)
 466                 status = twsi_send(twsi, addr >> (8*alen),
 467                         MVTWSI_STATUS_DATA_W_ACK);
 468         /* Send data bytes */
 469         while ((status == 0) && (length-- > 0))
 470                 status = twsi_send(twsi, *(data++), MVTWSI_STATUS_DATA_W_ACK);
 471         /* Stop transaction */
 472         stop_status = twsi_stop(twsi);
 473         /* Return 0, or the status of the first failure */
 474         return status != 0 ? status : stop_status;
 475 }
 476
 477 static void twsi_i2c_init(struct i2c_adapter *adap, int speed,
 478                           int slaveadd)
 479 {
 480         struct mvtwsi_registers *twsi = twsi_get_base(adap);
 481         __twsi_i2c_init(twsi, speed, slaveadd);
 482 }
 483
 484 static uint twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
 485                                    uint requested_speed)
 486 {
 487         struct mvtwsi_registers *twsi = twsi_get_base(adap);
 488         return __twsi_i2c_set_bus_speed(twsi, requested_speed);
 489 }
 490
 491 static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
 492 {
 493         struct mvtwsi_registers *twsi = twsi_get_base(adap);
 494         return __twsi_i2c_probe_chip(twsi, chip);
 495 }
 496
 497 static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 498                          int alen, uchar *data, int length)
 499 {
 500         struct mvtwsi_registers *twsi = twsi_get_base(adap);
 501         return __twsi_i2c_read(twsi, chip, addr, alen, data, length);
 502 }
 503
 504 static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 505                           int alen, uchar *data, int length)
 506 {
 507         struct mvtwsi_registers *twsi = twsi_get_base(adap);
 508         return __twsi_i2c_write(twsi, chip, addr, alen, data, length);
 509 }
 510
 511 #ifdef CONFIG_I2C_MVTWSI_BASE0
 512 U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe,
 513                          twsi_i2c_read, twsi_i2c_write,
 514                          twsi_i2c_set_bus_speed,
 515                          CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
 516 #endif
 517 #ifdef CONFIG_I2C_MVTWSI_BASE1
 518 U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe,
 519                          twsi_i2c_read, twsi_i2c_write,
 520                          twsi_i2c_set_bus_speed,
 521                          CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1)
 522
 523 #endif
 524 #ifdef CONFIG_I2C_MVTWSI_BASE2
 525 U_BOOT_I2C_ADAP_COMPLETE(twsi2, twsi_i2c_init, twsi_i2c_probe,
 526                          twsi_i2c_read, twsi_i2c_write,
 527                          twsi_i2c_set_bus_speed,
 528                          CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 2)
 529
 530 #endif
 531 #ifdef CONFIG_I2C_MVTWSI_BASE3
 532 U_BOOT_I2C_ADAP_COMPLETE(twsi3, twsi_i2c_init, twsi_i2c_probe,
 533                          twsi_i2c_read, twsi_i2c_write,
 534                          twsi_i2c_set_bus_speed,
 535                          CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 3)
 536
 537 #endif
 538 #ifdef CONFIG_I2C_MVTWSI_BASE4
 539 U_BOOT_I2C_ADAP_COMPLETE(twsi4, twsi_i2c_init, twsi_i2c_probe,
 540                          twsi_i2c_read, twsi_i2c_write,
 541                          twsi_i2c_set_bus_speed,
 542                          CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4)
 543
 544 #endif
 545 #ifdef CONFIG_I2C_MVTWSI_BASE5
 546 U_BOOT_I2C_ADAP_COMPLETE(twsi5, twsi_i2c_init, twsi_i2c_probe,
 547                          twsi_i2c_read, twsi_i2c_write,
 548                          twsi_i2c_set_bus_speed,
 549                          CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 5)
 550
 551 #endif