2 * (C) Copyright 2007-2009
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * based on work by Anne Sophie Harnois <anne-sophie.harnois@nextream.fr>
8 * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net
10 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/ppc4xx.h>
15 #include <asm/ppc4xx-i2c.h>
19 DECLARE_GLOBAL_DATA_PTR
;
21 static inline struct ppc4xx_i2c
*ppc4xx_get_i2c(int hwadapnr
)
25 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
26 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
27 defined(CONFIG_460EX) || defined(CONFIG_460GT)
28 base
= CONFIG_SYS_PERIPHERAL_BASE
+ 0x00000700 + (hwadapnr
* 0x100);
29 #elif defined(CONFIG_440) || defined(CONFIG_405EX)
30 /* all remaining 440 variants */
31 base
= CONFIG_SYS_PERIPHERAL_BASE
+ 0x00000400 + (hwadapnr
* 0x100);
33 /* all 405 variants */
34 base
= 0xEF600500 + (hwadapnr
* 0x100);
36 return (struct ppc4xx_i2c
*)base
;
39 static void _i2c_bus_reset(struct i2c_adapter
*adap
)
41 struct ppc4xx_i2c
*i2c
= ppc4xx_get_i2c(adap
->hwadapnr
);
45 /* Reset status register */
46 /* write 1 in SCMP and IRQA to clear these fields */
47 out_8(&i2c
->sts
, 0x0A);
49 /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
50 out_8(&i2c
->extsts
, 0x8F);
52 /* Place chip in the reset state */
53 out_8(&i2c
->xtcntlss
, IIC_XTCNTLSS_SRST
);
55 /* Check if bus is free */
56 dc
= in_8(&i2c
->directcntl
);
57 if (!DIRCTNL_FREE(dc
)){
58 /* Try to set bus free state */
59 out_8(&i2c
->directcntl
, IIC_DIRCNTL_SDAC
| IIC_DIRCNTL_SCC
);
61 /* Wait until we regain bus control */
62 for (i
= 0; i
< 100; ++i
) {
63 dc
= in_8(&i2c
->directcntl
);
68 dc
^= IIC_DIRCNTL_SCC
;
69 out_8(&i2c
->directcntl
, dc
);
71 dc
^= IIC_DIRCNTL_SCC
;
72 out_8(&i2c
->directcntl
, dc
);
77 out_8(&i2c
->xtcntlss
, 0);
80 static void ppc4xx_i2c_init(struct i2c_adapter
*adap
, int speed
, int slaveaddr
)
82 struct ppc4xx_i2c
*i2c
= ppc4xx_get_i2c(adap
->hwadapnr
);
85 #ifdef CONFIG_SYS_I2C_INIT_BOARD
87 * Call board specific i2c bus reset routine before accessing the
88 * environment, which might be in a chip on that bus. For details
89 * about this problem see doc/I2C_Edge_Conditions.
94 /* Handle possible failed I2C state */
95 /* FIXME: put this into i2c_init_board()? */
98 /* clear lo master address */
99 out_8(&i2c
->lmadr
, 0);
101 /* clear hi master address */
102 out_8(&i2c
->hmadr
, 0);
104 /* clear lo slave address */
105 out_8(&i2c
->lsadr
, 0);
107 /* clear hi slave address */
108 out_8(&i2c
->hsadr
, 0);
110 /* Clock divide Register */
111 /* set divisor according to freq_opb */
112 divisor
= (get_OPB_freq() - 1) / 10000000;
115 out_8(&i2c
->clkdiv
, divisor
);
118 out_8(&i2c
->intrmsk
, 0);
120 /* clear transfer count */
121 out_8(&i2c
->xfrcnt
, 0);
123 /* clear extended control & stat */
124 /* write 1 in SRC SRS SWC SWS to clear these fields */
125 out_8(&i2c
->xtcntlss
, 0xF0);
127 /* Mode Control Register
128 Flush Slave/Master data buffer */
129 out_8(&i2c
->mdcntl
, IIC_MDCNTL_FSDB
| IIC_MDCNTL_FMDB
);
131 val
= in_8(&i2c
->mdcntl
);
133 /* Ignore General Call, slave transfers are ignored,
134 * disable interrupts, exit unknown bus state, enable hold
135 * SCL 100kHz normaly or FastMode for 400kHz and above
138 val
|= IIC_MDCNTL_EUBS
| IIC_MDCNTL_HSCL
;
140 val
|= IIC_MDCNTL_FSM
;
141 out_8(&i2c
->mdcntl
, val
);
143 /* clear control reg */
144 out_8(&i2c
->cntl
, 0x00);
148 * This code tries to use the features of the 405GP i2c
149 * controller. It will transfer up to 4 bytes in one pass
150 * on the loop. It only does out_8((u8 *)lbz) to the buffer when it
151 * is possible to do out16(lhz) transfers.
153 * cmd_type is 0 for write 1 for read.
155 * addr_len can take any value from 0-255, it is only limited
156 * by the char, we could make it larger if needed. If it is
157 * 0 we skip the address write cycle.
159 * Typical case is a Write of an addr followd by a Read. The
160 * IBM FAQ does not cover this. On the last byte of the write
161 * we don't set the creg CHT bit but the RPST bit.
163 * It does not support address only transfers, there must be
164 * a data part. If you want to write the address yourself, put
165 * it in the data pointer.
167 * It does not support transfer to/from address 0.
169 * It does not check XFRCNT.
171 static int _i2c_transfer(struct i2c_adapter
*adap
,
172 unsigned char cmd_type
,
174 unsigned char addr
[],
175 unsigned char addr_len
,
176 unsigned char data
[],
177 unsigned short data_len
)
179 struct ppc4xx_i2c
*i2c
= ppc4xx_get_i2c(adap
->hwadapnr
);
188 if (data
== 0 || data_len
== 0) {
189 /* Don't support data transfer of no length or to address 0 */
190 printf( "i2c_transfer: bad call\n" );
193 if (addr
&& addr_len
) {
203 /* Clear Stop Complete Bit */
204 out_8(&i2c
->sts
, IIC_STS_SCMP
);
210 status
= in_8(&i2c
->sts
);
212 } while ((status
& IIC_STS_PT
) && (i
> 0));
214 if (status
& IIC_STS_PT
) {
215 result
= IIC_NOK_TOUT
;
219 /* flush the Master/Slave Databuffers */
220 out_8(&i2c
->mdcntl
, in_8(&i2c
->mdcntl
) |
221 IIC_MDCNTL_FMDB
| IIC_MDCNTL_FSDB
);
223 /* need to wait 4 OPB clocks? code below should take that long */
225 /* 7-bit adressing */
226 out_8(&i2c
->hmadr
, 0);
227 out_8(&i2c
->lmadr
, chip
);
233 while (tran
!= cnt
&& (result
== IIC_OK
)) {
238 * Normal transfer, 7-bits adressing, Transfer up to
239 * bc bytes, Normal start, Transfer is a sequence of transfers
243 bc
= (cnt
- tran
) > 4 ? 4 : cnt
- tran
;
244 creg
|= (bc
- 1) << 4;
245 /* if the real cmd type is write continue trans */
246 if ((!cmd_type
&& (ptr
== addr
)) || ((tran
+ bc
) != cnt
))
247 creg
|= IIC_CNTL_CHT
;
249 /* last part of address, prepare for repeated start on read */
250 if (cmd_type
&& (ptr
== addr
) && ((tran
+ bc
) == cnt
))
251 creg
|= IIC_CNTL_RPST
;
254 creg
|= IIC_CNTL_READ
;
256 for(j
= 0; j
< bc
; j
++) {
258 out_8(&i2c
->mdbuf
, ptr
[tran
+ j
]);
261 out_8(&i2c
->cntl
, creg
);
264 * Transfer is in progress
265 * we have to wait for upto 5 bytes of data
266 * 1 byte chip address+r/w bit then bc bytes
268 * udelay(10) is 1 bit time at 100khz
269 * Doubled for slop. 20 is too small.
274 status
= in_8(&i2c
->sts
);
277 } while ((status
& IIC_STS_PT
) && !(status
& IIC_STS_ERR
) &&
280 if (status
& IIC_STS_ERR
) {
282 status
= in_8(&i2c
->extsts
);
283 /* Lost arbitration? */
284 if (status
& IIC_EXTSTS_LA
)
286 /* Incomplete transfer? */
287 if (status
& IIC_EXTSTS_ICT
)
288 result
= IIC_NOK_ICT
;
289 /* Transfer aborted? */
290 if (status
& IIC_EXTSTS_XFRA
)
291 result
= IIC_NOK_XFRA
;
293 * If error happened during combined xfer
294 * IIC interface is usually stuck in some strange
295 * state without a valid stop condition.
296 * Brute, but working: generate stop, then soft reset.
298 if ((status
& IIC_EXTSTS_BCS_MASK
)
299 != IIC_EXTSTS_BCS_FREE
){
300 u8 mdcntl
= in_8(&i2c
->mdcntl
);
302 /* Generate valid stop condition */
303 out_8(&i2c
->xtcntlss
, IIC_XTCNTLSS_SRST
);
304 out_8(&i2c
->directcntl
, IIC_DIRCNTL_SCC
);
306 out_8(&i2c
->directcntl
,
307 IIC_DIRCNTL_SCC
| IIC_DIRCNTL_SDAC
);
308 out_8(&i2c
->xtcntlss
, 0);
310 ppc4xx_i2c_init(adap
, (mdcntl
& IIC_MDCNTL_FSM
)
311 ? 400000 : 100000, 0);
313 } else if ( status
& IIC_STS_PT
) {
314 result
= IIC_NOK_TOUT
;
317 /* Command is reading => get buffer */
318 if ((reading
) && (result
== IIC_OK
)) {
319 /* Are there data in buffer */
320 if (status
& IIC_STS_MDBS
) {
322 * even if we have data we have to wait 4OPB
323 * clocks for it to hit the front of the FIFO,
324 * after that we can just read. We should check
325 * XFCNT here and if the FIFO is full there is
329 for (j
= 0; j
< bc
; j
++)
330 ptr
[tran
+ j
] = in_8(&i2c
->mdbuf
);
332 result
= IIC_NOK_DATA
;
336 if (ptr
== addr
&& tran
== cnt
) {
346 static int ppc4xx_i2c_probe(struct i2c_adapter
*adap
, uchar chip
)
353 * What is needed is to send the chip address and verify that the
354 * address was <ACK>ed (i.e. there was a chip at that address which
355 * drove the data line low).
357 return (_i2c_transfer(adap
, 1, chip
<< 1, 0, 0, buf
, 1) != 0);
360 static int ppc4xx_i2c_transfer(struct i2c_adapter
*adap
, uchar chip
, uint addr
,
361 int alen
, uchar
*buffer
, int len
, int read
)
367 printf("I2C: addr len %d not supported\n", alen
);
372 xaddr
[0] = (addr
>> 24) & 0xFF;
373 xaddr
[1] = (addr
>> 16) & 0xFF;
374 xaddr
[2] = (addr
>> 8) & 0xFF;
375 xaddr
[3] = addr
& 0xFF;
379 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
381 * EEPROM chips that implement "address overflow" are ones
382 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
383 * address and the extra bits end up in the "chip address"
384 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
385 * four 256 byte chips.
387 * Note that we consider the length of the address field to
388 * still be one byte because the extra address bits are
389 * hidden in the chip address.
392 chip
|= ((addr
>> (alen
* 8)) &
393 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
);
395 ret
= _i2c_transfer(adap
, read
, chip
<< 1, &xaddr
[4 - alen
], alen
,
398 printf("I2C %s: failed %d\n", read
? "read" : "write", ret
);
405 static int ppc4xx_i2c_read(struct i2c_adapter
*adap
, uchar chip
, uint addr
,
406 int alen
, uchar
*buffer
, int len
)
408 return ppc4xx_i2c_transfer(adap
, chip
, addr
, alen
, buffer
, len
, 1);
411 static int ppc4xx_i2c_write(struct i2c_adapter
*adap
, uchar chip
, uint addr
,
412 int alen
, uchar
*buffer
, int len
)
414 return ppc4xx_i2c_transfer(adap
, chip
, addr
, alen
, buffer
, len
, 0);
417 static unsigned int ppc4xx_i2c_set_bus_speed(struct i2c_adapter
*adap
,
420 if (speed
!= adap
->speed
)
426 * Register ppc4xx i2c adapters
428 #ifdef CONFIG_SYS_I2C_PPC4XX_CH0
429 U_BOOT_I2C_ADAP_COMPLETE(ppc4xx_0
, ppc4xx_i2c_init
, ppc4xx_i2c_probe
,
430 ppc4xx_i2c_read
, ppc4xx_i2c_write
,
431 ppc4xx_i2c_set_bus_speed
,
432 CONFIG_SYS_I2C_PPC4XX_SPEED_0
,
433 CONFIG_SYS_I2C_PPC4XX_SLAVE_0
, 0)
435 #ifdef CONFIG_SYS_I2C_PPC4XX_CH1
436 U_BOOT_I2C_ADAP_COMPLETE(ppc4xx_1
, ppc4xx_i2c_init
, ppc4xx_i2c_probe
,
437 ppc4xx_i2c_read
, ppc4xx_i2c_write
,
438 ppc4xx_i2c_set_bus_speed
,
439 CONFIG_SYS_I2C_PPC4XX_SPEED_1
,
440 CONFIG_SYS_I2C_PPC4XX_SLAVE_1
, 1)