2 * Freescale i.MX28 OCOTP Driver
4 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
8 * Note: The i.MX23/i.MX28 OCOTP block is a predecessor to the OCOTP block
9 * used in i.MX6 . While these blocks are very similar at the first
10 * glance, by digging deeper, one will notice differences (like the
11 * tight dependence on MXS power block, some completely new registers
12 * etc.) which would make common driver an ifdef nightmare :-(
17 #include <linux/errno.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/imx-regs.h>
21 #include <asm/arch/sys_proto.h>
23 #define MXS_OCOTP_TIMEOUT 100000
25 static struct mxs_ocotp_regs
*ocotp_regs
=
26 (struct mxs_ocotp_regs
*)MXS_OCOTP_BASE
;
27 static struct mxs_power_regs
*power_regs
=
28 (struct mxs_power_regs
*)MXS_POWER_BASE
;
29 static struct mxs_clkctrl_regs
*clkctrl_regs
=
30 (struct mxs_clkctrl_regs
*)MXS_CLKCTRL_BASE
;
32 static int mxs_ocotp_wait_busy_clear(void)
35 int timeout
= MXS_OCOTP_TIMEOUT
;
38 reg
= readl(&ocotp_regs
->hw_ocotp_ctrl
);
39 if (!(reg
& OCOTP_CTRL_BUSY
))
47 /* Wait a little as per FSL datasheet's 'write postamble' section. */
53 static void mxs_ocotp_clear_error(void)
55 writel(OCOTP_CTRL_ERROR
, &ocotp_regs
->hw_ocotp_ctrl_clr
);
58 static int mxs_ocotp_read_bank_open(bool open
)
63 writel(OCOTP_CTRL_RD_BANK_OPEN
,
64 &ocotp_regs
->hw_ocotp_ctrl_set
);
67 * Wait before polling the BUSY bit, since the BUSY bit might
68 * be asserted only after a few HCLK cycles and if we were to
69 * poll immediatelly, we could miss the busy bit.
72 ret
= mxs_ocotp_wait_busy_clear();
74 writel(OCOTP_CTRL_RD_BANK_OPEN
,
75 &ocotp_regs
->hw_ocotp_ctrl_clr
);
81 static void mxs_ocotp_scale_vddio(bool enter
, uint32_t *val
)
87 * Enter the fuse programming VDDIO voltage setup. We start
88 * scaling the voltage from it's current value down to 2.8V
89 * which is the one and only correct voltage for programming
90 * the OCOTP fuses (according to datasheet).
92 scale_val
= readl(&power_regs
->hw_power_vddioctrl
);
93 scale_val
&= POWER_VDDIOCTRL_TRG_MASK
;
95 /* Return the original voltage. */
99 * Start scaling VDDIO down to 0x2, which is 2.8V . Actually,
100 * the value 0x0 should be 2.8V, but that's not the case on
101 * most designs due to load etc., so we play safe. Undervolt
102 * can actually cause incorrect programming of the fuses and
103 * or reboots of the board.
105 while (scale_val
> 2) {
106 clrsetbits_le32(&power_regs
->hw_power_vddioctrl
,
107 POWER_VDDIOCTRL_TRG_MASK
, --scale_val
);
111 /* Start scaling VDDIO up to original value . */
112 for (scale_val
= 2; scale_val
<= *val
; scale_val
++) {
113 clrsetbits_le32(&power_regs
->hw_power_vddioctrl
,
114 POWER_VDDIOCTRL_TRG_MASK
, scale_val
);
122 static int mxs_ocotp_wait_hclk_ready(void)
124 uint32_t reg
, timeout
= MXS_OCOTP_TIMEOUT
;
127 reg
= readl(&clkctrl_regs
->hw_clkctrl_hbus
);
128 if (!(reg
& CLKCTRL_HBUS_ASM_BUSY
))
138 static int mxs_ocotp_scale_hclk(bool enter
, uint32_t *val
)
143 ret
= mxs_ocotp_wait_hclk_ready();
148 writel(CLKCTRL_CLKSEQ_BYPASS_CPU
,
149 &clkctrl_regs
->hw_clkctrl_clkseq_set
);
152 /* Return the original HCLK clock speed. */
153 *val
= readl(&clkctrl_regs
->hw_clkctrl_hbus
);
154 *val
&= CLKCTRL_HBUS_DIV_MASK
;
155 *val
>>= CLKCTRL_HBUS_DIV_OFFSET
;
157 /* Scale the HCLK to 454/19 = 23.9 MHz . */
158 scale_val
= (~19) << CLKCTRL_HBUS_DIV_OFFSET
;
159 scale_val
&= CLKCTRL_HBUS_DIV_MASK
;
161 /* Scale the HCLK back to original frequency. */
162 scale_val
= (~(*val
)) << CLKCTRL_HBUS_DIV_OFFSET
;
163 scale_val
&= CLKCTRL_HBUS_DIV_MASK
;
166 writel(CLKCTRL_HBUS_DIV_MASK
,
167 &clkctrl_regs
->hw_clkctrl_hbus_set
);
169 &clkctrl_regs
->hw_clkctrl_hbus_clr
);
173 ret
= mxs_ocotp_wait_hclk_ready();
177 /* Disable CPU bypass */
178 writel(CLKCTRL_CLKSEQ_BYPASS_CPU
,
179 &clkctrl_regs
->hw_clkctrl_clkseq_clr
);
186 static int mxs_ocotp_write_fuse(uint32_t addr
, uint32_t mask
)
188 uint32_t hclk_val
, vddio_val
;
191 mxs_ocotp_clear_error();
193 /* Make sure the banks are closed for reading. */
194 ret
= mxs_ocotp_read_bank_open(0);
196 puts("Failed closing banks for reading!\n");
200 ret
= mxs_ocotp_scale_hclk(1, &hclk_val
);
202 puts("Failed scaling down the HCLK!\n");
205 mxs_ocotp_scale_vddio(1, &vddio_val
);
207 ret
= mxs_ocotp_wait_busy_clear();
209 puts("Failed waiting for ready state!\n");
213 /* Program the fuse address */
214 writel(addr
| OCOTP_CTRL_WR_UNLOCK_KEY
, &ocotp_regs
->hw_ocotp_ctrl
);
216 /* Program the data. */
217 writel(mask
, &ocotp_regs
->hw_ocotp_data
);
221 ret
= mxs_ocotp_wait_busy_clear();
223 puts("Failed waiting for ready state!\n");
227 /* Check for errors */
228 if (readl(&ocotp_regs
->hw_ocotp_ctrl
) & OCOTP_CTRL_ERROR
) {
229 puts("Failed writing fuses!\n");
235 mxs_ocotp_scale_vddio(0, &vddio_val
);
236 if (mxs_ocotp_scale_hclk(0, &hclk_val
))
237 puts("Failed scaling up the HCLK!\n");
242 static int mxs_ocotp_read_fuse(uint32_t reg
, uint32_t *val
)
246 /* Register offset from CUST0 */
247 reg
= ((uint32_t)&ocotp_regs
->hw_ocotp_cust0
) + (reg
<< 4);
249 ret
= mxs_ocotp_wait_busy_clear();
251 puts("Failed waiting for ready state!\n");
255 mxs_ocotp_clear_error();
257 ret
= mxs_ocotp_read_bank_open(1);
259 puts("Failed opening banks for reading!\n");
265 ret
= mxs_ocotp_read_bank_open(0);
267 puts("Failed closing banks for reading!\n");
274 static int mxs_ocotp_valid(u32 bank
, u32 word
)
284 * The 'fuse' command API
286 int fuse_read(u32 bank
, u32 word
, u32
*val
)
290 ret
= mxs_ocotp_valid(bank
, word
);
294 return mxs_ocotp_read_fuse((bank
<< 3) | word
, val
);
297 int fuse_prog(u32 bank
, u32 word
, u32 val
)
301 ret
= mxs_ocotp_valid(bank
, word
);
305 return mxs_ocotp_write_fuse((bank
<< 3) | word
, val
);
308 int fuse_sense(u32 bank
, u32 word
, u32
*val
)
310 /* We do not support sensing :-( */
314 int fuse_override(u32 bank
, u32 word
, u32 val
)
316 /* We do not support overriding :-( */