2 * (C) Copyright 2012 SAMSUNG Electronics
3 * Jaehoon Chung <jh80.chung@samsung.com>
4 * Rajeshawari Shinde <rajeshwari.s@samsung.com>
6 * SPDX-License-Identifier: GPL-2.0+
17 #define PAGE_SIZE 4096
19 static int dwmci_wait_reset(struct dwmci_host
*host
, u32 value
)
21 unsigned long timeout
= 1000;
24 dwmci_writel(host
, DWMCI_CTRL
, value
);
27 ctrl
= dwmci_readl(host
, DWMCI_CTRL
);
28 if (!(ctrl
& DWMCI_RESET_ALL
))
34 static void dwmci_set_idma_desc(struct dwmci_idmac
*idmac
,
35 u32 desc0
, u32 desc1
, u32 desc2
)
37 struct dwmci_idmac
*desc
= idmac
;
42 desc
->next_addr
= (ulong
)desc
+ sizeof(struct dwmci_idmac
);
45 static void dwmci_prepare_data(struct dwmci_host
*host
,
46 struct mmc_data
*data
,
47 struct dwmci_idmac
*cur_idmac
,
51 unsigned int i
= 0, flags
, cnt
, blk_cnt
;
52 ulong data_start
, data_end
;
55 blk_cnt
= data
->blocks
;
57 dwmci_wait_reset(host
, DWMCI_CTRL_FIFO_RESET
);
59 data_start
= (ulong
)cur_idmac
;
60 dwmci_writel(host
, DWMCI_DBADDR
, (ulong
)cur_idmac
);
63 flags
= DWMCI_IDMAC_OWN
| DWMCI_IDMAC_CH
;
64 flags
|= (i
== 0) ? DWMCI_IDMAC_FS
: 0;
66 flags
|= DWMCI_IDMAC_LD
;
67 cnt
= data
->blocksize
* blk_cnt
;
69 cnt
= data
->blocksize
* 8;
71 dwmci_set_idma_desc(cur_idmac
, flags
, cnt
,
72 (ulong
)bounce_buffer
+ (i
* PAGE_SIZE
));
81 data_end
= (ulong
)cur_idmac
;
82 flush_dcache_range(data_start
, data_end
+ ARCH_DMA_MINALIGN
);
84 ctrl
= dwmci_readl(host
, DWMCI_CTRL
);
85 ctrl
|= DWMCI_IDMAC_EN
| DWMCI_DMA_EN
;
86 dwmci_writel(host
, DWMCI_CTRL
, ctrl
);
88 ctrl
= dwmci_readl(host
, DWMCI_BMOD
);
89 ctrl
|= DWMCI_BMOD_IDMAC_FB
| DWMCI_BMOD_IDMAC_EN
;
90 dwmci_writel(host
, DWMCI_BMOD
, ctrl
);
92 dwmci_writel(host
, DWMCI_BLKSIZ
, data
->blocksize
);
93 dwmci_writel(host
, DWMCI_BYTCNT
, data
->blocksize
* data
->blocks
);
96 static int dwmci_data_transfer(struct dwmci_host
*host
, struct mmc_data
*data
)
100 u32 mask
, size
, i
, len
= 0;
102 ulong start
= get_timer(0);
103 u32 fifo_depth
= (((host
->fifoth_val
& RX_WMARK_MASK
) >>
104 RX_WMARK_SHIFT
) + 1) * 2;
106 size
= data
->blocksize
* data
->blocks
/ 4;
107 if (data
->flags
== MMC_DATA_READ
)
108 buf
= (unsigned int *)data
->dest
;
110 buf
= (unsigned int *)data
->src
;
113 mask
= dwmci_readl(host
, DWMCI_RINTSTS
);
114 /* Error during data transfer. */
115 if (mask
& (DWMCI_DATA_ERR
| DWMCI_DATA_TOUT
)) {
116 debug("%s: DATA ERROR!\n", __func__
);
121 if (host
->fifo_mode
&& size
) {
122 if (data
->flags
== MMC_DATA_READ
) {
123 if ((dwmci_readl(host
, DWMCI_RINTSTS
) &
124 DWMCI_INTMSK_RXDR
)) {
125 len
= dwmci_readl(host
, DWMCI_STATUS
);
126 len
= (len
>> DWMCI_FIFO_SHIFT
) &
128 for (i
= 0; i
< len
; i
++)
130 dwmci_readl(host
, DWMCI_DATA
);
131 dwmci_writel(host
, DWMCI_RINTSTS
,
135 if ((dwmci_readl(host
, DWMCI_RINTSTS
) &
136 DWMCI_INTMSK_TXDR
)) {
137 len
= dwmci_readl(host
, DWMCI_STATUS
);
138 len
= fifo_depth
- ((len
>>
141 for (i
= 0; i
< len
; i
++)
142 dwmci_writel(host
, DWMCI_DATA
,
144 dwmci_writel(host
, DWMCI_RINTSTS
,
148 size
= size
> len
? (size
- len
) : 0;
151 /* Data arrived correctly. */
152 if (mask
& DWMCI_INTMSK_DTO
) {
157 /* Check for timeout. */
158 if (get_timer(start
) > timeout
) {
159 debug("%s: Timeout waiting for data!\n",
166 dwmci_writel(host
, DWMCI_RINTSTS
, mask
);
171 static int dwmci_set_transfer_mode(struct dwmci_host
*host
,
172 struct mmc_data
*data
)
176 mode
= DWMCI_CMD_DATA_EXP
;
177 if (data
->flags
& MMC_DATA_WRITE
)
178 mode
|= DWMCI_CMD_RW
;
183 #ifdef CONFIG_DM_MMC_OPS
184 static int dwmci_send_cmd(struct udevice
*dev
, struct mmc_cmd
*cmd
,
185 struct mmc_data
*data
)
187 struct mmc
*mmc
= mmc_get_mmc_dev(dev
);
189 static int dwmci_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*cmd
,
190 struct mmc_data
*data
)
193 struct dwmci_host
*host
= mmc
->priv
;
194 ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac
, cur_idmac
,
195 data
? DIV_ROUND_UP(data
->blocks
, 8) : 0);
196 int ret
= 0, flags
= 0, i
;
197 unsigned int timeout
= 500;
200 ulong start
= get_timer(0);
201 struct bounce_buffer bbstate
;
203 while (dwmci_readl(host
, DWMCI_STATUS
) & DWMCI_BUSY
) {
204 if (get_timer(start
) > timeout
) {
205 debug("%s: Timeout on data busy\n", __func__
);
210 dwmci_writel(host
, DWMCI_RINTSTS
, DWMCI_INTMSK_ALL
);
213 if (host
->fifo_mode
) {
214 dwmci_writel(host
, DWMCI_BLKSIZ
, data
->blocksize
);
215 dwmci_writel(host
, DWMCI_BYTCNT
,
216 data
->blocksize
* data
->blocks
);
217 dwmci_wait_reset(host
, DWMCI_CTRL_FIFO_RESET
);
219 if (data
->flags
== MMC_DATA_READ
) {
220 bounce_buffer_start(&bbstate
, (void*)data
->dest
,
222 data
->blocks
, GEN_BB_WRITE
);
224 bounce_buffer_start(&bbstate
, (void*)data
->src
,
226 data
->blocks
, GEN_BB_READ
);
228 dwmci_prepare_data(host
, data
, cur_idmac
,
229 bbstate
.bounce_buffer
);
233 dwmci_writel(host
, DWMCI_CMDARG
, cmd
->cmdarg
);
236 flags
= dwmci_set_transfer_mode(host
, data
);
238 if ((cmd
->resp_type
& MMC_RSP_136
) && (cmd
->resp_type
& MMC_RSP_BUSY
))
241 if (cmd
->cmdidx
== MMC_CMD_STOP_TRANSMISSION
)
242 flags
|= DWMCI_CMD_ABORT_STOP
;
244 flags
|= DWMCI_CMD_PRV_DAT_WAIT
;
246 if (cmd
->resp_type
& MMC_RSP_PRESENT
) {
247 flags
|= DWMCI_CMD_RESP_EXP
;
248 if (cmd
->resp_type
& MMC_RSP_136
)
249 flags
|= DWMCI_CMD_RESP_LENGTH
;
252 if (cmd
->resp_type
& MMC_RSP_CRC
)
253 flags
|= DWMCI_CMD_CHECK_CRC
;
255 flags
|= (cmd
->cmdidx
| DWMCI_CMD_START
| DWMCI_CMD_USE_HOLD_REG
);
257 debug("Sending CMD%d\n",cmd
->cmdidx
);
259 dwmci_writel(host
, DWMCI_CMD
, flags
);
261 for (i
= 0; i
< retry
; i
++) {
262 mask
= dwmci_readl(host
, DWMCI_RINTSTS
);
263 if (mask
& DWMCI_INTMSK_CDONE
) {
265 dwmci_writel(host
, DWMCI_RINTSTS
, mask
);
271 debug("%s: Timeout.\n", __func__
);
275 if (mask
& DWMCI_INTMSK_RTO
) {
277 * Timeout here is not necessarily fatal. (e)MMC cards
278 * will splat here when they receive CMD55 as they do
279 * not support this command and that is exactly the way
280 * to tell them apart from SD cards. Thus, this output
281 * below shall be debug(). eMMC cards also do not favor
282 * CMD8, please keep that in mind.
284 debug("%s: Response Timeout.\n", __func__
);
286 } else if (mask
& DWMCI_INTMSK_RE
) {
287 debug("%s: Response Error.\n", __func__
);
292 if (cmd
->resp_type
& MMC_RSP_PRESENT
) {
293 if (cmd
->resp_type
& MMC_RSP_136
) {
294 cmd
->response
[0] = dwmci_readl(host
, DWMCI_RESP3
);
295 cmd
->response
[1] = dwmci_readl(host
, DWMCI_RESP2
);
296 cmd
->response
[2] = dwmci_readl(host
, DWMCI_RESP1
);
297 cmd
->response
[3] = dwmci_readl(host
, DWMCI_RESP0
);
299 cmd
->response
[0] = dwmci_readl(host
, DWMCI_RESP0
);
304 ret
= dwmci_data_transfer(host
, data
);
306 /* only dma mode need it */
307 if (!host
->fifo_mode
) {
308 ctrl
= dwmci_readl(host
, DWMCI_CTRL
);
309 ctrl
&= ~(DWMCI_DMA_EN
);
310 dwmci_writel(host
, DWMCI_CTRL
, ctrl
);
311 bounce_buffer_stop(&bbstate
);
320 static int dwmci_setup_bus(struct dwmci_host
*host
, u32 freq
)
326 if ((freq
== host
->clock
) || (freq
== 0))
329 * If host->get_mmc_clk isn't defined,
330 * then assume that host->bus_hz is source clock value.
331 * host->bus_hz should be set by user.
333 if (host
->get_mmc_clk
)
334 sclk
= host
->get_mmc_clk(host
, freq
);
335 else if (host
->bus_hz
)
338 debug("%s: Didn't get source clock value.\n", __func__
);
343 div
= 0; /* bypass mode */
345 div
= DIV_ROUND_UP(sclk
, 2 * freq
);
347 dwmci_writel(host
, DWMCI_CLKENA
, 0);
348 dwmci_writel(host
, DWMCI_CLKSRC
, 0);
350 dwmci_writel(host
, DWMCI_CLKDIV
, div
);
351 dwmci_writel(host
, DWMCI_CMD
, DWMCI_CMD_PRV_DAT_WAIT
|
352 DWMCI_CMD_UPD_CLK
| DWMCI_CMD_START
);
355 status
= dwmci_readl(host
, DWMCI_CMD
);
357 debug("%s: Timeout!\n", __func__
);
360 } while (status
& DWMCI_CMD_START
);
362 dwmci_writel(host
, DWMCI_CLKENA
, DWMCI_CLKEN_ENABLE
|
363 DWMCI_CLKEN_LOW_PWR
);
365 dwmci_writel(host
, DWMCI_CMD
, DWMCI_CMD_PRV_DAT_WAIT
|
366 DWMCI_CMD_UPD_CLK
| DWMCI_CMD_START
);
370 status
= dwmci_readl(host
, DWMCI_CMD
);
372 debug("%s: Timeout!\n", __func__
);
375 } while (status
& DWMCI_CMD_START
);
382 #ifdef CONFIG_DM_MMC_OPS
383 static int dwmci_set_ios(struct udevice
*dev
)
385 struct mmc
*mmc
= mmc_get_mmc_dev(dev
);
387 static void dwmci_set_ios(struct mmc
*mmc
)
390 struct dwmci_host
*host
= (struct dwmci_host
*)mmc
->priv
;
393 debug("Buswidth = %d, clock: %d\n", mmc
->bus_width
, mmc
->clock
);
395 dwmci_setup_bus(host
, mmc
->clock
);
396 switch (mmc
->bus_width
) {
398 ctype
= DWMCI_CTYPE_8BIT
;
401 ctype
= DWMCI_CTYPE_4BIT
;
404 ctype
= DWMCI_CTYPE_1BIT
;
408 dwmci_writel(host
, DWMCI_CTYPE
, ctype
);
410 regs
= dwmci_readl(host
, DWMCI_UHS_REG
);
412 regs
|= DWMCI_DDR_MODE
;
414 regs
&= ~DWMCI_DDR_MODE
;
416 dwmci_writel(host
, DWMCI_UHS_REG
, regs
);
420 #ifdef CONFIG_DM_MMC_OPS
425 static int dwmci_init(struct mmc
*mmc
)
427 struct dwmci_host
*host
= mmc
->priv
;
429 if (host
->board_init
)
430 host
->board_init(host
);
432 dwmci_writel(host
, DWMCI_PWREN
, 1);
434 if (!dwmci_wait_reset(host
, DWMCI_RESET_ALL
)) {
435 debug("%s[%d] Fail-reset!!\n", __func__
, __LINE__
);
439 /* Enumerate at 400KHz */
440 dwmci_setup_bus(host
, mmc
->cfg
->f_min
);
442 dwmci_writel(host
, DWMCI_RINTSTS
, 0xFFFFFFFF);
443 dwmci_writel(host
, DWMCI_INTMASK
, 0);
445 dwmci_writel(host
, DWMCI_TMOUT
, 0xFFFFFFFF);
447 dwmci_writel(host
, DWMCI_IDINTEN
, 0);
448 dwmci_writel(host
, DWMCI_BMOD
, 1);
450 if (!host
->fifoth_val
) {
453 fifo_size
= dwmci_readl(host
, DWMCI_FIFOTH
);
454 fifo_size
= ((fifo_size
& RX_WMARK_MASK
) >> RX_WMARK_SHIFT
) + 1;
455 host
->fifoth_val
= MSIZE(0x2) | RX_WMARK(fifo_size
/ 2 - 1) |
456 TX_WMARK(fifo_size
/ 2);
458 dwmci_writel(host
, DWMCI_FIFOTH
, host
->fifoth_val
);
460 dwmci_writel(host
, DWMCI_CLKENA
, 0);
461 dwmci_writel(host
, DWMCI_CLKSRC
, 0);
466 #ifdef CONFIG_DM_MMC_OPS
467 int dwmci_probe(struct udevice
*dev
)
469 struct mmc
*mmc
= mmc_get_mmc_dev(dev
);
471 return dwmci_init(mmc
);
474 const struct dm_mmc_ops dm_dwmci_ops
= {
475 .send_cmd
= dwmci_send_cmd
,
476 .set_ios
= dwmci_set_ios
,
480 static const struct mmc_ops dwmci_ops
= {
481 .send_cmd
= dwmci_send_cmd
,
482 .set_ios
= dwmci_set_ios
,
487 void dwmci_setup_cfg(struct mmc_config
*cfg
, const char *name
, int buswidth
,
488 uint caps
, u32 max_clk
, u32 min_clk
)
491 #ifndef CONFIG_DM_MMC_OPS
492 cfg
->ops
= &dwmci_ops
;
494 cfg
->f_min
= min_clk
;
495 cfg
->f_max
= max_clk
;
497 cfg
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
;
499 cfg
->host_caps
= caps
;
502 cfg
->host_caps
|= MMC_MODE_8BIT
;
503 cfg
->host_caps
&= ~MMC_MODE_4BIT
;
505 cfg
->host_caps
|= MMC_MODE_4BIT
;
506 cfg
->host_caps
&= ~MMC_MODE_8BIT
;
508 cfg
->host_caps
|= MMC_MODE_HS
| MMC_MODE_HS_52MHz
;
510 cfg
->b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
514 int dwmci_bind(struct udevice
*dev
, struct mmc
*mmc
, struct mmc_config
*cfg
)
516 return mmc_bind(dev
, mmc
, cfg
);
519 int add_dwmci(struct dwmci_host
*host
, u32 max_clk
, u32 min_clk
)
521 dwmci_setup_cfg(&host
->cfg
, host
->name
, host
->buswidth
, host
->caps
,
524 host
->mmc
= mmc_create(&host
->cfg
, host
);
525 if (host
->mmc
== NULL
)