drivers/mmc/dw_mmc.c

   1 /*
   2  * (C) Copyright 2012 SAMSUNG Electronics
   3  * Jaehoon Chung <jh80.chung@samsung.com>
   4  * Rajeshawari Shinde <rajeshwari.s@samsung.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <bouncebuf.h>
  10 #include <common.h>
  11 #include <errno.h>
  12 #include <malloc.h>
  13 #include <memalign.h>
  14 #include <mmc.h>
  15 #include <dwmmc.h>
  16 #include <asm-generic/errno.h>
  17
  18 #define PAGE_SIZE 4096
  19
  20 static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
  21 {
  22         unsigned long timeout = 1000;
  23         u32 ctrl;
  24
  25         dwmci_writel(host, DWMCI_CTRL, value);
  26
  27         while (timeout--) {
  28                 ctrl = dwmci_readl(host, DWMCI_CTRL);
  29                 if (!(ctrl & DWMCI_RESET_ALL))
  30                         return 1;
  31         }
  32         return 0;
  33 }
  34
  35 static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
  36                 u32 desc0, u32 desc1, u32 desc2)
  37 {
  38         struct dwmci_idmac *desc = idmac;
  39
  40         desc->flags = desc0;
  41         desc->cnt = desc1;
  42         desc->addr = desc2;
  43         desc->next_addr = (unsigned int)desc + sizeof(struct dwmci_idmac);
  44 }
  45
  46 static void dwmci_prepare_data(struct dwmci_host *host,
  47                                struct mmc_data *data,
  48                                struct dwmci_idmac *cur_idmac,
  49                                void *bounce_buffer)
  50 {
  51         unsigned long ctrl;
  52         unsigned int i = 0, flags, cnt, blk_cnt;
  53         ulong data_start, data_end;
  54
  55
  56         blk_cnt = data->blocks;
  57
  58         dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
  59
  60         data_start = (ulong)cur_idmac;
  61         dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac);
  62
  63         do {
  64                 flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
  65                 flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
  66                 if (blk_cnt <= 8) {
  67                         flags |= DWMCI_IDMAC_LD;
  68                         cnt = data->blocksize * blk_cnt;
  69                 } else
  70                         cnt = data->blocksize * 8;
  71
  72                 dwmci_set_idma_desc(cur_idmac, flags, cnt,
  73                                     (u32)bounce_buffer + (i * PAGE_SIZE));
  74
  75                 if (blk_cnt <= 8)
  76                         break;
  77                 blk_cnt -= 8;
  78                 cur_idmac++;
  79                 i++;
  80         } while(1);
  81
  82         data_end = (ulong)cur_idmac;
  83         flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
  84
  85         ctrl = dwmci_readl(host, DWMCI_CTRL);
  86         ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
  87         dwmci_writel(host, DWMCI_CTRL, ctrl);
  88
  89         ctrl = dwmci_readl(host, DWMCI_BMOD);
  90         ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
  91         dwmci_writel(host, DWMCI_BMOD, ctrl);
  92
  93         dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
  94         dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
  95 }
  96
  97 static int dwmci_set_transfer_mode(struct dwmci_host *host,
  98                 struct mmc_data *data)
  99 {
 100         unsigned long mode;
 101
 102         mode = DWMCI_CMD_DATA_EXP;
 103         if (data->flags & MMC_DATA_WRITE)
 104                 mode |= DWMCI_CMD_RW;
 105
 106         return mode;
 107 }
 108
 109 static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 110                 struct mmc_data *data)
 111 {
 112         struct dwmci_host *host = mmc->priv;
 113         ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
 114                                  data ? DIV_ROUND_UP(data->blocks, 8) : 0);
 115         int ret = 0, flags = 0, i;
 116         unsigned int timeout = 100000;
 117         u32 retry = 10000;
 118         u32 mask, ctrl;
 119         ulong start = get_timer(0);
 120         struct bounce_buffer bbstate;
 121
 122         while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
 123                 if (get_timer(start) > timeout) {
 124                         debug("%s: Timeout on data busy\n", __func__);
 125                         return TIMEOUT;
 126                 }
 127         }
 128
 129         dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
 130
 131         if (data) {
 132                 if (data->flags == MMC_DATA_READ) {
 133                         bounce_buffer_start(&bbstate, (void*)data->dest,
 134                                             data->blocksize *
 135                                             data->blocks, GEN_BB_WRITE);
 136                 } else {
 137                         bounce_buffer_start(&bbstate, (void*)data->src,
 138                                             data->blocksize *
 139                                             data->blocks, GEN_BB_READ);
 140                 }
 141                 dwmci_prepare_data(host, data, cur_idmac,
 142                                    bbstate.bounce_buffer);
 143         }
 144
 145         dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
 146
 147         if (data)
 148                 flags = dwmci_set_transfer_mode(host, data);
 149
 150         if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
 151                 return -1;
 152
 153         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 154                 flags |= DWMCI_CMD_ABORT_STOP;
 155         else
 156                 flags |= DWMCI_CMD_PRV_DAT_WAIT;
 157
 158         if (cmd->resp_type & MMC_RSP_PRESENT) {
 159                 flags |= DWMCI_CMD_RESP_EXP;
 160                 if (cmd->resp_type & MMC_RSP_136)
 161                         flags |= DWMCI_CMD_RESP_LENGTH;
 162         }
 163
 164         if (cmd->resp_type & MMC_RSP_CRC)
 165                 flags |= DWMCI_CMD_CHECK_CRC;
 166
 167         flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
 168
 169         debug("Sending CMD%d\n",cmd->cmdidx);
 170
 171         dwmci_writel(host, DWMCI_CMD, flags);
 172
 173         for (i = 0; i < retry; i++) {
 174                 mask = dwmci_readl(host, DWMCI_RINTSTS);
 175                 if (mask & DWMCI_INTMSK_CDONE) {
 176                         if (!data)
 177                                 dwmci_writel(host, DWMCI_RINTSTS, mask);
 178                         break;
 179                 }
 180         }
 181
 182         if (i == retry) {
 183                 debug("%s: Timeout.\n", __func__);
 184                 return TIMEOUT;
 185         }
 186
 187         if (mask & DWMCI_INTMSK_RTO) {
 188                 /*
 189                  * Timeout here is not necessarily fatal. (e)MMC cards
 190                  * will splat here when they receive CMD55 as they do
 191                  * not support this command and that is exactly the way
 192                  * to tell them apart from SD cards. Thus, this output
 193                  * below shall be debug(). eMMC cards also do not favor
 194                  * CMD8, please keep that in mind.
 195                  */
 196                 debug("%s: Response Timeout.\n", __func__);
 197                 return TIMEOUT;
 198         } else if (mask & DWMCI_INTMSK_RE) {
 199                 debug("%s: Response Error.\n", __func__);
 200                 return -EIO;
 201         }
 202
 203
 204         if (cmd->resp_type & MMC_RSP_PRESENT) {
 205                 if (cmd->resp_type & MMC_RSP_136) {
 206                         cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
 207                         cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
 208                         cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
 209                         cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
 210                 } else {
 211                         cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
 212                 }
 213         }
 214
 215         if (data) {
 216                 start = get_timer(0);
 217                 timeout = 1000;
 218                 for (;;) {
 219                         mask = dwmci_readl(host, DWMCI_RINTSTS);
 220                         /* Error during data transfer. */
 221                         if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
 222                                 debug("%s: DATA ERROR!\n", __func__);
 223                                 ret = -EINVAL;
 224                                 break;
 225                         }
 226
 227                         /* Data arrived correctly. */
 228                         if (mask & DWMCI_INTMSK_DTO) {
 229                                 ret = 0;
 230                                 break;
 231                         }
 232
 233                         /* Check for timeout. */
 234                         if (get_timer(start) > timeout) {
 235                                 debug("%s: Timeout waiting for data!\n",
 236                                        __func__);
 237                                 ret = TIMEOUT;
 238                                 break;
 239                         }
 240                 }
 241
 242                 dwmci_writel(host, DWMCI_RINTSTS, mask);
 243
 244                 ctrl = dwmci_readl(host, DWMCI_CTRL);
 245                 ctrl &= ~(DWMCI_DMA_EN);
 246                 dwmci_writel(host, DWMCI_CTRL, ctrl);
 247
 248                 bounce_buffer_stop(&bbstate);
 249         }
 250
 251         udelay(100);
 252
 253         return ret;
 254 }
 255
 256 static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
 257 {
 258         u32 div, status;
 259         int timeout = 10000;
 260         unsigned long sclk;
 261
 262         if ((freq == host->clock) || (freq == 0))
 263                 return 0;
 264         /*
 265          * If host->get_mmc_clk isn't defined,
 266          * then assume that host->bus_hz is source clock value.
 267          * host->bus_hz should be set by user.
 268          */
 269         if (host->get_mmc_clk)
 270                 sclk = host->get_mmc_clk(host, freq);
 271         else if (host->bus_hz)
 272                 sclk = host->bus_hz;
 273         else {
 274                 debug("%s: Didn't get source clock value.\n", __func__);
 275                 return -EINVAL;
 276         }
 277
 278         if (sclk == freq)
 279                 div = 0;        /* bypass mode */
 280         else
 281                 div = DIV_ROUND_UP(sclk, 2 * freq);
 282
 283         dwmci_writel(host, DWMCI_CLKENA, 0);
 284         dwmci_writel(host, DWMCI_CLKSRC, 0);
 285
 286         dwmci_writel(host, DWMCI_CLKDIV, div);
 287         dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
 288                         DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
 289
 290         do {
 291                 status = dwmci_readl(host, DWMCI_CMD);
 292                 if (timeout-- < 0) {
 293                         debug("%s: Timeout!\n", __func__);
 294                         return -ETIMEDOUT;
 295                 }
 296         } while (status & DWMCI_CMD_START);
 297
 298         dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
 299                         DWMCI_CLKEN_LOW_PWR);
 300
 301         dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
 302                         DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
 303
 304         timeout = 10000;
 305         do {
 306                 status = dwmci_readl(host, DWMCI_CMD);
 307                 if (timeout-- < 0) {
 308                         debug("%s: Timeout!\n", __func__);
 309                         return -ETIMEDOUT;
 310                 }
 311         } while (status & DWMCI_CMD_START);
 312
 313         host->clock = freq;
 314
 315         return 0;
 316 }
 317
 318 static void dwmci_set_ios(struct mmc *mmc)
 319 {
 320         struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
 321         u32 ctype, regs;
 322
 323         debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
 324
 325         dwmci_setup_bus(host, mmc->clock);
 326         switch (mmc->bus_width) {
 327         case 8:
 328                 ctype = DWMCI_CTYPE_8BIT;
 329                 break;
 330         case 4:
 331                 ctype = DWMCI_CTYPE_4BIT;
 332                 break;
 333         default:
 334                 ctype = DWMCI_CTYPE_1BIT;
 335                 break;
 336         }
 337
 338         dwmci_writel(host, DWMCI_CTYPE, ctype);
 339
 340         regs = dwmci_readl(host, DWMCI_UHS_REG);
 341         if (mmc->ddr_mode)
 342                 regs |= DWMCI_DDR_MODE;
 343         else
 344                 regs &= ~DWMCI_DDR_MODE;
 345
 346         dwmci_writel(host, DWMCI_UHS_REG, regs);
 347
 348         if (host->clksel)
 349                 host->clksel(host);
 350 }
 351
 352 static int dwmci_init(struct mmc *mmc)
 353 {
 354         struct dwmci_host *host = mmc->priv;
 355
 356         if (host->board_init)
 357                 host->board_init(host);
 358
 359         dwmci_writel(host, DWMCI_PWREN, 1);
 360
 361         if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
 362                 debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
 363                 return -EIO;
 364         }
 365
 366         /* Enumerate at 400KHz */
 367         dwmci_setup_bus(host, mmc->cfg->f_min);
 368
 369         dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
 370         dwmci_writel(host, DWMCI_INTMASK, 0);
 371
 372         dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
 373
 374         dwmci_writel(host, DWMCI_IDINTEN, 0);
 375         dwmci_writel(host, DWMCI_BMOD, 1);
 376
 377         if (!host->fifoth_val) {
 378                 uint32_t fifo_size;
 379
 380                 fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
 381                 fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
 382                 host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
 383                                 TX_WMARK(fifo_size / 2);
 384         }
 385         dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
 386
 387         dwmci_writel(host, DWMCI_CLKENA, 0);
 388         dwmci_writel(host, DWMCI_CLKSRC, 0);
 389
 390         return 0;
 391 }
 392
 393 static const struct mmc_ops dwmci_ops = {
 394         .send_cmd       = dwmci_send_cmd,
 395         .set_ios        = dwmci_set_ios,
 396         .init           = dwmci_init,
 397 };
 398
 399 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
 400 {
 401         host->cfg.name = host->name;
 402         host->cfg.ops = &dwmci_ops;
 403         host->cfg.f_min = min_clk;
 404         host->cfg.f_max = max_clk;
 405
 406         host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 407
 408         host->cfg.host_caps = host->caps;
 409
 410         if (host->buswidth == 8) {
 411                 host->cfg.host_caps |= MMC_MODE_8BIT;
 412                 host->cfg.host_caps &= ~MMC_MODE_4BIT;
 413         } else {
 414                 host->cfg.host_caps |= MMC_MODE_4BIT;
 415                 host->cfg.host_caps &= ~MMC_MODE_8BIT;
 416         }
 417         host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
 418
 419         host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 420
 421         host->mmc = mmc_create(&host->cfg, host);
 422         if (host->mmc == NULL)
 423                 return -1;
 424
 425         return 0;
 426 }