drivers/mmc/fsl_esdhc.c

   1 /*
   2  * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
   3  * Andy Fleming
   4  *
   5  * Based vaguely on the pxa mmc code:
   6  * (C) Copyright 2003
   7  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <config.h>
  13 #include <common.h>
  14 #include <command.h>
  15 #include <errno.h>
  16 #include <hwconfig.h>
  17 #include <mmc.h>
  18 #include <part.h>
  19 #include <malloc.h>
  20 #include <fsl_esdhc.h>
  21 #include <fdt_support.h>
  22 #include <asm/io.h>
  23 #include <dm.h>
  24 #include <asm-generic/gpio.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #define SDHCI_IRQ_EN_BITS               (IRQSTATEN_CC | IRQSTATEN_TC | \
  29                                 IRQSTATEN_CINT | \
  30                                 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
  31                                 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
  32                                 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
  33                                 IRQSTATEN_DINT)
  34
  35 struct fsl_esdhc {
  36         uint    dsaddr;         /* SDMA system address register */
  37         uint    blkattr;        /* Block attributes register */
  38         uint    cmdarg;         /* Command argument register */
  39         uint    xfertyp;        /* Transfer type register */
  40         uint    cmdrsp0;        /* Command response 0 register */
  41         uint    cmdrsp1;        /* Command response 1 register */
  42         uint    cmdrsp2;        /* Command response 2 register */
  43         uint    cmdrsp3;        /* Command response 3 register */
  44         uint    datport;        /* Buffer data port register */
  45         uint    prsstat;        /* Present state register */
  46         uint    proctl;         /* Protocol control register */
  47         uint    sysctl;         /* System Control Register */
  48         uint    irqstat;        /* Interrupt status register */
  49         uint    irqstaten;      /* Interrupt status enable register */
  50         uint    irqsigen;       /* Interrupt signal enable register */
  51         uint    autoc12err;     /* Auto CMD error status register */
  52         uint    hostcapblt;     /* Host controller capabilities register */
  53         uint    wml;            /* Watermark level register */
  54         uint    mixctrl;        /* For USDHC */
  55         char    reserved1[4];   /* reserved */
  56         uint    fevt;           /* Force event register */
  57         uint    admaes;         /* ADMA error status register */
  58         uint    adsaddr;        /* ADMA system address register */
  59         char    reserved2[4];
  60         uint    dllctrl;
  61         uint    dllstat;
  62         uint    clktunectrlstatus;
  63         char    reserved3[84];
  64         uint    vendorspec;
  65         uint    mmcboot;
  66         uint    vendorspec2;
  67         char    reserved4[48];
  68         uint    hostver;        /* Host controller version register */
  69         char    reserved5[4];   /* reserved */
  70         uint    dmaerraddr;     /* DMA error address register */
  71         char    reserved6[4];   /* reserved */
  72         uint    dmaerrattr;     /* DMA error attribute register */
  73         char    reserved7[4];   /* reserved */
  74         uint    hostcapblt2;    /* Host controller capabilities register 2 */
  75         char    reserved8[8];   /* reserved */
  76         uint    tcr;            /* Tuning control register */
  77         char    reserved9[28];  /* reserved */
  78         uint    sddirctl;       /* SD direction control register */
  79         char    reserved10[712];/* reserved */
  80         uint    scr;            /* eSDHC control register */
  81 };
  82
  83 /**
  84  * struct fsl_esdhc_priv
  85  *
  86  * @esdhc_regs: registers of the sdhc controller
  87  * @sdhc_clk: Current clk of the sdhc controller
  88  * @bus_width: bus width, 1bit, 4bit or 8bit
  89  * @cfg: mmc config
  90  * @mmc: mmc
  91  * Following is used when Driver Model is enabled for MMC
  92  * @dev: pointer for the device
  93  * @non_removable: 0: removable; 1: non-removable
  94  * @wp_enable: 1: enable checking wp; 0: no check
  95  * @cd_gpio: gpio for card detection
  96  * @wp_gpio: gpio for write protection
  97  */
  98 struct fsl_esdhc_priv {
  99         struct fsl_esdhc *esdhc_regs;
 100         unsigned int sdhc_clk;
 101         unsigned int bus_width;
 102         struct mmc_config cfg;
 103         struct mmc *mmc;
 104         struct udevice *dev;
 105         int non_removable;
 106         int wp_enable;
 107         struct gpio_desc cd_gpio;
 108         struct gpio_desc wp_gpio;
 109 };
 110
 111 /* Return the XFERTYP flags for a given command and data packet */
 112 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
 113 {
 114         uint xfertyp = 0;
 115
 116         if (data) {
 117                 xfertyp |= XFERTYP_DPSEL;
 118 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 119                 xfertyp |= XFERTYP_DMAEN;
 120 #endif
 121                 if (data->blocks > 1) {
 122                         xfertyp |= XFERTYP_MSBSEL;
 123                         xfertyp |= XFERTYP_BCEN;
 124 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
 125                         xfertyp |= XFERTYP_AC12EN;
 126 #endif
 127                 }
 128
 129                 if (data->flags & MMC_DATA_READ)
 130                         xfertyp |= XFERTYP_DTDSEL;
 131         }
 132
 133         if (cmd->resp_type & MMC_RSP_CRC)
 134                 xfertyp |= XFERTYP_CCCEN;
 135         if (cmd->resp_type & MMC_RSP_OPCODE)
 136                 xfertyp |= XFERTYP_CICEN;
 137         if (cmd->resp_type & MMC_RSP_136)
 138                 xfertyp |= XFERTYP_RSPTYP_136;
 139         else if (cmd->resp_type & MMC_RSP_BUSY)
 140                 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
 141         else if (cmd->resp_type & MMC_RSP_PRESENT)
 142                 xfertyp |= XFERTYP_RSPTYP_48;
 143
 144         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 145                 xfertyp |= XFERTYP_CMDTYP_ABORT;
 146
 147         return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
 148 }
 149
 150 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
 151 /*
 152  * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
 153  */
 154 static void
 155 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
 156 {
 157         struct fsl_esdhc_priv *priv = mmc->priv;
 158         struct fsl_esdhc *regs = priv->esdhc_regs;
 159         uint blocks;
 160         char *buffer;
 161         uint databuf;
 162         uint size;
 163         uint irqstat;
 164         uint timeout;
 165
 166         if (data->flags & MMC_DATA_READ) {
 167                 blocks = data->blocks;
 168                 buffer = data->dest;
 169                 while (blocks) {
 170                         timeout = PIO_TIMEOUT;
 171                         size = data->blocksize;
 172                         irqstat = esdhc_read32(&regs->irqstat);
 173                         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
 174                                 && --timeout);
 175                         if (timeout <= 0) {
 176                                 printf("\nData Read Failed in PIO Mode.");
 177                                 return;
 178                         }
 179                         while (size && (!(irqstat & IRQSTAT_TC))) {
 180                                 udelay(100); /* Wait before last byte transfer complete */
 181                                 irqstat = esdhc_read32(&regs->irqstat);
 182                                 databuf = in_le32(&regs->datport);
 183                                 *((uint *)buffer) = databuf;
 184                                 buffer += 4;
 185                                 size -= 4;
 186                         }
 187                         blocks--;
 188                 }
 189         } else {
 190                 blocks = data->blocks;
 191                 buffer = (char *)data->src;
 192                 while (blocks) {
 193                         timeout = PIO_TIMEOUT;
 194                         size = data->blocksize;
 195                         irqstat = esdhc_read32(&regs->irqstat);
 196                         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
 197                                 && --timeout);
 198                         if (timeout <= 0) {
 199                                 printf("\nData Write Failed in PIO Mode.");
 200                                 return;
 201                         }
 202                         while (size && (!(irqstat & IRQSTAT_TC))) {
 203                                 udelay(100); /* Wait before last byte transfer complete */
 204                                 databuf = *((uint *)buffer);
 205                                 buffer += 4;
 206                                 size -= 4;
 207                                 irqstat = esdhc_read32(&regs->irqstat);
 208                                 out_le32(&regs->datport, databuf);
 209                         }
 210                         blocks--;
 211                 }
 212         }
 213 }
 214 #endif
 215
 216 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 217 {
 218         int timeout;
 219         struct fsl_esdhc_priv *priv = mmc->priv;
 220         struct fsl_esdhc *regs = priv->esdhc_regs;
 221 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
 222         dma_addr_t addr;
 223 #endif
 224         uint wml_value;
 225
 226         wml_value = data->blocksize/4;
 227
 228         if (data->flags & MMC_DATA_READ) {
 229                 if (wml_value > WML_RD_WML_MAX)
 230                         wml_value = WML_RD_WML_MAX_VAL;
 231
 232                 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
 233 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 234 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
 235                 addr = virt_to_phys((void *)(data->dest));
 236                 if (upper_32_bits(addr))
 237                         printf("Error found for upper 32 bits\n");
 238                 else
 239                         esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
 240 #else
 241                 esdhc_write32(&regs->dsaddr, (u32)data->dest);
 242 #endif
 243 #endif
 244         } else {
 245 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 246                 flush_dcache_range((ulong)data->src,
 247                                    (ulong)data->src+data->blocks
 248                                          *data->blocksize);
 249 #endif
 250                 if (wml_value > WML_WR_WML_MAX)
 251                         wml_value = WML_WR_WML_MAX_VAL;
 252                 if (priv->wp_enable) {
 253                         if ((esdhc_read32(&regs->prsstat) &
 254                             PRSSTAT_WPSPL) == 0) {
 255                                 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
 256                                 return -ETIMEDOUT;
 257                         }
 258                 }
 259
 260                 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
 261                                         wml_value << 16);
 262 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 263 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
 264                 addr = virt_to_phys((void *)(data->src));
 265                 if (upper_32_bits(addr))
 266                         printf("Error found for upper 32 bits\n");
 267                 else
 268                         esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
 269 #else
 270                 esdhc_write32(&regs->dsaddr, (u32)data->src);
 271 #endif
 272 #endif
 273         }
 274
 275         esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
 276
 277         /* Calculate the timeout period for data transactions */
 278         /*
 279          * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
 280          * 2)Timeout period should be minimum 0.250sec as per SD Card spec
 281          *  So, Number of SD Clock cycles for 0.25sec should be minimum
 282          *              (SD Clock/sec * 0.25 sec) SD Clock cycles
 283          *              = (mmc->clock * 1/4) SD Clock cycles
 284          * As 1) >=  2)
 285          * => (2^(timeout+13)) >= mmc->clock * 1/4
 286          * Taking log2 both the sides
 287          * => timeout + 13 >= log2(mmc->clock/4)
 288          * Rounding up to next power of 2
 289          * => timeout + 13 = log2(mmc->clock/4) + 1
 290          * => timeout + 13 = fls(mmc->clock/4)
 291          *
 292          * However, the MMC spec "It is strongly recommended for hosts to
 293          * implement more than 500ms timeout value even if the card
 294          * indicates the 250ms maximum busy length."  Even the previous
 295          * value of 300ms is known to be insufficient for some cards.
 296          * So, we use
 297          * => timeout + 13 = fls(mmc->clock/2)
 298          */
 299         timeout = fls(mmc->clock/2);
 300         timeout -= 13;
 301
 302         if (timeout > 14)
 303                 timeout = 14;
 304
 305         if (timeout < 0)
 306                 timeout = 0;
 307
 308 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
 309         if ((timeout == 4) || (timeout == 8) || (timeout == 12))
 310                 timeout++;
 311 #endif
 312
 313 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 314         timeout = 0xE;
 315 #endif
 316         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
 317
 318         return 0;
 319 }
 320
 321 static void check_and_invalidate_dcache_range
 322         (struct mmc_cmd *cmd,
 323          struct mmc_data *data) {
 324         unsigned start = 0;
 325         unsigned end = 0;
 326         unsigned size = roundup(ARCH_DMA_MINALIGN,
 327                                 data->blocks*data->blocksize);
 328 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
 329         dma_addr_t addr;
 330
 331         addr = virt_to_phys((void *)(data->dest));
 332         if (upper_32_bits(addr))
 333                 printf("Error found for upper 32 bits\n");
 334         else
 335                 start = lower_32_bits(addr);
 336 #else
 337         start = (unsigned)data->dest;
 338 #endif
 339         end = start + size;
 340         invalidate_dcache_range(start, end);
 341 }
 342
 343 /*
 344  * Sends a command out on the bus.  Takes the mmc pointer,
 345  * a command pointer, and an optional data pointer.
 346  */
 347 static int
 348 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 349 {
 350         int     err = 0;
 351         uint    xfertyp;
 352         uint    irqstat;
 353         struct fsl_esdhc_priv *priv = mmc->priv;
 354         struct fsl_esdhc *regs = priv->esdhc_regs;
 355
 356 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
 357         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 358                 return 0;
 359 #endif
 360
 361         esdhc_write32(&regs->irqstat, -1);
 362
 363         sync();
 364
 365         /* Wait for the bus to be idle */
 366         while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
 367                         (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
 368                 ;
 369
 370         while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
 371                 ;
 372
 373         /* Wait at least 8 SD clock cycles before the next command */
 374         /*
 375          * Note: This is way more than 8 cycles, but 1ms seems to
 376          * resolve timing issues with some cards
 377          */
 378         udelay(1000);
 379
 380         /* Set up for a data transfer if we have one */
 381         if (data) {
 382                 err = esdhc_setup_data(mmc, data);
 383                 if(err)
 384                         return err;
 385
 386                 if (data->flags & MMC_DATA_READ)
 387                         check_and_invalidate_dcache_range(cmd, data);
 388         }
 389
 390         /* Figure out the transfer arguments */
 391         xfertyp = esdhc_xfertyp(cmd, data);
 392
 393         /* Mask all irqs */
 394         esdhc_write32(&regs->irqsigen, 0);
 395
 396         /* Send the command */
 397         esdhc_write32(&regs->cmdarg, cmd->cmdarg);
 398 #if defined(CONFIG_FSL_USDHC)
 399         esdhc_write32(&regs->mixctrl,
 400         (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
 401                         | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
 402         esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
 403 #else
 404         esdhc_write32(&regs->xfertyp, xfertyp);
 405 #endif
 406
 407         /* Wait for the command to complete */
 408         while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
 409                 ;
 410
 411         irqstat = esdhc_read32(&regs->irqstat);
 412
 413         if (irqstat & CMD_ERR) {
 414                 err = -ECOMM;
 415                 goto out;
 416         }
 417
 418         if (irqstat & IRQSTAT_CTOE) {
 419                 err = -ETIMEDOUT;
 420                 goto out;
 421         }
 422
 423         /* Switch voltage to 1.8V if CMD11 succeeded */
 424         if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
 425                 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
 426
 427                 printf("Run CMD11 1.8V switch\n");
 428                 /* Sleep for 5 ms - max time for card to switch to 1.8V */
 429                 udelay(5000);
 430         }
 431
 432         /* Workaround for ESDHC errata ENGcm03648 */
 433         if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
 434                 int timeout = 6000;
 435
 436                 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
 437                 while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
 438                                         PRSSTAT_DAT0)) {
 439                         udelay(100);
 440                         timeout--;
 441                 }
 442
 443                 if (timeout <= 0) {
 444                         printf("Timeout waiting for DAT0 to go high!\n");
 445                         err = -ETIMEDOUT;
 446                         goto out;
 447                 }
 448         }
 449
 450         /* Copy the response to the response buffer */
 451         if (cmd->resp_type & MMC_RSP_136) {
 452                 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
 453
 454                 cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
 455                 cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
 456                 cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
 457                 cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
 458                 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
 459                 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
 460                 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
 461                 cmd->response[3] = (cmdrsp0 << 8);
 462         } else
 463                 cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
 464
 465         /* Wait until all of the blocks are transferred */
 466         if (data) {
 467 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
 468                 esdhc_pio_read_write(mmc, data);
 469 #else
 470                 do {
 471                         irqstat = esdhc_read32(&regs->irqstat);
 472
 473                         if (irqstat & IRQSTAT_DTOE) {
 474                                 err = -ETIMEDOUT;
 475                                 goto out;
 476                         }
 477
 478                         if (irqstat & DATA_ERR) {
 479                                 err = -ECOMM;
 480                                 goto out;
 481                         }
 482                 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
 483
 484                 /*
 485                  * Need invalidate the dcache here again to avoid any
 486                  * cache-fill during the DMA operations such as the
 487                  * speculative pre-fetching etc.
 488                  */
 489                 if (data->flags & MMC_DATA_READ)
 490                         check_and_invalidate_dcache_range(cmd, data);
 491 #endif
 492         }
 493
 494 out:
 495         /* Reset CMD and DATA portions on error */
 496         if (err) {
 497                 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
 498                               SYSCTL_RSTC);
 499                 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
 500                         ;
 501
 502                 if (data) {
 503                         esdhc_write32(&regs->sysctl,
 504                                       esdhc_read32(&regs->sysctl) |
 505                                       SYSCTL_RSTD);
 506                         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
 507                                 ;
 508                 }
 509
 510                 /* If this was CMD11, then notify that power cycle is needed */
 511                 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
 512                         printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
 513         }
 514
 515         esdhc_write32(&regs->irqstat, -1);
 516
 517         return err;
 518 }
 519
 520 static void set_sysctl(struct mmc *mmc, uint clock)
 521 {
 522         int div, pre_div;
 523         struct fsl_esdhc_priv *priv = mmc->priv;
 524         struct fsl_esdhc *regs = priv->esdhc_regs;
 525         int sdhc_clk = priv->sdhc_clk;
 526         uint clk;
 527
 528         if (clock < mmc->cfg->f_min)
 529                 clock = mmc->cfg->f_min;
 530
 531         if (sdhc_clk / 16 > clock) {
 532                 for (pre_div = 2; pre_div < 256; pre_div *= 2)
 533                         if ((sdhc_clk / pre_div) <= (clock * 16))
 534                                 break;
 535         } else
 536                 pre_div = 2;
 537
 538         for (div = 1; div <= 16; div++)
 539                 if ((sdhc_clk / (div * pre_div)) <= clock)
 540                         break;
 541
 542         pre_div >>= mmc->ddr_mode ? 2 : 1;
 543         div -= 1;
 544
 545         clk = (pre_div << 8) | (div << 4);
 546
 547 #ifdef CONFIG_FSL_USDHC
 548         esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
 549 #else
 550         esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
 551 #endif
 552
 553         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
 554
 555         udelay(10000);
 556
 557 #ifdef CONFIG_FSL_USDHC
 558         esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
 559 #else
 560         esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
 561 #endif
 562
 563 }
 564
 565 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 566 static void esdhc_clock_control(struct mmc *mmc, bool enable)
 567 {
 568         struct fsl_esdhc_priv *priv = mmc->priv;
 569         struct fsl_esdhc *regs = priv->esdhc_regs;
 570         u32 value;
 571         u32 time_out;
 572
 573         value = esdhc_read32(&regs->sysctl);
 574
 575         if (enable)
 576                 value |= SYSCTL_CKEN;
 577         else
 578                 value &= ~SYSCTL_CKEN;
 579
 580         esdhc_write32(&regs->sysctl, value);
 581
 582         time_out = 20;
 583         value = PRSSTAT_SDSTB;
 584         while (!(esdhc_read32(&regs->prsstat) & value)) {
 585                 if (time_out == 0) {
 586                         printf("fsl_esdhc: Internal clock never stabilised.\n");
 587                         break;
 588                 }
 589                 time_out--;
 590                 mdelay(1);
 591         }
 592 }
 593 #endif
 594
 595 static void esdhc_set_ios(struct mmc *mmc)
 596 {
 597         struct fsl_esdhc_priv *priv = mmc->priv;
 598         struct fsl_esdhc *regs = priv->esdhc_regs;
 599
 600 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 601         /* Select to use peripheral clock */
 602         esdhc_clock_control(mmc, false);
 603         esdhc_setbits32(&regs->scr, ESDHCCTL_PCS);
 604         esdhc_clock_control(mmc, true);
 605 #endif
 606         /* Set the clock speed */
 607         set_sysctl(mmc, mmc->clock);
 608
 609         /* Set the bus width */
 610         esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
 611
 612         if (mmc->bus_width == 4)
 613                 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
 614         else if (mmc->bus_width == 8)
 615                 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
 616
 617 }
 618
 619 static int esdhc_init(struct mmc *mmc)
 620 {
 621         struct fsl_esdhc_priv *priv = mmc->priv;
 622         struct fsl_esdhc *regs = priv->esdhc_regs;
 623         int timeout = 1000;
 624
 625         /* Reset the entire host controller */
 626         esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
 627
 628         /* Wait until the controller is available */
 629         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
 630                 udelay(1000);
 631
 632 #if defined(CONFIG_FSL_USDHC)
 633         /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
 634         esdhc_write32(&regs->mmcboot, 0x0);
 635         /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
 636         esdhc_write32(&regs->mixctrl, 0x0);
 637         esdhc_write32(&regs->clktunectrlstatus, 0x0);
 638
 639         /* Put VEND_SPEC to default value */
 640         esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
 641
 642         /* Disable DLL_CTRL delay line */
 643         esdhc_write32(&regs->dllctrl, 0x0);
 644 #endif
 645
 646 #ifndef ARCH_MXC
 647         /* Enable cache snooping */
 648         esdhc_write32(&regs->scr, 0x00000040);
 649 #endif
 650
 651 #ifndef CONFIG_FSL_USDHC
 652         esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
 653 #else
 654         esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
 655 #endif
 656
 657         /* Set the initial clock speed */
 658         mmc_set_clock(mmc, 400000);
 659
 660         /* Disable the BRR and BWR bits in IRQSTAT */
 661         esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
 662
 663         /* Put the PROCTL reg back to the default */
 664         esdhc_write32(&regs->proctl, PROCTL_INIT);
 665
 666         /* Set timout to the maximum value */
 667         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
 668
 669 #ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
 670         esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
 671 #endif
 672
 673         return 0;
 674 }
 675
 676 static int esdhc_getcd(struct mmc *mmc)
 677 {
 678         struct fsl_esdhc_priv *priv = mmc->priv;
 679         struct fsl_esdhc *regs = priv->esdhc_regs;
 680         int timeout = 1000;
 681
 682 #ifdef CONFIG_ESDHC_DETECT_QUIRK
 683         if (CONFIG_ESDHC_DETECT_QUIRK)
 684                 return 1;
 685 #endif
 686
 687 #ifdef CONFIG_DM_MMC
 688         if (priv->non_removable)
 689                 return 1;
 690
 691         if (dm_gpio_is_valid(&priv->cd_gpio))
 692                 return dm_gpio_get_value(&priv->cd_gpio);
 693 #endif
 694
 695         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
 696                 udelay(1000);
 697
 698         return timeout > 0;
 699 }
 700
 701 static void esdhc_reset(struct fsl_esdhc *regs)
 702 {
 703         unsigned long timeout = 100; /* wait max 100 ms */
 704
 705         /* reset the controller */
 706         esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
 707
 708         /* hardware clears the bit when it is done */
 709         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
 710                 udelay(1000);
 711         if (!timeout)
 712                 printf("MMC/SD: Reset never completed.\n");
 713 }
 714
 715 static const struct mmc_ops esdhc_ops = {
 716         .send_cmd       = esdhc_send_cmd,
 717         .set_ios        = esdhc_set_ios,
 718         .init           = esdhc_init,
 719         .getcd          = esdhc_getcd,
 720 };
 721
 722 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
 723                                  struct fsl_esdhc_priv *priv)
 724 {
 725         if (!cfg || !priv)
 726                 return -EINVAL;
 727
 728         priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
 729         priv->bus_width = cfg->max_bus_width;
 730         priv->sdhc_clk = cfg->sdhc_clk;
 731         priv->wp_enable  = cfg->wp_enable;
 732
 733         return 0;
 734 };
 735
 736 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
 737 {
 738         struct fsl_esdhc *regs;
 739         struct mmc *mmc;
 740         u32 caps, voltage_caps;
 741
 742         if (!priv)
 743                 return -EINVAL;
 744
 745         regs = priv->esdhc_regs;
 746
 747         /* First reset the eSDHC controller */
 748         esdhc_reset(regs);
 749
 750 #ifndef CONFIG_FSL_USDHC
 751         esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
 752                                 | SYSCTL_IPGEN | SYSCTL_CKEN);
 753 #else
 754         esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
 755                         VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
 756 #endif
 757
 758         writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
 759         memset(&priv->cfg, 0, sizeof(priv->cfg));
 760
 761         voltage_caps = 0;
 762         caps = esdhc_read32(&regs->hostcapblt);
 763
 764 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
 765         caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
 766                         ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
 767 #endif
 768
 769 /* T4240 host controller capabilities register should have VS33 bit */
 770 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 771         caps = caps | ESDHC_HOSTCAPBLT_VS33;
 772 #endif
 773
 774         if (caps & ESDHC_HOSTCAPBLT_VS18)
 775                 voltage_caps |= MMC_VDD_165_195;
 776         if (caps & ESDHC_HOSTCAPBLT_VS30)
 777                 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
 778         if (caps & ESDHC_HOSTCAPBLT_VS33)
 779                 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
 780
 781         priv->cfg.name = "FSL_SDHC";
 782         priv->cfg.ops = &esdhc_ops;
 783 #ifdef CONFIG_SYS_SD_VOLTAGE
 784         priv->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
 785 #else
 786         priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 787 #endif
 788         if ((priv->cfg.voltages & voltage_caps) == 0) {
 789                 printf("voltage not supported by controller\n");
 790                 return -1;
 791         }
 792
 793         if (priv->bus_width == 8)
 794                 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
 795         else if (priv->bus_width == 4)
 796                 priv->cfg.host_caps = MMC_MODE_4BIT;
 797
 798         priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
 799 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
 800         priv->cfg.host_caps |= MMC_MODE_DDR_52MHz;
 801 #endif
 802
 803         if (priv->bus_width > 0) {
 804                 if (priv->bus_width < 8)
 805                         priv->cfg.host_caps &= ~MMC_MODE_8BIT;
 806                 if (priv->bus_width < 4)
 807                         priv->cfg.host_caps &= ~MMC_MODE_4BIT;
 808         }
 809
 810         if (caps & ESDHC_HOSTCAPBLT_HSS)
 811                 priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 812
 813 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
 814         if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
 815                 priv->cfg.host_caps &= ~MMC_MODE_8BIT;
 816 #endif
 817
 818         priv->cfg.f_min = 400000;
 819         priv->cfg.f_max = min(priv->sdhc_clk, (u32)52000000);
 820
 821         priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 822
 823         mmc = mmc_create(&priv->cfg, priv);
 824         if (mmc == NULL)
 825                 return -1;
 826
 827         priv->mmc = mmc;
 828
 829         return 0;
 830 }
 831
 832 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 833 {
 834         struct fsl_esdhc_priv *priv;
 835         int ret;
 836
 837         if (!cfg)
 838                 return -EINVAL;
 839
 840         priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
 841         if (!priv)
 842                 return -ENOMEM;
 843
 844         ret = fsl_esdhc_cfg_to_priv(cfg, priv);
 845         if (ret) {
 846                 debug("%s xlate failure\n", __func__);
 847                 free(priv);
 848                 return ret;
 849         }
 850
 851         ret = fsl_esdhc_init(priv);
 852         if (ret) {
 853                 debug("%s init failure\n", __func__);
 854                 free(priv);
 855                 return ret;
 856         }
 857
 858         return 0;
 859 }
 860
 861 int fsl_esdhc_mmc_init(bd_t *bis)
 862 {
 863         struct fsl_esdhc_cfg *cfg;
 864
 865         cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
 866         cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
 867         cfg->sdhc_clk = gd->arch.sdhc_clk;
 868         return fsl_esdhc_initialize(bis, cfg);
 869 }
 870
 871 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
 872 void mmc_adapter_card_type_ident(void)
 873 {
 874         u8 card_id;
 875         u8 value;
 876
 877         card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
 878         gd->arch.sdhc_adapter = card_id;
 879
 880         switch (card_id) {
 881         case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
 882                 value = QIXIS_READ(brdcfg[5]);
 883                 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
 884                 QIXIS_WRITE(brdcfg[5], value);
 885                 break;
 886         case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
 887                 value = QIXIS_READ(pwr_ctl[1]);
 888                 value |= QIXIS_EVDD_BY_SDHC_VS;
 889                 QIXIS_WRITE(pwr_ctl[1], value);
 890                 break;
 891         case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
 892                 value = QIXIS_READ(brdcfg[5]);
 893                 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
 894                 QIXIS_WRITE(brdcfg[5], value);
 895                 break;
 896         case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
 897                 break;
 898         case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
 899                 break;
 900         case QIXIS_ESDHC_ADAPTER_TYPE_SD:
 901                 break;
 902         case QIXIS_ESDHC_NO_ADAPTER:
 903                 break;
 904         default:
 905                 break;
 906         }
 907 }
 908 #endif
 909
 910 #ifdef CONFIG_OF_LIBFDT
 911 void fdt_fixup_esdhc(void *blob, bd_t *bd)
 912 {
 913         const char *compat = "fsl,esdhc";
 914
 915 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
 916         if (!hwconfig("esdhc")) {
 917                 do_fixup_by_compat(blob, compat, "status", "disabled",
 918                                 8 + 1, 1);
 919                 return;
 920         }
 921 #endif
 922
 923 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 924         do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
 925                                gd->arch.sdhc_clk, 1);
 926 #else
 927         do_fixup_by_compat_u32(blob, compat, "clock-frequency",
 928                                gd->arch.sdhc_clk, 1);
 929 #endif
 930 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
 931         do_fixup_by_compat_u32(blob, compat, "adapter-type",
 932                                (u32)(gd->arch.sdhc_adapter), 1);
 933 #endif
 934         do_fixup_by_compat(blob, compat, "status", "okay",
 935                            4 + 1, 1);
 936 }
 937 #endif
 938
 939 #ifdef CONFIG_DM_MMC
 940 #include <asm/arch/clock.h>
 941 static int fsl_esdhc_probe(struct udevice *dev)
 942 {
 943         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 944         struct fsl_esdhc_priv *priv = dev_get_priv(dev);
 945         const void *fdt = gd->fdt_blob;
 946         int node = dev->of_offset;
 947         fdt_addr_t addr;
 948         unsigned int val;
 949         int ret;
 950
 951         addr = dev_get_addr(dev);
 952         if (addr == FDT_ADDR_T_NONE)
 953                 return -EINVAL;
 954
 955         priv->esdhc_regs = (struct fsl_esdhc *)addr;
 956         priv->dev = dev;
 957
 958         val = fdtdec_get_int(fdt, node, "bus-width", -1);
 959         if (val == 8)
 960                 priv->bus_width = 8;
 961         else if (val == 4)
 962                 priv->bus_width = 4;
 963         else
 964                 priv->bus_width = 1;
 965
 966         if (fdt_get_property(fdt, node, "non-removable", NULL)) {
 967                 priv->non_removable = 1;
 968          } else {
 969                 priv->non_removable = 0;
 970                 gpio_request_by_name_nodev(fdt, node, "cd-gpios", 0,
 971                                            &priv->cd_gpio, GPIOD_IS_IN);
 972         }
 973
 974         priv->wp_enable = 1;
 975
 976         ret = gpio_request_by_name_nodev(fdt, node, "wp-gpios", 0,
 977                                          &priv->wp_gpio, GPIOD_IS_IN);
 978         if (ret)
 979                 priv->wp_enable = 0;
 980
 981         /*
 982          * TODO:
 983          * Because lack of clk driver, if SDHC clk is not enabled,
 984          * need to enable it first before this driver is invoked.
 985          *
 986          * we use MXC_ESDHC_CLK to get clk freq.
 987          * If one would like to make this function work,
 988          * the aliases should be provided in dts as this:
 989          *
 990          *  aliases {
 991          *      mmc0 = &usdhc1;
 992          *      mmc1 = &usdhc2;
 993          *      mmc2 = &usdhc3;
 994          *      mmc3 = &usdhc4;
 995          *      };
 996          * Then if your board only supports mmc2 and mmc3, but we can
 997          * correctly get the seq as 2 and 3, then let mxc_get_clock
 998          * work as expected.
 999          */
1000         priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1001         if (priv->sdhc_clk <= 0) {
1002                 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1003                 return -EINVAL;
1004         }
1005
1006         ret = fsl_esdhc_init(priv);
1007         if (ret) {
1008                 dev_err(dev, "fsl_esdhc_init failure\n");
1009                 return ret;
1010         }
1011
1012         upriv->mmc = priv->mmc;
1013
1014         return 0;
1015 }
1016
1017 static const struct udevice_id fsl_esdhc_ids[] = {
1018         { .compatible = "fsl,imx6ul-usdhc", },
1019         { .compatible = "fsl,imx6sx-usdhc", },
1020         { .compatible = "fsl,imx6sl-usdhc", },
1021         { .compatible = "fsl,imx6q-usdhc", },
1022         { .compatible = "fsl,imx7d-usdhc", },
1023         { /* sentinel */ }
1024 };
1025
1026 U_BOOT_DRIVER(fsl_esdhc) = {
1027         .name   = "fsl-esdhc-mmc",
1028         .id     = UCLASS_MMC,
1029         .of_match = fsl_esdhc_ids,
1030         .probe  = fsl_esdhc_probe,
1031         .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
1032 };
1033 #endif