2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
5 * Based vaguely on the pxa mmc code:
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * SPDX-License-Identifier: GPL-2.0+
20 #include <fsl_esdhc.h>
21 #include <fdt_support.h>
24 DECLARE_GLOBAL_DATA_PTR
;
26 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
28 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
29 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
30 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
34 uint dsaddr
; /* SDMA system address register */
35 uint blkattr
; /* Block attributes register */
36 uint cmdarg
; /* Command argument register */
37 uint xfertyp
; /* Transfer type register */
38 uint cmdrsp0
; /* Command response 0 register */
39 uint cmdrsp1
; /* Command response 1 register */
40 uint cmdrsp2
; /* Command response 2 register */
41 uint cmdrsp3
; /* Command response 3 register */
42 uint datport
; /* Buffer data port register */
43 uint prsstat
; /* Present state register */
44 uint proctl
; /* Protocol control register */
45 uint sysctl
; /* System Control Register */
46 uint irqstat
; /* Interrupt status register */
47 uint irqstaten
; /* Interrupt status enable register */
48 uint irqsigen
; /* Interrupt signal enable register */
49 uint autoc12err
; /* Auto CMD error status register */
50 uint hostcapblt
; /* Host controller capabilities register */
51 uint wml
; /* Watermark level register */
52 uint mixctrl
; /* For USDHC */
53 char reserved1
[4]; /* reserved */
54 uint fevt
; /* Force event register */
55 uint admaes
; /* ADMA error status register */
56 uint adsaddr
; /* ADMA system address register */
57 char reserved2
[100]; /* reserved */
58 uint vendorspec
; /* Vendor Specific register */
59 char reserved3
[56]; /* reserved */
60 uint hostver
; /* Host controller version register */
61 char reserved4
[4]; /* reserved */
62 uint dmaerraddr
; /* DMA error address register */
63 char reserved5
[4]; /* reserved */
64 uint dmaerrattr
; /* DMA error attribute register */
65 char reserved6
[4]; /* reserved */
66 uint hostcapblt2
; /* Host controller capabilities register 2 */
67 char reserved7
[8]; /* reserved */
68 uint tcr
; /* Tuning control register */
69 char reserved8
[28]; /* reserved */
70 uint sddirctl
; /* SD direction control register */
71 char reserved9
[712]; /* reserved */
72 uint scr
; /* eSDHC control register */
75 /* Return the XFERTYP flags for a given command and data packet */
76 static uint
esdhc_xfertyp(struct mmc_cmd
*cmd
, struct mmc_data
*data
)
81 xfertyp
|= XFERTYP_DPSEL
;
82 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
83 xfertyp
|= XFERTYP_DMAEN
;
85 if (data
->blocks
> 1) {
86 xfertyp
|= XFERTYP_MSBSEL
;
87 xfertyp
|= XFERTYP_BCEN
;
88 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
89 xfertyp
|= XFERTYP_AC12EN
;
93 if (data
->flags
& MMC_DATA_READ
)
94 xfertyp
|= XFERTYP_DTDSEL
;
97 if (cmd
->resp_type
& MMC_RSP_CRC
)
98 xfertyp
|= XFERTYP_CCCEN
;
99 if (cmd
->resp_type
& MMC_RSP_OPCODE
)
100 xfertyp
|= XFERTYP_CICEN
;
101 if (cmd
->resp_type
& MMC_RSP_136
)
102 xfertyp
|= XFERTYP_RSPTYP_136
;
103 else if (cmd
->resp_type
& MMC_RSP_BUSY
)
104 xfertyp
|= XFERTYP_RSPTYP_48_BUSY
;
105 else if (cmd
->resp_type
& MMC_RSP_PRESENT
)
106 xfertyp
|= XFERTYP_RSPTYP_48
;
108 #if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \
109 defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A)
110 if (cmd
->cmdidx
== MMC_CMD_STOP_TRANSMISSION
)
111 xfertyp
|= XFERTYP_CMDTYP_ABORT
;
113 return XFERTYP_CMD(cmd
->cmdidx
) | xfertyp
;
116 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
118 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
121 esdhc_pio_read_write(struct mmc
*mmc
, struct mmc_data
*data
)
123 struct fsl_esdhc_cfg
*cfg
= mmc
->priv
;
124 struct fsl_esdhc
*regs
= (struct fsl_esdhc
*)cfg
->esdhc_base
;
132 if (data
->flags
& MMC_DATA_READ
) {
133 blocks
= data
->blocks
;
136 timeout
= PIO_TIMEOUT
;
137 size
= data
->blocksize
;
138 irqstat
= esdhc_read32(®s
->irqstat
);
139 while (!(esdhc_read32(®s
->prsstat
) & PRSSTAT_BREN
)
142 printf("\nData Read Failed in PIO Mode.");
145 while (size
&& (!(irqstat
& IRQSTAT_TC
))) {
146 udelay(100); /* Wait before last byte transfer complete */
147 irqstat
= esdhc_read32(®s
->irqstat
);
148 databuf
= in_le32(®s
->datport
);
149 *((uint
*)buffer
) = databuf
;
156 blocks
= data
->blocks
;
157 buffer
= (char *)data
->src
;
159 timeout
= PIO_TIMEOUT
;
160 size
= data
->blocksize
;
161 irqstat
= esdhc_read32(®s
->irqstat
);
162 while (!(esdhc_read32(®s
->prsstat
) & PRSSTAT_BWEN
)
165 printf("\nData Write Failed in PIO Mode.");
168 while (size
&& (!(irqstat
& IRQSTAT_TC
))) {
169 udelay(100); /* Wait before last byte transfer complete */
170 databuf
= *((uint
*)buffer
);
173 irqstat
= esdhc_read32(®s
->irqstat
);
174 out_le32(®s
->datport
, databuf
);
182 static int esdhc_setup_data(struct mmc
*mmc
, struct mmc_data
*data
)
185 struct fsl_esdhc_cfg
*cfg
= mmc
->priv
;
186 struct fsl_esdhc
*regs
= (struct fsl_esdhc
*)cfg
->esdhc_base
;
187 #ifdef CONFIG_LS2085A
192 wml_value
= data
->blocksize
/4;
194 if (data
->flags
& MMC_DATA_READ
) {
195 if (wml_value
> WML_RD_WML_MAX
)
196 wml_value
= WML_RD_WML_MAX_VAL
;
198 esdhc_clrsetbits32(®s
->wml
, WML_RD_WML_MASK
, wml_value
);
199 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
200 #ifdef CONFIG_LS2085A
201 addr
= virt_to_phys((void *)(data
->dest
));
202 if (upper_32_bits(addr
))
203 printf("Error found for upper 32 bits\n");
205 esdhc_write32(®s
->dsaddr
, lower_32_bits(addr
));
207 esdhc_write32(®s
->dsaddr
, (u32
)data
->dest
);
211 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
212 flush_dcache_range((ulong
)data
->src
,
213 (ulong
)data
->src
+data
->blocks
216 if (wml_value
> WML_WR_WML_MAX
)
217 wml_value
= WML_WR_WML_MAX_VAL
;
218 if ((esdhc_read32(®s
->prsstat
) & PRSSTAT_WPSPL
) == 0) {
219 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
223 esdhc_clrsetbits32(®s
->wml
, WML_WR_WML_MASK
,
225 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
226 #ifdef CONFIG_LS2085A
227 addr
= virt_to_phys((void *)(data
->src
));
228 if (upper_32_bits(addr
))
229 printf("Error found for upper 32 bits\n");
231 esdhc_write32(®s
->dsaddr
, lower_32_bits(addr
));
233 esdhc_write32(®s
->dsaddr
, (u32
)data
->src
);
238 esdhc_write32(®s
->blkattr
, data
->blocks
<< 16 | data
->blocksize
);
240 /* Calculate the timeout period for data transactions */
242 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
243 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
244 * So, Number of SD Clock cycles for 0.25sec should be minimum
245 * (SD Clock/sec * 0.25 sec) SD Clock cycles
246 * = (mmc->clock * 1/4) SD Clock cycles
248 * => (2^(timeout+13)) >= mmc->clock * 1/4
249 * Taking log2 both the sides
250 * => timeout + 13 >= log2(mmc->clock/4)
251 * Rounding up to next power of 2
252 * => timeout + 13 = log2(mmc->clock/4) + 1
253 * => timeout + 13 = fls(mmc->clock/4)
255 timeout
= fls(mmc
->clock
/4);
264 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
265 if ((timeout
== 4) || (timeout
== 8) || (timeout
== 12))
269 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
272 esdhc_clrsetbits32(®s
->sysctl
, SYSCTL_TIMEOUT_MASK
, timeout
<< 16);
277 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
278 static void check_and_invalidate_dcache_range
279 (struct mmc_cmd
*cmd
,
280 struct mmc_data
*data
) {
281 #ifdef CONFIG_LS2085A
284 unsigned start
= (unsigned)data
->dest
;
286 unsigned size
= roundup(ARCH_DMA_MINALIGN
,
287 data
->blocks
*data
->blocksize
);
288 unsigned end
= start
+size
;
289 #ifdef CONFIG_LS2085A
292 addr
= virt_to_phys((void *)(data
->dest
));
293 if (upper_32_bits(addr
))
294 printf("Error found for upper 32 bits\n");
296 start
= lower_32_bits(addr
);
298 invalidate_dcache_range(start
, end
);
303 * Sends a command out on the bus. Takes the mmc pointer,
304 * a command pointer, and an optional data pointer.
307 esdhc_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*cmd
, struct mmc_data
*data
)
312 struct fsl_esdhc_cfg
*cfg
= mmc
->priv
;
313 volatile struct fsl_esdhc
*regs
= (struct fsl_esdhc
*)cfg
->esdhc_base
;
315 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
316 if (cmd
->cmdidx
== MMC_CMD_STOP_TRANSMISSION
)
320 esdhc_write32(®s
->irqstat
, -1);
324 /* Wait for the bus to be idle */
325 while ((esdhc_read32(®s
->prsstat
) & PRSSTAT_CICHB
) ||
326 (esdhc_read32(®s
->prsstat
) & PRSSTAT_CIDHB
))
329 while (esdhc_read32(®s
->prsstat
) & PRSSTAT_DLA
)
332 /* Wait at least 8 SD clock cycles before the next command */
334 * Note: This is way more than 8 cycles, but 1ms seems to
335 * resolve timing issues with some cards
339 /* Set up for a data transfer if we have one */
341 err
= esdhc_setup_data(mmc
, data
);
346 /* Figure out the transfer arguments */
347 xfertyp
= esdhc_xfertyp(cmd
, data
);
350 esdhc_write32(®s
->irqsigen
, 0);
352 /* Send the command */
353 esdhc_write32(®s
->cmdarg
, cmd
->cmdarg
);
354 #if defined(CONFIG_FSL_USDHC)
355 esdhc_write32(®s
->mixctrl
,
356 (esdhc_read32(®s
->mixctrl
) & 0xFFFFFF80) | (xfertyp
& 0x7F)
357 | (mmc
->ddr_mode
? XFERTYP_DDREN
: 0));
358 esdhc_write32(®s
->xfertyp
, xfertyp
& 0xFFFF0000);
360 esdhc_write32(®s
->xfertyp
, xfertyp
);
363 /* Wait for the command to complete */
364 while (!(esdhc_read32(®s
->irqstat
) & (IRQSTAT_CC
| IRQSTAT_CTOE
)))
367 irqstat
= esdhc_read32(®s
->irqstat
);
369 if (irqstat
& CMD_ERR
) {
374 if (irqstat
& IRQSTAT_CTOE
) {
379 /* Switch voltage to 1.8V if CMD11 succeeded */
380 if (cmd
->cmdidx
== SD_CMD_SWITCH_UHS18V
) {
381 esdhc_setbits32(®s
->vendorspec
, ESDHC_VENDORSPEC_VSELECT
);
383 printf("Run CMD11 1.8V switch\n");
384 /* Sleep for 5 ms - max time for card to switch to 1.8V */
388 /* Workaround for ESDHC errata ENGcm03648 */
389 if (!data
&& (cmd
->resp_type
& MMC_RSP_BUSY
)) {
392 /* Poll on DATA0 line for cmd with busy signal for 250 ms */
393 while (timeout
> 0 && !(esdhc_read32(®s
->prsstat
) &
400 printf("Timeout waiting for DAT0 to go high!\n");
406 /* Copy the response to the response buffer */
407 if (cmd
->resp_type
& MMC_RSP_136
) {
408 u32 cmdrsp3
, cmdrsp2
, cmdrsp1
, cmdrsp0
;
410 cmdrsp3
= esdhc_read32(®s
->cmdrsp3
);
411 cmdrsp2
= esdhc_read32(®s
->cmdrsp2
);
412 cmdrsp1
= esdhc_read32(®s
->cmdrsp1
);
413 cmdrsp0
= esdhc_read32(®s
->cmdrsp0
);
414 cmd
->response
[0] = (cmdrsp3
<< 8) | (cmdrsp2
>> 24);
415 cmd
->response
[1] = (cmdrsp2
<< 8) | (cmdrsp1
>> 24);
416 cmd
->response
[2] = (cmdrsp1
<< 8) | (cmdrsp0
>> 24);
417 cmd
->response
[3] = (cmdrsp0
<< 8);
419 cmd
->response
[0] = esdhc_read32(®s
->cmdrsp0
);
421 /* Wait until all of the blocks are transferred */
423 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
424 esdhc_pio_read_write(mmc
, data
);
427 irqstat
= esdhc_read32(®s
->irqstat
);
429 if (irqstat
& IRQSTAT_DTOE
) {
434 if (irqstat
& DATA_ERR
) {
438 } while ((irqstat
& DATA_COMPLETE
) != DATA_COMPLETE
);
440 if (data
->flags
& MMC_DATA_READ
)
441 check_and_invalidate_dcache_range(cmd
, data
);
446 /* Reset CMD and DATA portions on error */
448 esdhc_write32(®s
->sysctl
, esdhc_read32(®s
->sysctl
) |
450 while (esdhc_read32(®s
->sysctl
) & SYSCTL_RSTC
)
454 esdhc_write32(®s
->sysctl
,
455 esdhc_read32(®s
->sysctl
) |
457 while ((esdhc_read32(®s
->sysctl
) & SYSCTL_RSTD
))
461 /* If this was CMD11, then notify that power cycle is needed */
462 if (cmd
->cmdidx
== SD_CMD_SWITCH_UHS18V
)
463 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
466 esdhc_write32(®s
->irqstat
, -1);
471 static void set_sysctl(struct mmc
*mmc
, uint clock
)
474 struct fsl_esdhc_cfg
*cfg
= mmc
->priv
;
475 volatile struct fsl_esdhc
*regs
= (struct fsl_esdhc
*)cfg
->esdhc_base
;
476 int sdhc_clk
= cfg
->sdhc_clk
;
479 if (clock
< mmc
->cfg
->f_min
)
480 clock
= mmc
->cfg
->f_min
;
482 if (sdhc_clk
/ 16 > clock
) {
483 for (pre_div
= 2; pre_div
< 256; pre_div
*= 2)
484 if ((sdhc_clk
/ pre_div
) <= (clock
* 16))
489 for (div
= 1; div
<= 16; div
++)
490 if ((sdhc_clk
/ (div
* pre_div
)) <= clock
)
493 pre_div
>>= mmc
->ddr_mode
? 2 : 1;
496 clk
= (pre_div
<< 8) | (div
<< 4);
498 esdhc_clrbits32(®s
->sysctl
, SYSCTL_CKEN
);
500 esdhc_clrsetbits32(®s
->sysctl
, SYSCTL_CLOCK_MASK
, clk
);
504 clk
= SYSCTL_PEREN
| SYSCTL_CKEN
;
506 esdhc_setbits32(®s
->sysctl
, clk
);
509 static void esdhc_set_ios(struct mmc
*mmc
)
511 struct fsl_esdhc_cfg
*cfg
= mmc
->priv
;
512 struct fsl_esdhc
*regs
= (struct fsl_esdhc
*)cfg
->esdhc_base
;
514 /* Set the clock speed */
515 set_sysctl(mmc
, mmc
->clock
);
517 /* Set the bus width */
518 esdhc_clrbits32(®s
->proctl
, PROCTL_DTW_4
| PROCTL_DTW_8
);
520 if (mmc
->bus_width
== 4)
521 esdhc_setbits32(®s
->proctl
, PROCTL_DTW_4
);
522 else if (mmc
->bus_width
== 8)
523 esdhc_setbits32(®s
->proctl
, PROCTL_DTW_8
);
527 static int esdhc_init(struct mmc
*mmc
)
529 struct fsl_esdhc_cfg
*cfg
= mmc
->priv
;
530 struct fsl_esdhc
*regs
= (struct fsl_esdhc
*)cfg
->esdhc_base
;
533 /* Reset the entire host controller */
534 esdhc_setbits32(®s
->sysctl
, SYSCTL_RSTA
);
536 /* Wait until the controller is available */
537 while ((esdhc_read32(®s
->sysctl
) & SYSCTL_RSTA
) && --timeout
)
541 /* Enable cache snooping */
542 esdhc_write32(®s
->scr
, 0x00000040);
545 esdhc_setbits32(®s
->sysctl
, SYSCTL_HCKEN
| SYSCTL_IPGEN
);
547 /* Set the initial clock speed */
548 mmc_set_clock(mmc
, 400000);
550 /* Disable the BRR and BWR bits in IRQSTAT */
551 esdhc_clrbits32(®s
->irqstaten
, IRQSTATEN_BRR
| IRQSTATEN_BWR
);
553 /* Put the PROCTL reg back to the default */
554 esdhc_write32(®s
->proctl
, PROCTL_INIT
);
556 /* Set timout to the maximum value */
557 esdhc_clrsetbits32(®s
->sysctl
, SYSCTL_TIMEOUT_MASK
, 14 << 16);
559 #ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
560 esdhc_setbits32(®s
->vendorspec
, ESDHC_VENDORSPEC_VSELECT
);
566 static int esdhc_getcd(struct mmc
*mmc
)
568 struct fsl_esdhc_cfg
*cfg
= mmc
->priv
;
569 struct fsl_esdhc
*regs
= (struct fsl_esdhc
*)cfg
->esdhc_base
;
572 #ifdef CONFIG_ESDHC_DETECT_QUIRK
573 if (CONFIG_ESDHC_DETECT_QUIRK
)
576 while (!(esdhc_read32(®s
->prsstat
) & PRSSTAT_CINS
) && --timeout
)
582 static void esdhc_reset(struct fsl_esdhc
*regs
)
584 unsigned long timeout
= 100; /* wait max 100 ms */
586 /* reset the controller */
587 esdhc_setbits32(®s
->sysctl
, SYSCTL_RSTA
);
589 /* hardware clears the bit when it is done */
590 while ((esdhc_read32(®s
->sysctl
) & SYSCTL_RSTA
) && --timeout
)
593 printf("MMC/SD: Reset never completed.\n");
596 static const struct mmc_ops esdhc_ops
= {
597 .send_cmd
= esdhc_send_cmd
,
598 .set_ios
= esdhc_set_ios
,
600 .getcd
= esdhc_getcd
,
603 int fsl_esdhc_initialize(bd_t
*bis
, struct fsl_esdhc_cfg
*cfg
)
605 struct fsl_esdhc
*regs
;
607 u32 caps
, voltage_caps
;
612 regs
= (struct fsl_esdhc
*)cfg
->esdhc_base
;
614 /* First reset the eSDHC controller */
617 esdhc_setbits32(®s
->sysctl
, SYSCTL_PEREN
| SYSCTL_HCKEN
618 | SYSCTL_IPGEN
| SYSCTL_CKEN
);
620 writel(SDHCI_IRQ_EN_BITS
, ®s
->irqstaten
);
621 memset(&cfg
->cfg
, 0, sizeof(cfg
->cfg
));
624 caps
= esdhc_read32(®s
->hostcapblt
);
626 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
627 caps
= caps
& ~(ESDHC_HOSTCAPBLT_SRS
|
628 ESDHC_HOSTCAPBLT_VS18
| ESDHC_HOSTCAPBLT_VS30
);
631 /* T4240 host controller capabilities register should have VS33 bit */
632 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
633 caps
= caps
| ESDHC_HOSTCAPBLT_VS33
;
636 if (caps
& ESDHC_HOSTCAPBLT_VS18
)
637 voltage_caps
|= MMC_VDD_165_195
;
638 if (caps
& ESDHC_HOSTCAPBLT_VS30
)
639 voltage_caps
|= MMC_VDD_29_30
| MMC_VDD_30_31
;
640 if (caps
& ESDHC_HOSTCAPBLT_VS33
)
641 voltage_caps
|= MMC_VDD_32_33
| MMC_VDD_33_34
;
643 cfg
->cfg
.name
= "FSL_SDHC";
644 cfg
->cfg
.ops
= &esdhc_ops
;
645 #ifdef CONFIG_SYS_SD_VOLTAGE
646 cfg
->cfg
.voltages
= CONFIG_SYS_SD_VOLTAGE
;
648 cfg
->cfg
.voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
;
650 if ((cfg
->cfg
.voltages
& voltage_caps
) == 0) {
651 printf("voltage not supported by controller\n");
655 cfg
->cfg
.host_caps
= MMC_MODE_4BIT
| MMC_MODE_8BIT
| MMC_MODE_HC
;
656 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
657 cfg
->cfg
.host_caps
|= MMC_MODE_DDR_52MHz
;
660 if (cfg
->max_bus_width
> 0) {
661 if (cfg
->max_bus_width
< 8)
662 cfg
->cfg
.host_caps
&= ~MMC_MODE_8BIT
;
663 if (cfg
->max_bus_width
< 4)
664 cfg
->cfg
.host_caps
&= ~MMC_MODE_4BIT
;
667 if (caps
& ESDHC_HOSTCAPBLT_HSS
)
668 cfg
->cfg
.host_caps
|= MMC_MODE_HS_52MHz
| MMC_MODE_HS
;
670 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
671 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK
)
672 cfg
->cfg
.host_caps
&= ~MMC_MODE_8BIT
;
675 cfg
->cfg
.f_min
= 400000;
676 cfg
->cfg
.f_max
= min(cfg
->sdhc_clk
, (u32
)52000000);
678 cfg
->cfg
.b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
680 mmc
= mmc_create(&cfg
->cfg
, cfg
);
687 int fsl_esdhc_mmc_init(bd_t
*bis
)
689 struct fsl_esdhc_cfg
*cfg
;
691 cfg
= calloc(sizeof(struct fsl_esdhc_cfg
), 1);
692 cfg
->esdhc_base
= CONFIG_SYS_FSL_ESDHC_ADDR
;
693 cfg
->sdhc_clk
= gd
->arch
.sdhc_clk
;
694 return fsl_esdhc_initialize(bis
, cfg
);
697 #ifdef CONFIG_OF_LIBFDT
698 void fdt_fixup_esdhc(void *blob
, bd_t
*bd
)
700 const char *compat
= "fsl,esdhc";
702 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
703 if (!hwconfig("esdhc")) {
704 do_fixup_by_compat(blob
, compat
, "status", "disabled",
710 do_fixup_by_compat_u32(blob
, compat
, "clock-frequency",
711 gd
->arch
.sdhc_clk
, 1);
713 do_fixup_by_compat(blob
, compat
, "status", "okay",