drivers/mmc/fsl_esdhc.c

   1 /*
   2  * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
   3  * Andy Fleming
   4  *
   5  * Based vaguely on the pxa mmc code:
   6  * (C) Copyright 2003
   7  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <config.h>
  29 #include <common.h>
  30 #include <command.h>
  31 #include <hwconfig.h>
  32 #include <mmc.h>
  33 #include <part.h>
  34 #include <malloc.h>
  35 #include <mmc.h>
  36 #include <fsl_esdhc.h>
  37 #include <fdt_support.h>
  38 #include <asm/io.h>
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 struct fsl_esdhc {
  43         uint    dsaddr;
  44         uint    blkattr;
  45         uint    cmdarg;
  46         uint    xfertyp;
  47         uint    cmdrsp0;
  48         uint    cmdrsp1;
  49         uint    cmdrsp2;
  50         uint    cmdrsp3;
  51         uint    datport;
  52         uint    prsstat;
  53         uint    proctl;
  54         uint    sysctl;
  55         uint    irqstat;
  56         uint    irqstaten;
  57         uint    irqsigen;
  58         uint    autoc12err;
  59         uint    hostcapblt;
  60         uint    wml;
  61         uint    mixctrl;
  62         char    reserved1[4];
  63         uint    fevt;
  64         char    reserved2[168];
  65         uint    hostver;
  66         char    reserved3[780];
  67         uint    scr;
  68 };
  69
  70 /* Return the XFERTYP flags for a given command and data packet */
  71 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
  72 {
  73         uint xfertyp = 0;
  74
  75         if (data) {
  76                 xfertyp |= XFERTYP_DPSEL;
  77 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  78                 xfertyp |= XFERTYP_DMAEN;
  79 #endif
  80                 if (data->blocks > 1) {
  81                         xfertyp |= XFERTYP_MSBSEL;
  82                         xfertyp |= XFERTYP_BCEN;
  83 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
  84                         xfertyp |= XFERTYP_AC12EN;
  85 #endif
  86                 }
  87
  88                 if (data->flags & MMC_DATA_READ)
  89                         xfertyp |= XFERTYP_DTDSEL;
  90         }
  91
  92         if (cmd->resp_type & MMC_RSP_CRC)
  93                 xfertyp |= XFERTYP_CCCEN;
  94         if (cmd->resp_type & MMC_RSP_OPCODE)
  95                 xfertyp |= XFERTYP_CICEN;
  96         if (cmd->resp_type & MMC_RSP_136)
  97                 xfertyp |= XFERTYP_RSPTYP_136;
  98         else if (cmd->resp_type & MMC_RSP_BUSY)
  99                 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
 100         else if (cmd->resp_type & MMC_RSP_PRESENT)
 101                 xfertyp |= XFERTYP_RSPTYP_48;
 102
 103 #ifdef CONFIG_MX53
 104         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 105                 xfertyp |= XFERTYP_CMDTYP_ABORT;
 106 #endif
 107         return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
 108 }
 109
 110 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
 111 /*
 112  * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
 113  */
 114 static void
 115 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
 116 {
 117         struct fsl_esdhc_cfg *cfg = mmc->priv;
 118         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 119         uint blocks;
 120         char *buffer;
 121         uint databuf;
 122         uint size;
 123         uint irqstat;
 124         uint timeout;
 125
 126         if (data->flags & MMC_DATA_READ) {
 127                 blocks = data->blocks;
 128                 buffer = data->dest;
 129                 while (blocks) {
 130                         timeout = PIO_TIMEOUT;
 131                         size = data->blocksize;
 132                         irqstat = esdhc_read32(&regs->irqstat);
 133                         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
 134                                 && --timeout);
 135                         if (timeout <= 0) {
 136                                 printf("\nData Read Failed in PIO Mode.");
 137                                 return;
 138                         }
 139                         while (size && (!(irqstat & IRQSTAT_TC))) {
 140                                 udelay(100); /* Wait before last byte transfer complete */
 141                                 irqstat = esdhc_read32(&regs->irqstat);
 142                                 databuf = in_le32(&regs->datport);
 143                                 *((uint *)buffer) = databuf;
 144                                 buffer += 4;
 145                                 size -= 4;
 146                         }
 147                         blocks--;
 148                 }
 149         } else {
 150                 blocks = data->blocks;
 151                 buffer = (char *)data->src;
 152                 while (blocks) {
 153                         timeout = PIO_TIMEOUT;
 154                         size = data->blocksize;
 155                         irqstat = esdhc_read32(&regs->irqstat);
 156                         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
 157                                 && --timeout);
 158                         if (timeout <= 0) {
 159                                 printf("\nData Write Failed in PIO Mode.");
 160                                 return;
 161                         }
 162                         while (size && (!(irqstat & IRQSTAT_TC))) {
 163                                 udelay(100); /* Wait before last byte transfer complete */
 164                                 databuf = *((uint *)buffer);
 165                                 buffer += 4;
 166                                 size -= 4;
 167                                 irqstat = esdhc_read32(&regs->irqstat);
 168                                 out_le32(&regs->datport, databuf);
 169                         }
 170                         blocks--;
 171                 }
 172         }
 173 }
 174 #endif
 175
 176 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 177 {
 178         int timeout;
 179         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 180         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 181 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 182         uint wml_value;
 183
 184         wml_value = data->blocksize/4;
 185
 186         if (data->flags & MMC_DATA_READ) {
 187                 if (wml_value > WML_RD_WML_MAX)
 188                         wml_value = WML_RD_WML_MAX_VAL;
 189
 190                 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
 191                 esdhc_write32(&regs->dsaddr, (u32)data->dest);
 192         } else {
 193                 flush_dcache_range((ulong)data->src,
 194                                    (ulong)data->src+data->blocks
 195                                          *data->blocksize);
 196
 197                 if (wml_value > WML_WR_WML_MAX)
 198                         wml_value = WML_WR_WML_MAX_VAL;
 199                 if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
 200                         printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
 201                         return TIMEOUT;
 202                 }
 203
 204                 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
 205                                         wml_value << 16);
 206                 esdhc_write32(&regs->dsaddr, (u32)data->src);
 207         }
 208 #else   /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
 209         if (!(data->flags & MMC_DATA_READ)) {
 210                 if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
 211                         printf("\nThe SD card is locked. "
 212                                 "Can not write to a locked card.\n\n");
 213                         return TIMEOUT;
 214                 }
 215                 esdhc_write32(&regs->dsaddr, (u32)data->src);
 216         } else
 217                 esdhc_write32(&regs->dsaddr, (u32)data->dest);
 218 #endif  /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
 219
 220         esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
 221
 222         /* Calculate the timeout period for data transactions */
 223         /*
 224          * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
 225          * 2)Timeout period should be minimum 0.250sec as per SD Card spec
 226          *  So, Number of SD Clock cycles for 0.25sec should be minimum
 227          *              (SD Clock/sec * 0.25 sec) SD Clock cycles
 228          *              = (mmc->tran_speed * 1/4) SD Clock cycles
 229          * As 1) >=  2)
 230          * => (2^(timeout+13)) >= mmc->tran_speed * 1/4
 231          * Taking log2 both the sides
 232          * => timeout + 13 >= log2(mmc->tran_speed/4)
 233          * Rounding up to next power of 2
 234          * => timeout + 13 = log2(mmc->tran_speed/4) + 1
 235          * => timeout + 13 = fls(mmc->tran_speed/4)
 236          */
 237         timeout = fls(mmc->tran_speed/4);
 238         timeout -= 13;
 239
 240         if (timeout > 14)
 241                 timeout = 14;
 242
 243         if (timeout < 0)
 244                 timeout = 0;
 245
 246 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
 247         if ((timeout == 4) || (timeout == 8) || (timeout == 12))
 248                 timeout++;
 249 #endif
 250
 251         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
 252
 253         return 0;
 254 }
 255
 256 static void check_and_invalidate_dcache_range
 257         (struct mmc_cmd *cmd,
 258          struct mmc_data *data) {
 259         unsigned start = (unsigned)data->dest ;
 260         unsigned size = roundup(ARCH_DMA_MINALIGN,
 261                                 data->blocks*data->blocksize);
 262         unsigned end = start+size ;
 263         invalidate_dcache_range(start, end);
 264 }
 265 /*
 266  * Sends a command out on the bus.  Takes the mmc pointer,
 267  * a command pointer, and an optional data pointer.
 268  */
 269 static int
 270 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 271 {
 272         uint    xfertyp;
 273         uint    irqstat;
 274         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 275         volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 276
 277 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
 278         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 279                 return 0;
 280 #endif
 281
 282         esdhc_write32(&regs->irqstat, -1);
 283
 284         sync();
 285
 286         /* Wait for the bus to be idle */
 287         while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
 288                         (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
 289                 ;
 290
 291         while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
 292                 ;
 293
 294         /* Wait at least 8 SD clock cycles before the next command */
 295         /*
 296          * Note: This is way more than 8 cycles, but 1ms seems to
 297          * resolve timing issues with some cards
 298          */
 299         udelay(1000);
 300
 301         /* Set up for a data transfer if we have one */
 302         if (data) {
 303                 int err;
 304
 305                 err = esdhc_setup_data(mmc, data);
 306                 if(err)
 307                         return err;
 308         }
 309
 310         /* Figure out the transfer arguments */
 311         xfertyp = esdhc_xfertyp(cmd, data);
 312
 313         /* Send the command */
 314         esdhc_write32(&regs->cmdarg, cmd->cmdarg);
 315 #if defined(CONFIG_FSL_USDHC)
 316         esdhc_write32(&regs->mixctrl,
 317         (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));
 318         esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
 319 #else
 320         esdhc_write32(&regs->xfertyp, xfertyp);
 321 #endif
 322
 323         /* Mask all irqs */
 324         esdhc_write32(&regs->irqsigen, 0);
 325
 326         /* Wait for the command to complete */
 327         while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
 328                 ;
 329
 330         if (data && (data->flags & MMC_DATA_READ))
 331                 check_and_invalidate_dcache_range(cmd, data);
 332
 333         irqstat = esdhc_read32(&regs->irqstat);
 334         esdhc_write32(&regs->irqstat, irqstat);
 335
 336         /* Reset CMD and DATA portions on error */
 337         if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) {
 338                 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
 339                               SYSCTL_RSTC);
 340                 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
 341                         ;
 342
 343                 if (data) {
 344                         esdhc_write32(&regs->sysctl,
 345                                       esdhc_read32(&regs->sysctl) |
 346                                       SYSCTL_RSTD);
 347                         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
 348                                 ;
 349                 }
 350         }
 351
 352         if (irqstat & CMD_ERR)
 353                 return COMM_ERR;
 354
 355         if (irqstat & IRQSTAT_CTOE)
 356                 return TIMEOUT;
 357
 358         /* Workaround for ESDHC errata ENGcm03648 */
 359         if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
 360                 int timeout = 2500;
 361
 362                 /* Poll on DATA0 line for cmd with busy signal for 250 ms */
 363                 while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
 364                                         PRSSTAT_DAT0)) {
 365                         udelay(100);
 366                         timeout--;
 367                 }
 368
 369                 if (timeout <= 0) {
 370                         printf("Timeout waiting for DAT0 to go high!\n");
 371                         return TIMEOUT;
 372                 }
 373         }
 374
 375         /* Copy the response to the response buffer */
 376         if (cmd->resp_type & MMC_RSP_136) {
 377                 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
 378
 379                 cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
 380                 cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
 381                 cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
 382                 cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
 383                 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
 384                 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
 385                 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
 386                 cmd->response[3] = (cmdrsp0 << 8);
 387         } else
 388                 cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
 389
 390         /* Wait until all of the blocks are transferred */
 391         if (data) {
 392 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
 393                 esdhc_pio_read_write(mmc, data);
 394 #else
 395                 do {
 396                         irqstat = esdhc_read32(&regs->irqstat);
 397
 398                         if (irqstat & IRQSTAT_DTOE)
 399                                 return TIMEOUT;
 400
 401                         if (irqstat & DATA_ERR)
 402                                 return COMM_ERR;
 403                 } while (!(irqstat & IRQSTAT_TC) &&
 404                                 (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA));
 405 #endif
 406         }
 407
 408         esdhc_write32(&regs->irqstat, -1);
 409
 410         return 0;
 411 }
 412
 413 static void set_sysctl(struct mmc *mmc, uint clock)
 414 {
 415         int div, pre_div;
 416         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 417         volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 418         int sdhc_clk = cfg->sdhc_clk;
 419         uint clk;
 420
 421         if (clock < mmc->f_min)
 422                 clock = mmc->f_min;
 423
 424         if (sdhc_clk / 16 > clock) {
 425                 for (pre_div = 2; pre_div < 256; pre_div *= 2)
 426                         if ((sdhc_clk / pre_div) <= (clock * 16))
 427                                 break;
 428         } else
 429                 pre_div = 2;
 430
 431         for (div = 1; div <= 16; div++)
 432                 if ((sdhc_clk / (div * pre_div)) <= clock)
 433                         break;
 434
 435         pre_div >>= 1;
 436         div -= 1;
 437
 438         clk = (pre_div << 8) | (div << 4);
 439
 440         esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
 441
 442         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
 443
 444         udelay(10000);
 445
 446         clk = SYSCTL_PEREN | SYSCTL_CKEN;
 447
 448         esdhc_setbits32(&regs->sysctl, clk);
 449 }
 450
 451 static void esdhc_set_ios(struct mmc *mmc)
 452 {
 453         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 454         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 455
 456         /* Set the clock speed */
 457         set_sysctl(mmc, mmc->clock);
 458
 459         /* Set the bus width */
 460         esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
 461
 462         if (mmc->bus_width == 4)
 463                 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
 464         else if (mmc->bus_width == 8)
 465                 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
 466
 467 }
 468
 469 static int esdhc_init(struct mmc *mmc)
 470 {
 471         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 472         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 473         int timeout = 1000;
 474
 475         /* Reset the entire host controller */
 476         esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
 477
 478         /* Wait until the controller is available */
 479         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
 480                 udelay(1000);
 481
 482 #ifndef ARCH_MXC
 483         /* Enable cache snooping */
 484         esdhc_write32(&regs->scr, 0x00000040);
 485 #endif
 486
 487         esdhc_write32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
 488
 489         /* Set the initial clock speed */
 490         mmc_set_clock(mmc, 400000);
 491
 492         /* Disable the BRR and BWR bits in IRQSTAT */
 493         esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
 494
 495         /* Put the PROCTL reg back to the default */
 496         esdhc_write32(&regs->proctl, PROCTL_INIT);
 497
 498         /* Set timout to the maximum value */
 499         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
 500
 501         return 0;
 502 }
 503
 504 static int esdhc_getcd(struct mmc *mmc)
 505 {
 506         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 507         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 508         int timeout = 1000;
 509
 510         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
 511                 udelay(1000);
 512
 513         return timeout > 0;
 514 }
 515
 516 static void esdhc_reset(struct fsl_esdhc *regs)
 517 {
 518         unsigned long timeout = 100; /* wait max 100 ms */
 519
 520         /* reset the controller */
 521         esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
 522
 523         /* hardware clears the bit when it is done */
 524         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
 525                 udelay(1000);
 526         if (!timeout)
 527                 printf("MMC/SD: Reset never completed.\n");
 528 }
 529
 530 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 531 {
 532         struct fsl_esdhc *regs;
 533         struct mmc *mmc;
 534         u32 caps, voltage_caps;
 535
 536         if (!cfg)
 537                 return -1;
 538
 539         mmc = malloc(sizeof(struct mmc));
 540
 541         sprintf(mmc->name, "FSL_SDHC");
 542         regs = (struct fsl_esdhc *)cfg->esdhc_base;
 543
 544         /* First reset the eSDHC controller */
 545         esdhc_reset(regs);
 546
 547         esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
 548                                 | SYSCTL_IPGEN | SYSCTL_CKEN);
 549
 550         mmc->priv = cfg;
 551         mmc->send_cmd = esdhc_send_cmd;
 552         mmc->set_ios = esdhc_set_ios;
 553         mmc->init = esdhc_init;
 554         mmc->getcd = esdhc_getcd;
 555         mmc->getwp = NULL;
 556
 557         voltage_caps = 0;
 558         caps = regs->hostcapblt;
 559
 560 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
 561         caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
 562                         ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
 563 #endif
 564         if (caps & ESDHC_HOSTCAPBLT_VS18)
 565                 voltage_caps |= MMC_VDD_165_195;
 566         if (caps & ESDHC_HOSTCAPBLT_VS30)
 567                 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
 568         if (caps & ESDHC_HOSTCAPBLT_VS33)
 569                 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
 570
 571 #ifdef CONFIG_SYS_SD_VOLTAGE
 572         mmc->voltages = CONFIG_SYS_SD_VOLTAGE;
 573 #else
 574         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 575 #endif
 576         if ((mmc->voltages & voltage_caps) == 0) {
 577                 printf("voltage not supported by controller\n");
 578                 return -1;
 579         }
 580
 581         mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
 582
 583         if (cfg->max_bus_width > 0) {
 584                 if (cfg->max_bus_width < 8)
 585                         mmc->host_caps &= ~MMC_MODE_8BIT;
 586                 if (cfg->max_bus_width < 4)
 587                         mmc->host_caps &= ~MMC_MODE_4BIT;
 588         }
 589
 590         if (caps & ESDHC_HOSTCAPBLT_HSS)
 591                 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 592
 593         mmc->f_min = 400000;
 594         mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000);
 595
 596         mmc->b_max = 0;
 597         mmc_register(mmc);
 598
 599         return 0;
 600 }
 601
 602 int fsl_esdhc_mmc_init(bd_t *bis)
 603 {
 604         struct fsl_esdhc_cfg *cfg;
 605
 606         cfg = malloc(sizeof(struct fsl_esdhc_cfg));
 607         memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
 608         cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
 609         cfg->sdhc_clk = gd->arch.sdhc_clk;
 610         return fsl_esdhc_initialize(bis, cfg);
 611 }
 612
 613 #ifdef CONFIG_OF_LIBFDT
 614 void fdt_fixup_esdhc(void *blob, bd_t *bd)
 615 {
 616         const char *compat = "fsl,esdhc";
 617
 618 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
 619         if (!hwconfig("esdhc")) {
 620                 do_fixup_by_compat(blob, compat, "status", "disabled",
 621                                 8 + 1, 1);
 622                 return;
 623         }
 624 #endif
 625
 626         do_fixup_by_compat_u32(blob, compat, "clock-frequency",
 627                                gd->arch.sdhc_clk, 1);
 628
 629         do_fixup_by_compat(blob, compat, "status", "okay",
 630                            4 + 1, 1);
 631 }
 632 #endif