drivers/mmc/fsl_esdhc.c

   1 /*
   2  * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
   3  * Andy Fleming
   4  *
   5  * Based vaguely on the pxa mmc code:
   6  * (C) Copyright 2003
   7  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <config.h>
  13 #include <common.h>
  14 #include <command.h>
  15 #include <errno.h>
  16 #include <hwconfig.h>
  17 #include <mmc.h>
  18 #include <part.h>
  19 #include <power/regulator.h>
  20 #include <malloc.h>
  21 #include <fsl_esdhc.h>
  22 #include <fdt_support.h>
  23 #include <asm/io.h>
  24 #include <dm.h>
  25 #include <asm-generic/gpio.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #define SDHCI_IRQ_EN_BITS               (IRQSTATEN_CC | IRQSTATEN_TC | \
  30                                 IRQSTATEN_CINT | \
  31                                 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
  32                                 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
  33                                 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
  34                                 IRQSTATEN_DINT)
  35
  36 struct fsl_esdhc {
  37         uint    dsaddr;         /* SDMA system address register */
  38         uint    blkattr;        /* Block attributes register */
  39         uint    cmdarg;         /* Command argument register */
  40         uint    xfertyp;        /* Transfer type register */
  41         uint    cmdrsp0;        /* Command response 0 register */
  42         uint    cmdrsp1;        /* Command response 1 register */
  43         uint    cmdrsp2;        /* Command response 2 register */
  44         uint    cmdrsp3;        /* Command response 3 register */
  45         uint    datport;        /* Buffer data port register */
  46         uint    prsstat;        /* Present state register */
  47         uint    proctl;         /* Protocol control register */
  48         uint    sysctl;         /* System Control Register */
  49         uint    irqstat;        /* Interrupt status register */
  50         uint    irqstaten;      /* Interrupt status enable register */
  51         uint    irqsigen;       /* Interrupt signal enable register */
  52         uint    autoc12err;     /* Auto CMD error status register */
  53         uint    hostcapblt;     /* Host controller capabilities register */
  54         uint    wml;            /* Watermark level register */
  55         uint    mixctrl;        /* For USDHC */
  56         char    reserved1[4];   /* reserved */
  57         uint    fevt;           /* Force event register */
  58         uint    admaes;         /* ADMA error status register */
  59         uint    adsaddr;        /* ADMA system address register */
  60         char    reserved2[4];
  61         uint    dllctrl;
  62         uint    dllstat;
  63         uint    clktunectrlstatus;
  64         char    reserved3[84];
  65         uint    vendorspec;
  66         uint    mmcboot;
  67         uint    vendorspec2;
  68         char    reserved4[48];
  69         uint    hostver;        /* Host controller version register */
  70         char    reserved5[4];   /* reserved */
  71         uint    dmaerraddr;     /* DMA error address register */
  72         char    reserved6[4];   /* reserved */
  73         uint    dmaerrattr;     /* DMA error attribute register */
  74         char    reserved7[4];   /* reserved */
  75         uint    hostcapblt2;    /* Host controller capabilities register 2 */
  76         char    reserved8[8];   /* reserved */
  77         uint    tcr;            /* Tuning control register */
  78         char    reserved9[28];  /* reserved */
  79         uint    sddirctl;       /* SD direction control register */
  80         char    reserved10[712];/* reserved */
  81         uint    scr;            /* eSDHC control register */
  82 };
  83
  84 struct fsl_esdhc_plat {
  85         struct mmc_config cfg;
  86         struct mmc mmc;
  87 };
  88
  89 /**
  90  * struct fsl_esdhc_priv
  91  *
  92  * @esdhc_regs: registers of the sdhc controller
  93  * @sdhc_clk: Current clk of the sdhc controller
  94  * @bus_width: bus width, 1bit, 4bit or 8bit
  95  * @cfg: mmc config
  96  * @mmc: mmc
  97  * Following is used when Driver Model is enabled for MMC
  98  * @dev: pointer for the device
  99  * @non_removable: 0: removable; 1: non-removable
 100  * @wp_enable: 1: enable checking wp; 0: no check
 101  * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
 102  * @cd_gpio: gpio for card detection
 103  * @wp_gpio: gpio for write protection
 104  */
 105 struct fsl_esdhc_priv {
 106         struct fsl_esdhc *esdhc_regs;
 107         unsigned int sdhc_clk;
 108         unsigned int bus_width;
 109 #if !CONFIG_IS_ENABLED(BLK)
 110         struct mmc *mmc;
 111 #endif
 112         struct udevice *dev;
 113         int non_removable;
 114         int wp_enable;
 115         int vs18_enable;
 116 #ifdef CONFIG_DM_GPIO
 117         struct gpio_desc cd_gpio;
 118         struct gpio_desc wp_gpio;
 119 #endif
 120 };
 121
 122 /* Return the XFERTYP flags for a given command and data packet */
 123 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
 124 {
 125         uint xfertyp = 0;
 126
 127         if (data) {
 128                 xfertyp |= XFERTYP_DPSEL;
 129 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 130                 xfertyp |= XFERTYP_DMAEN;
 131 #endif
 132                 if (data->blocks > 1) {
 133                         xfertyp |= XFERTYP_MSBSEL;
 134                         xfertyp |= XFERTYP_BCEN;
 135 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
 136                         xfertyp |= XFERTYP_AC12EN;
 137 #endif
 138                 }
 139
 140                 if (data->flags & MMC_DATA_READ)
 141                         xfertyp |= XFERTYP_DTDSEL;
 142         }
 143
 144         if (cmd->resp_type & MMC_RSP_CRC)
 145                 xfertyp |= XFERTYP_CCCEN;
 146         if (cmd->resp_type & MMC_RSP_OPCODE)
 147                 xfertyp |= XFERTYP_CICEN;
 148         if (cmd->resp_type & MMC_RSP_136)
 149                 xfertyp |= XFERTYP_RSPTYP_136;
 150         else if (cmd->resp_type & MMC_RSP_BUSY)
 151                 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
 152         else if (cmd->resp_type & MMC_RSP_PRESENT)
 153                 xfertyp |= XFERTYP_RSPTYP_48;
 154
 155         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 156                 xfertyp |= XFERTYP_CMDTYP_ABORT;
 157
 158         return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
 159 }
 160
 161 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
 162 /*
 163  * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
 164  */
 165 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
 166                                  struct mmc_data *data)
 167 {
 168         struct fsl_esdhc *regs = priv->esdhc_regs;
 169         uint blocks;
 170         char *buffer;
 171         uint databuf;
 172         uint size;
 173         uint irqstat;
 174         ulong start;
 175
 176         if (data->flags & MMC_DATA_READ) {
 177                 blocks = data->blocks;
 178                 buffer = data->dest;
 179                 while (blocks) {
 180                         start = get_timer(0);
 181                         size = data->blocksize;
 182                         irqstat = esdhc_read32(&regs->irqstat);
 183                         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {
 184                                 if (get_timer(start) > PIO_TIMEOUT) {
 185                                         printf("\nData Read Failed in PIO Mode.");
 186                                         return;
 187                                 }
 188                         }
 189                         while (size && (!(irqstat & IRQSTAT_TC))) {
 190                                 udelay(100); /* Wait before last byte transfer complete */
 191                                 irqstat = esdhc_read32(&regs->irqstat);
 192                                 databuf = in_le32(&regs->datport);
 193                                 *((uint *)buffer) = databuf;
 194                                 buffer += 4;
 195                                 size -= 4;
 196                         }
 197                         blocks--;
 198                 }
 199         } else {
 200                 blocks = data->blocks;
 201                 buffer = (char *)data->src;
 202                 while (blocks) {
 203                         start = get_timer(0);
 204                         size = data->blocksize;
 205                         irqstat = esdhc_read32(&regs->irqstat);
 206                         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {
 207                                 if (get_timer(start) > PIO_TIMEOUT) {
 208                                         printf("\nData Write Failed in PIO Mode.");
 209                                         return;
 210                                 }
 211                         }
 212                         while (size && (!(irqstat & IRQSTAT_TC))) {
 213                                 udelay(100); /* Wait before last byte transfer complete */
 214                                 databuf = *((uint *)buffer);
 215                                 buffer += 4;
 216                                 size -= 4;
 217                                 irqstat = esdhc_read32(&regs->irqstat);
 218                                 out_le32(&regs->datport, databuf);
 219                         }
 220                         blocks--;
 221                 }
 222         }
 223 }
 224 #endif
 225
 226 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
 227                             struct mmc_data *data)
 228 {
 229         int timeout;
 230         struct fsl_esdhc *regs = priv->esdhc_regs;
 231 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
 232         defined(CONFIG_MX8M)
 233         dma_addr_t addr;
 234 #endif
 235         uint wml_value;
 236
 237         wml_value = data->blocksize/4;
 238
 239         if (data->flags & MMC_DATA_READ) {
 240                 if (wml_value > WML_RD_WML_MAX)
 241                         wml_value = WML_RD_WML_MAX_VAL;
 242
 243                 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
 244 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 245 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
 246         defined(CONFIG_MX8M)
 247                 addr = virt_to_phys((void *)(data->dest));
 248                 if (upper_32_bits(addr))
 249                         printf("Error found for upper 32 bits\n");
 250                 else
 251                         esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
 252 #else
 253                 esdhc_write32(&regs->dsaddr, (u32)data->dest);
 254 #endif
 255 #endif
 256         } else {
 257 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 258                 flush_dcache_range((ulong)data->src,
 259                                    (ulong)data->src+data->blocks
 260                                          *data->blocksize);
 261 #endif
 262                 if (wml_value > WML_WR_WML_MAX)
 263                         wml_value = WML_WR_WML_MAX_VAL;
 264                 if (priv->wp_enable) {
 265                         if ((esdhc_read32(&regs->prsstat) &
 266                             PRSSTAT_WPSPL) == 0) {
 267                                 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
 268                                 return -ETIMEDOUT;
 269                         }
 270                 }
 271
 272                 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
 273                                         wml_value << 16);
 274 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 275 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
 276         defined(CONFIG_MX8M)
 277                 addr = virt_to_phys((void *)(data->src));
 278                 if (upper_32_bits(addr))
 279                         printf("Error found for upper 32 bits\n");
 280                 else
 281                         esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
 282 #else
 283                 esdhc_write32(&regs->dsaddr, (u32)data->src);
 284 #endif
 285 #endif
 286         }
 287
 288         esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
 289
 290         /* Calculate the timeout period for data transactions */
 291         /*
 292          * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
 293          * 2)Timeout period should be minimum 0.250sec as per SD Card spec
 294          *  So, Number of SD Clock cycles for 0.25sec should be minimum
 295          *              (SD Clock/sec * 0.25 sec) SD Clock cycles
 296          *              = (mmc->clock * 1/4) SD Clock cycles
 297          * As 1) >=  2)
 298          * => (2^(timeout+13)) >= mmc->clock * 1/4
 299          * Taking log2 both the sides
 300          * => timeout + 13 >= log2(mmc->clock/4)
 301          * Rounding up to next power of 2
 302          * => timeout + 13 = log2(mmc->clock/4) + 1
 303          * => timeout + 13 = fls(mmc->clock/4)
 304          *
 305          * However, the MMC spec "It is strongly recommended for hosts to
 306          * implement more than 500ms timeout value even if the card
 307          * indicates the 250ms maximum busy length."  Even the previous
 308          * value of 300ms is known to be insufficient for some cards.
 309          * So, we use
 310          * => timeout + 13 = fls(mmc->clock/2)
 311          */
 312         timeout = fls(mmc->clock/2);
 313         timeout -= 13;
 314
 315         if (timeout > 14)
 316                 timeout = 14;
 317
 318         if (timeout < 0)
 319                 timeout = 0;
 320
 321 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
 322         if ((timeout == 4) || (timeout == 8) || (timeout == 12))
 323                 timeout++;
 324 #endif
 325
 326 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 327         timeout = 0xE;
 328 #endif
 329         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
 330
 331         return 0;
 332 }
 333
 334 static void check_and_invalidate_dcache_range
 335         (struct mmc_cmd *cmd,
 336          struct mmc_data *data) {
 337         unsigned start = 0;
 338         unsigned end = 0;
 339         unsigned size = roundup(ARCH_DMA_MINALIGN,
 340                                 data->blocks*data->blocksize);
 341 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
 342         defined(CONFIG_MX8M)
 343         dma_addr_t addr;
 344
 345         addr = virt_to_phys((void *)(data->dest));
 346         if (upper_32_bits(addr))
 347                 printf("Error found for upper 32 bits\n");
 348         else
 349                 start = lower_32_bits(addr);
 350 #else
 351         start = (unsigned)data->dest;
 352 #endif
 353         end = start + size;
 354         invalidate_dcache_range(start, end);
 355 }
 356
 357 /*
 358  * Sends a command out on the bus.  Takes the mmc pointer,
 359  * a command pointer, and an optional data pointer.
 360  */
 361 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
 362                                  struct mmc_cmd *cmd, struct mmc_data *data)
 363 {
 364         int     err = 0;
 365         uint    xfertyp;
 366         uint    irqstat;
 367         struct fsl_esdhc *regs = priv->esdhc_regs;
 368
 369 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
 370         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 371                 return 0;
 372 #endif
 373
 374         esdhc_write32(&regs->irqstat, -1);
 375
 376         sync();
 377
 378         /* Wait for the bus to be idle */
 379         while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
 380                         (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
 381                 ;
 382
 383         while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
 384                 ;
 385
 386         /* Wait at least 8 SD clock cycles before the next command */
 387         /*
 388          * Note: This is way more than 8 cycles, but 1ms seems to
 389          * resolve timing issues with some cards
 390          */
 391         udelay(1000);
 392
 393         /* Set up for a data transfer if we have one */
 394         if (data) {
 395                 err = esdhc_setup_data(priv, mmc, data);
 396                 if(err)
 397                         return err;
 398
 399                 if (data->flags & MMC_DATA_READ)
 400                         check_and_invalidate_dcache_range(cmd, data);
 401         }
 402
 403         /* Figure out the transfer arguments */
 404         xfertyp = esdhc_xfertyp(cmd, data);
 405
 406         /* Mask all irqs */
 407         esdhc_write32(&regs->irqsigen, 0);
 408
 409         /* Send the command */
 410         esdhc_write32(&regs->cmdarg, cmd->cmdarg);
 411 #if defined(CONFIG_FSL_USDHC)
 412         esdhc_write32(&regs->mixctrl,
 413         (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
 414                         | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
 415         esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
 416 #else
 417         esdhc_write32(&regs->xfertyp, xfertyp);
 418 #endif
 419
 420         /* Wait for the command to complete */
 421         while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
 422                 ;
 423
 424         irqstat = esdhc_read32(&regs->irqstat);
 425
 426         if (irqstat & CMD_ERR) {
 427                 err = -ECOMM;
 428                 goto out;
 429         }
 430
 431         if (irqstat & IRQSTAT_CTOE) {
 432                 err = -ETIMEDOUT;
 433                 goto out;
 434         }
 435
 436         /* Switch voltage to 1.8V if CMD11 succeeded */
 437         if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
 438                 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
 439
 440                 printf("Run CMD11 1.8V switch\n");
 441                 /* Sleep for 5 ms - max time for card to switch to 1.8V */
 442                 udelay(5000);
 443         }
 444
 445         /* Workaround for ESDHC errata ENGcm03648 */
 446         if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
 447                 int timeout = 6000;
 448
 449                 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
 450                 while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
 451                                         PRSSTAT_DAT0)) {
 452                         udelay(100);
 453                         timeout--;
 454                 }
 455
 456                 if (timeout <= 0) {
 457                         printf("Timeout waiting for DAT0 to go high!\n");
 458                         err = -ETIMEDOUT;
 459                         goto out;
 460                 }
 461         }
 462
 463         /* Copy the response to the response buffer */
 464         if (cmd->resp_type & MMC_RSP_136) {
 465                 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
 466
 467                 cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
 468                 cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
 469                 cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
 470                 cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
 471                 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
 472                 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
 473                 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
 474                 cmd->response[3] = (cmdrsp0 << 8);
 475         } else
 476                 cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
 477
 478         /* Wait until all of the blocks are transferred */
 479         if (data) {
 480 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
 481                 esdhc_pio_read_write(priv, data);
 482 #else
 483                 do {
 484                         irqstat = esdhc_read32(&regs->irqstat);
 485
 486                         if (irqstat & IRQSTAT_DTOE) {
 487                                 err = -ETIMEDOUT;
 488                                 goto out;
 489                         }
 490
 491                         if (irqstat & DATA_ERR) {
 492                                 err = -ECOMM;
 493                                 goto out;
 494                         }
 495                 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
 496
 497                 /*
 498                  * Need invalidate the dcache here again to avoid any
 499                  * cache-fill during the DMA operations such as the
 500                  * speculative pre-fetching etc.
 501                  */
 502                 if (data->flags & MMC_DATA_READ)
 503                         check_and_invalidate_dcache_range(cmd, data);
 504 #endif
 505         }
 506
 507 out:
 508         /* Reset CMD and DATA portions on error */
 509         if (err) {
 510                 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
 511                               SYSCTL_RSTC);
 512                 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
 513                         ;
 514
 515                 if (data) {
 516                         esdhc_write32(&regs->sysctl,
 517                                       esdhc_read32(&regs->sysctl) |
 518                                       SYSCTL_RSTD);
 519                         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
 520                                 ;
 521                 }
 522
 523                 /* If this was CMD11, then notify that power cycle is needed */
 524                 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
 525                         printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
 526         }
 527
 528         esdhc_write32(&regs->irqstat, -1);
 529
 530         return err;
 531 }
 532
 533 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
 534 {
 535         struct fsl_esdhc *regs = priv->esdhc_regs;
 536         int div = 1;
 537 #ifdef ARCH_MXC
 538 #ifdef CONFIG_MX53
 539         /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
 540         int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
 541 #else
 542         int pre_div = 1;
 543 #endif
 544 #else
 545         int pre_div = 2;
 546 #endif
 547         int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
 548         int sdhc_clk = priv->sdhc_clk;
 549         uint clk;
 550
 551         if (clock < mmc->cfg->f_min)
 552                 clock = mmc->cfg->f_min;
 553
 554         while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
 555                 pre_div *= 2;
 556
 557         while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
 558                 div++;
 559
 560         pre_div >>= 1;
 561         div -= 1;
 562
 563         clk = (pre_div << 8) | (div << 4);
 564
 565 #ifdef CONFIG_FSL_USDHC
 566         esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
 567 #else
 568         esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
 569 #endif
 570
 571         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
 572
 573         udelay(10000);
 574
 575 #ifdef CONFIG_FSL_USDHC
 576         esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
 577 #else
 578         esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
 579 #endif
 580
 581 }
 582
 583 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 584 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
 585 {
 586         struct fsl_esdhc *regs = priv->esdhc_regs;
 587         u32 value;
 588         u32 time_out;
 589
 590         value = esdhc_read32(&regs->sysctl);
 591
 592         if (enable)
 593                 value |= SYSCTL_CKEN;
 594         else
 595                 value &= ~SYSCTL_CKEN;
 596
 597         esdhc_write32(&regs->sysctl, value);
 598
 599         time_out = 20;
 600         value = PRSSTAT_SDSTB;
 601         while (!(esdhc_read32(&regs->prsstat) & value)) {
 602                 if (time_out == 0) {
 603                         printf("fsl_esdhc: Internal clock never stabilised.\n");
 604                         break;
 605                 }
 606                 time_out--;
 607                 mdelay(1);
 608         }
 609 }
 610 #endif
 611
 612 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
 613 {
 614         struct fsl_esdhc *regs = priv->esdhc_regs;
 615
 616 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 617         /* Select to use peripheral clock */
 618         esdhc_clock_control(priv, false);
 619         esdhc_setbits32(&regs->scr, ESDHCCTL_PCS);
 620         esdhc_clock_control(priv, true);
 621 #endif
 622         /* Set the clock speed */
 623         set_sysctl(priv, mmc, mmc->clock);
 624
 625         /* Set the bus width */
 626         esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
 627
 628         if (mmc->bus_width == 4)
 629                 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
 630         else if (mmc->bus_width == 8)
 631                 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
 632
 633         return 0;
 634 }
 635
 636 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
 637 {
 638         struct fsl_esdhc *regs = priv->esdhc_regs;
 639         ulong start;
 640
 641         /* Reset the entire host controller */
 642         esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
 643
 644         /* Wait until the controller is available */
 645         start = get_timer(0);
 646         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
 647                 if (get_timer(start) > 1000)
 648                         return -ETIMEDOUT;
 649         }
 650
 651 #if defined(CONFIG_FSL_USDHC)
 652         /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
 653         esdhc_write32(&regs->mmcboot, 0x0);
 654         /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
 655         esdhc_write32(&regs->mixctrl, 0x0);
 656         esdhc_write32(&regs->clktunectrlstatus, 0x0);
 657
 658         /* Put VEND_SPEC to default value */
 659         if (priv->vs18_enable)
 660                 esdhc_write32(&regs->vendorspec, (VENDORSPEC_INIT |
 661                               ESDHC_VENDORSPEC_VSELECT));
 662         else
 663                 esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
 664
 665         /* Disable DLL_CTRL delay line */
 666         esdhc_write32(&regs->dllctrl, 0x0);
 667 #endif
 668
 669 #ifndef ARCH_MXC
 670         /* Enable cache snooping */
 671         esdhc_write32(&regs->scr, 0x00000040);
 672 #endif
 673
 674 #ifndef CONFIG_FSL_USDHC
 675         esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
 676 #else
 677         esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
 678 #endif
 679
 680         /* Set the initial clock speed */
 681         mmc_set_clock(mmc, 400000, false);
 682
 683         /* Disable the BRR and BWR bits in IRQSTAT */
 684         esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
 685
 686         /* Put the PROCTL reg back to the default */
 687         esdhc_write32(&regs->proctl, PROCTL_INIT);
 688
 689         /* Set timout to the maximum value */
 690         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
 691
 692         return 0;
 693 }
 694
 695 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
 696 {
 697         struct fsl_esdhc *regs = priv->esdhc_regs;
 698         int timeout = 1000;
 699
 700 #ifdef CONFIG_ESDHC_DETECT_QUIRK
 701         if (CONFIG_ESDHC_DETECT_QUIRK)
 702                 return 1;
 703 #endif
 704
 705 #if CONFIG_IS_ENABLED(DM_MMC)
 706         if (priv->non_removable)
 707                 return 1;
 708 #ifdef CONFIG_DM_GPIO
 709         if (dm_gpio_is_valid(&priv->cd_gpio))
 710                 return dm_gpio_get_value(&priv->cd_gpio);
 711 #endif
 712 #endif
 713
 714         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
 715                 udelay(1000);
 716
 717         return timeout > 0;
 718 }
 719
 720 static int esdhc_reset(struct fsl_esdhc *regs)
 721 {
 722         ulong start;
 723
 724         /* reset the controller */
 725         esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
 726
 727         /* hardware clears the bit when it is done */
 728         start = get_timer(0);
 729         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
 730                 if (get_timer(start) > 100) {
 731                         printf("MMC/SD: Reset never completed.\n");
 732                         return -ETIMEDOUT;
 733                 }
 734         }
 735
 736         return 0;
 737 }
 738
 739 #if !CONFIG_IS_ENABLED(DM_MMC)
 740 static int esdhc_getcd(struct mmc *mmc)
 741 {
 742         struct fsl_esdhc_priv *priv = mmc->priv;
 743
 744         return esdhc_getcd_common(priv);
 745 }
 746
 747 static int esdhc_init(struct mmc *mmc)
 748 {
 749         struct fsl_esdhc_priv *priv = mmc->priv;
 750
 751         return esdhc_init_common(priv, mmc);
 752 }
 753
 754 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 755                           struct mmc_data *data)
 756 {
 757         struct fsl_esdhc_priv *priv = mmc->priv;
 758
 759         return esdhc_send_cmd_common(priv, mmc, cmd, data);
 760 }
 761
 762 static int esdhc_set_ios(struct mmc *mmc)
 763 {
 764         struct fsl_esdhc_priv *priv = mmc->priv;
 765
 766         return esdhc_set_ios_common(priv, mmc);
 767 }
 768
 769 static const struct mmc_ops esdhc_ops = {
 770         .getcd          = esdhc_getcd,
 771         .init           = esdhc_init,
 772         .send_cmd       = esdhc_send_cmd,
 773         .set_ios        = esdhc_set_ios,
 774 };
 775 #endif
 776
 777 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
 778                           struct fsl_esdhc_plat *plat)
 779 {
 780         struct mmc_config *cfg;
 781         struct fsl_esdhc *regs;
 782         u32 caps, voltage_caps;
 783         int ret;
 784
 785         if (!priv)
 786                 return -EINVAL;
 787
 788         regs = priv->esdhc_regs;
 789
 790         /* First reset the eSDHC controller */
 791         ret = esdhc_reset(regs);
 792         if (ret)
 793                 return ret;
 794
 795 #ifndef CONFIG_FSL_USDHC
 796         esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
 797                                 | SYSCTL_IPGEN | SYSCTL_CKEN);
 798 #else
 799         esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
 800                         VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
 801 #endif
 802
 803         if (priv->vs18_enable)
 804                 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
 805
 806         writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
 807         cfg = &plat->cfg;
 808 #ifndef CONFIG_DM_MMC
 809         memset(cfg, '\0', sizeof(*cfg));
 810 #endif
 811
 812         voltage_caps = 0;
 813         caps = esdhc_read32(&regs->hostcapblt);
 814
 815 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
 816         caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
 817                         ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
 818 #endif
 819
 820 /* T4240 host controller capabilities register should have VS33 bit */
 821 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 822         caps = caps | ESDHC_HOSTCAPBLT_VS33;
 823 #endif
 824
 825         if (caps & ESDHC_HOSTCAPBLT_VS18)
 826                 voltage_caps |= MMC_VDD_165_195;
 827         if (caps & ESDHC_HOSTCAPBLT_VS30)
 828                 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
 829         if (caps & ESDHC_HOSTCAPBLT_VS33)
 830                 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
 831
 832         cfg->name = "FSL_SDHC";
 833 #if !CONFIG_IS_ENABLED(DM_MMC)
 834         cfg->ops = &esdhc_ops;
 835 #endif
 836 #ifdef CONFIG_SYS_SD_VOLTAGE
 837         cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
 838 #else
 839         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 840 #endif
 841         if ((cfg->voltages & voltage_caps) == 0) {
 842                 printf("voltage not supported by controller\n");
 843                 return -1;
 844         }
 845
 846         if (priv->bus_width == 8)
 847                 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
 848         else if (priv->bus_width == 4)
 849                 cfg->host_caps = MMC_MODE_4BIT;
 850
 851         cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
 852 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
 853         cfg->host_caps |= MMC_MODE_DDR_52MHz;
 854 #endif
 855
 856         if (priv->bus_width > 0) {
 857                 if (priv->bus_width < 8)
 858                         cfg->host_caps &= ~MMC_MODE_8BIT;
 859                 if (priv->bus_width < 4)
 860                         cfg->host_caps &= ~MMC_MODE_4BIT;
 861         }
 862
 863         if (caps & ESDHC_HOSTCAPBLT_HSS)
 864                 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 865
 866 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
 867         if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
 868                 cfg->host_caps &= ~MMC_MODE_8BIT;
 869 #endif
 870
 871         cfg->f_min = 400000;
 872         cfg->f_max = min(priv->sdhc_clk, (u32)52000000);
 873
 874         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 875
 876         return 0;
 877 }
 878
 879 #if !CONFIG_IS_ENABLED(DM_MMC)
 880 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
 881                                  struct fsl_esdhc_priv *priv)
 882 {
 883         if (!cfg || !priv)
 884                 return -EINVAL;
 885
 886         priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
 887         priv->bus_width = cfg->max_bus_width;
 888         priv->sdhc_clk = cfg->sdhc_clk;
 889         priv->wp_enable  = cfg->wp_enable;
 890         priv->vs18_enable  = cfg->vs18_enable;
 891
 892         return 0;
 893 };
 894
 895 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 896 {
 897         struct fsl_esdhc_plat *plat;
 898         struct fsl_esdhc_priv *priv;
 899         struct mmc *mmc;
 900         int ret;
 901
 902         if (!cfg)
 903                 return -EINVAL;
 904
 905         priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
 906         if (!priv)
 907                 return -ENOMEM;
 908         plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
 909         if (!plat) {
 910                 free(priv);
 911                 return -ENOMEM;
 912         }
 913
 914         ret = fsl_esdhc_cfg_to_priv(cfg, priv);
 915         if (ret) {
 916                 debug("%s xlate failure\n", __func__);
 917                 free(plat);
 918                 free(priv);
 919                 return ret;
 920         }
 921
 922         ret = fsl_esdhc_init(priv, plat);
 923         if (ret) {
 924                 debug("%s init failure\n", __func__);
 925                 free(plat);
 926                 free(priv);
 927                 return ret;
 928         }
 929
 930         mmc = mmc_create(&plat->cfg, priv);
 931         if (!mmc)
 932                 return -EIO;
 933
 934         priv->mmc = mmc;
 935
 936         return 0;
 937 }
 938
 939 int fsl_esdhc_mmc_init(bd_t *bis)
 940 {
 941         struct fsl_esdhc_cfg *cfg;
 942
 943         cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
 944         cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
 945         cfg->sdhc_clk = gd->arch.sdhc_clk;
 946         return fsl_esdhc_initialize(bis, cfg);
 947 }
 948 #endif
 949
 950 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
 951 void mmc_adapter_card_type_ident(void)
 952 {
 953         u8 card_id;
 954         u8 value;
 955
 956         card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
 957         gd->arch.sdhc_adapter = card_id;
 958
 959         switch (card_id) {
 960         case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
 961                 value = QIXIS_READ(brdcfg[5]);
 962                 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
 963                 QIXIS_WRITE(brdcfg[5], value);
 964                 break;
 965         case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
 966                 value = QIXIS_READ(pwr_ctl[1]);
 967                 value |= QIXIS_EVDD_BY_SDHC_VS;
 968                 QIXIS_WRITE(pwr_ctl[1], value);
 969                 break;
 970         case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
 971                 value = QIXIS_READ(brdcfg[5]);
 972                 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
 973                 QIXIS_WRITE(brdcfg[5], value);
 974                 break;
 975         case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
 976                 break;
 977         case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
 978                 break;
 979         case QIXIS_ESDHC_ADAPTER_TYPE_SD:
 980                 break;
 981         case QIXIS_ESDHC_NO_ADAPTER:
 982                 break;
 983         default:
 984                 break;
 985         }
 986 }
 987 #endif
 988
 989 #ifdef CONFIG_OF_LIBFDT
 990 __weak int esdhc_status_fixup(void *blob, const char *compat)
 991 {
 992 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
 993         if (!hwconfig("esdhc")) {
 994                 do_fixup_by_compat(blob, compat, "status", "disabled",
 995                                 sizeof("disabled"), 1);
 996                 return 1;
 997         }
 998 #endif
 999         return 0;
1000 }
1001
1002 void fdt_fixup_esdhc(void *blob, bd_t *bd)
1003 {
1004         const char *compat = "fsl,esdhc";
1005
1006         if (esdhc_status_fixup(blob, compat))
1007                 return;
1008
1009 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
1010         do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
1011                                gd->arch.sdhc_clk, 1);
1012 #else
1013         do_fixup_by_compat_u32(blob, compat, "clock-frequency",
1014                                gd->arch.sdhc_clk, 1);
1015 #endif
1016 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1017         do_fixup_by_compat_u32(blob, compat, "adapter-type",
1018                                (u32)(gd->arch.sdhc_adapter), 1);
1019 #endif
1020 }
1021 #endif
1022
1023 #if CONFIG_IS_ENABLED(DM_MMC)
1024 #include <asm/arch/clock.h>
1025 __weak void init_clk_usdhc(u32 index)
1026 {
1027 }
1028
1029 static int fsl_esdhc_probe(struct udevice *dev)
1030 {
1031         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1032         struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1033         struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1034 #ifdef CONFIG_DM_REGULATOR
1035         struct udevice *vqmmc_dev;
1036 #endif
1037         fdt_addr_t addr;
1038         unsigned int val;
1039         struct mmc *mmc;
1040         int ret;
1041
1042         addr = dev_read_addr(dev);
1043         if (addr == FDT_ADDR_T_NONE)
1044                 return -EINVAL;
1045
1046         priv->esdhc_regs = (struct fsl_esdhc *)addr;
1047         priv->dev = dev;
1048
1049         val = dev_read_u32_default(dev, "bus-width", -1);
1050         if (val == 8)
1051                 priv->bus_width = 8;
1052         else if (val == 4)
1053                 priv->bus_width = 4;
1054         else
1055                 priv->bus_width = 1;
1056
1057         if (dev_read_bool(dev, "non-removable")) {
1058                 priv->non_removable = 1;
1059          } else {
1060                 priv->non_removable = 0;
1061 #ifdef CONFIG_DM_GPIO
1062                 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1063                                      GPIOD_IS_IN);
1064 #endif
1065         }
1066
1067         priv->wp_enable = 1;
1068
1069 #ifdef CONFIG_DM_GPIO
1070         ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1071                                    GPIOD_IS_IN);
1072         if (ret)
1073                 priv->wp_enable = 0;
1074 #endif
1075
1076         priv->vs18_enable = 0;
1077
1078 #ifdef CONFIG_DM_REGULATOR
1079         /*
1080          * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1081          * otherwise, emmc will work abnormally.
1082          */
1083         ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1084         if (ret) {
1085                 dev_dbg(dev, "no vqmmc-supply\n");
1086         } else {
1087                 ret = regulator_set_enable(vqmmc_dev, true);
1088                 if (ret) {
1089                         dev_err(dev, "fail to enable vqmmc-supply\n");
1090                         return ret;
1091                 }
1092
1093                 if (regulator_get_value(vqmmc_dev) == 1800000)
1094                         priv->vs18_enable = 1;
1095         }
1096 #endif
1097
1098         /*
1099          * TODO:
1100          * Because lack of clk driver, if SDHC clk is not enabled,
1101          * need to enable it first before this driver is invoked.
1102          *
1103          * we use MXC_ESDHC_CLK to get clk freq.
1104          * If one would like to make this function work,
1105          * the aliases should be provided in dts as this:
1106          *
1107          *  aliases {
1108          *      mmc0 = &usdhc1;
1109          *      mmc1 = &usdhc2;
1110          *      mmc2 = &usdhc3;
1111          *      mmc3 = &usdhc4;
1112          *      };
1113          * Then if your board only supports mmc2 and mmc3, but we can
1114          * correctly get the seq as 2 and 3, then let mxc_get_clock
1115          * work as expected.
1116          */
1117
1118         init_clk_usdhc(dev->seq);
1119
1120         priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1121         if (priv->sdhc_clk <= 0) {
1122                 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1123                 return -EINVAL;
1124         }
1125
1126         ret = fsl_esdhc_init(priv, plat);
1127         if (ret) {
1128                 dev_err(dev, "fsl_esdhc_init failure\n");
1129                 return ret;
1130         }
1131
1132         mmc = &plat->mmc;
1133         mmc->cfg = &plat->cfg;
1134         mmc->dev = dev;
1135         upriv->mmc = mmc;
1136
1137         return esdhc_init_common(priv, mmc);
1138 }
1139
1140 #if CONFIG_IS_ENABLED(DM_MMC)
1141 static int fsl_esdhc_get_cd(struct udevice *dev)
1142 {
1143         struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1144
1145         return true;
1146         return esdhc_getcd_common(priv);
1147 }
1148
1149 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1150                               struct mmc_data *data)
1151 {
1152         struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1153         struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1154
1155         return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1156 }
1157
1158 static int fsl_esdhc_set_ios(struct udevice *dev)
1159 {
1160         struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1161         struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1162
1163         return esdhc_set_ios_common(priv, &plat->mmc);
1164 }
1165
1166 static const struct dm_mmc_ops fsl_esdhc_ops = {
1167         .get_cd         = fsl_esdhc_get_cd,
1168         .send_cmd       = fsl_esdhc_send_cmd,
1169         .set_ios        = fsl_esdhc_set_ios,
1170 };
1171 #endif
1172
1173 static const struct udevice_id fsl_esdhc_ids[] = {
1174         { .compatible = "fsl,imx6ul-usdhc", },
1175         { .compatible = "fsl,imx6sx-usdhc", },
1176         { .compatible = "fsl,imx6sl-usdhc", },
1177         { .compatible = "fsl,imx6q-usdhc", },
1178         { .compatible = "fsl,imx7d-usdhc", },
1179         { .compatible = "fsl,imx7ulp-usdhc", },
1180         { .compatible = "fsl,esdhc", },
1181         { /* sentinel */ }
1182 };
1183
1184 #if CONFIG_IS_ENABLED(BLK)
1185 static int fsl_esdhc_bind(struct udevice *dev)
1186 {
1187         struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1188
1189         return mmc_bind(dev, &plat->mmc, &plat->cfg);
1190 }
1191 #endif
1192
1193 U_BOOT_DRIVER(fsl_esdhc) = {
1194         .name   = "fsl-esdhc-mmc",
1195         .id     = UCLASS_MMC,
1196         .of_match = fsl_esdhc_ids,
1197         .ops    = &fsl_esdhc_ops,
1198 #if CONFIG_IS_ENABLED(BLK)
1199         .bind   = fsl_esdhc_bind,
1200 #endif
1201         .probe  = fsl_esdhc_probe,
1202         .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
1203         .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
1204 };
1205 #endif