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Merge git://git.denx.de/u-boot-mmc
[people/ms/u-boot.git] / drivers / mmc / fsl_esdhc.c
1 /*
2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based vaguely on the pxa mmc code:
6 * (C) Copyright 2003
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12 #include <config.h>
13 #include <common.h>
14 #include <command.h>
15 #include <errno.h>
16 #include <hwconfig.h>
17 #include <mmc.h>
18 #include <part.h>
19 #include <power/regulator.h>
20 #include <malloc.h>
21 #include <fsl_esdhc.h>
22 #include <fdt_support.h>
23 #include <asm/io.h>
24 #include <dm.h>
25 #include <asm-generic/gpio.h>
26 #include <dm/pinctrl.h>
27
28 DECLARE_GLOBAL_DATA_PTR;
29
30 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
31 IRQSTATEN_CINT | \
32 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
33 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
34 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
35 IRQSTATEN_DINT)
36 #define MAX_TUNING_LOOP 40
37
38 struct fsl_esdhc {
39 uint dsaddr; /* SDMA system address register */
40 uint blkattr; /* Block attributes register */
41 uint cmdarg; /* Command argument register */
42 uint xfertyp; /* Transfer type register */
43 uint cmdrsp0; /* Command response 0 register */
44 uint cmdrsp1; /* Command response 1 register */
45 uint cmdrsp2; /* Command response 2 register */
46 uint cmdrsp3; /* Command response 3 register */
47 uint datport; /* Buffer data port register */
48 uint prsstat; /* Present state register */
49 uint proctl; /* Protocol control register */
50 uint sysctl; /* System Control Register */
51 uint irqstat; /* Interrupt status register */
52 uint irqstaten; /* Interrupt status enable register */
53 uint irqsigen; /* Interrupt signal enable register */
54 uint autoc12err; /* Auto CMD error status register */
55 uint hostcapblt; /* Host controller capabilities register */
56 uint wml; /* Watermark level register */
57 uint mixctrl; /* For USDHC */
58 char reserved1[4]; /* reserved */
59 uint fevt; /* Force event register */
60 uint admaes; /* ADMA error status register */
61 uint adsaddr; /* ADMA system address register */
62 char reserved2[4];
63 uint dllctrl;
64 uint dllstat;
65 uint clktunectrlstatus;
66 char reserved3[4];
67 uint strobe_dllctrl;
68 uint strobe_dllstat;
69 char reserved4[72];
70 uint vendorspec;
71 uint mmcboot;
72 uint vendorspec2;
73 uint tuning_ctrl; /* on i.MX6/7/8 */
74 char reserved5[44];
75 uint hostver; /* Host controller version register */
76 char reserved6[4]; /* reserved */
77 uint dmaerraddr; /* DMA error address register */
78 char reserved7[4]; /* reserved */
79 uint dmaerrattr; /* DMA error attribute register */
80 char reserved8[4]; /* reserved */
81 uint hostcapblt2; /* Host controller capabilities register 2 */
82 char reserved9[8]; /* reserved */
83 uint tcr; /* Tuning control register */
84 char reserved10[28]; /* reserved */
85 uint sddirctl; /* SD direction control register */
86 char reserved11[712];/* reserved */
87 uint scr; /* eSDHC control register */
88 };
89
90 struct fsl_esdhc_plat {
91 struct mmc_config cfg;
92 struct mmc mmc;
93 };
94
95 struct esdhc_soc_data {
96 u32 flags;
97 u32 caps;
98 };
99
100 /**
101 * struct fsl_esdhc_priv
102 *
103 * @esdhc_regs: registers of the sdhc controller
104 * @sdhc_clk: Current clk of the sdhc controller
105 * @bus_width: bus width, 1bit, 4bit or 8bit
106 * @cfg: mmc config
107 * @mmc: mmc
108 * Following is used when Driver Model is enabled for MMC
109 * @dev: pointer for the device
110 * @non_removable: 0: removable; 1: non-removable
111 * @wp_enable: 1: enable checking wp; 0: no check
112 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
113 * @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h
114 * @caps: controller capabilities
115 * @tuning_step: tuning step setting in tuning_ctrl register
116 * @start_tuning_tap: the start point for tuning in tuning_ctrl register
117 * @strobe_dll_delay_target: settings in strobe_dllctrl
118 * @signal_voltage: indicating the current voltage
119 * @cd_gpio: gpio for card detection
120 * @wp_gpio: gpio for write protection
121 */
122 struct fsl_esdhc_priv {
123 struct fsl_esdhc *esdhc_regs;
124 unsigned int sdhc_clk;
125 unsigned int clock;
126 unsigned int mode;
127 unsigned int bus_width;
128 #if !CONFIG_IS_ENABLED(BLK)
129 struct mmc *mmc;
130 #endif
131 struct udevice *dev;
132 int non_removable;
133 int wp_enable;
134 int vs18_enable;
135 u32 flags;
136 u32 caps;
137 u32 tuning_step;
138 u32 tuning_start_tap;
139 u32 strobe_dll_delay_target;
140 u32 signal_voltage;
141 #if IS_ENABLED(CONFIG_DM_REGULATOR)
142 struct udevice *vqmmc_dev;
143 struct udevice *vmmc_dev;
144 #endif
145 #ifdef CONFIG_DM_GPIO
146 struct gpio_desc cd_gpio;
147 struct gpio_desc wp_gpio;
148 #endif
149 };
150
151 /* Return the XFERTYP flags for a given command and data packet */
152 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
153 {
154 uint xfertyp = 0;
155
156 if (data) {
157 xfertyp |= XFERTYP_DPSEL;
158 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
159 xfertyp |= XFERTYP_DMAEN;
160 #endif
161 if (data->blocks > 1) {
162 xfertyp |= XFERTYP_MSBSEL;
163 xfertyp |= XFERTYP_BCEN;
164 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
165 xfertyp |= XFERTYP_AC12EN;
166 #endif
167 }
168
169 if (data->flags & MMC_DATA_READ)
170 xfertyp |= XFERTYP_DTDSEL;
171 }
172
173 if (cmd->resp_type & MMC_RSP_CRC)
174 xfertyp |= XFERTYP_CCCEN;
175 if (cmd->resp_type & MMC_RSP_OPCODE)
176 xfertyp |= XFERTYP_CICEN;
177 if (cmd->resp_type & MMC_RSP_136)
178 xfertyp |= XFERTYP_RSPTYP_136;
179 else if (cmd->resp_type & MMC_RSP_BUSY)
180 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
181 else if (cmd->resp_type & MMC_RSP_PRESENT)
182 xfertyp |= XFERTYP_RSPTYP_48;
183
184 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
185 xfertyp |= XFERTYP_CMDTYP_ABORT;
186
187 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
188 }
189
190 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
191 /*
192 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
193 */
194 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
195 struct mmc_data *data)
196 {
197 struct fsl_esdhc *regs = priv->esdhc_regs;
198 uint blocks;
199 char *buffer;
200 uint databuf;
201 uint size;
202 uint irqstat;
203 ulong start;
204
205 if (data->flags & MMC_DATA_READ) {
206 blocks = data->blocks;
207 buffer = data->dest;
208 while (blocks) {
209 start = get_timer(0);
210 size = data->blocksize;
211 irqstat = esdhc_read32(&regs->irqstat);
212 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {
213 if (get_timer(start) > PIO_TIMEOUT) {
214 printf("\nData Read Failed in PIO Mode.");
215 return;
216 }
217 }
218 while (size && (!(irqstat & IRQSTAT_TC))) {
219 udelay(100); /* Wait before last byte transfer complete */
220 irqstat = esdhc_read32(&regs->irqstat);
221 databuf = in_le32(&regs->datport);
222 *((uint *)buffer) = databuf;
223 buffer += 4;
224 size -= 4;
225 }
226 blocks--;
227 }
228 } else {
229 blocks = data->blocks;
230 buffer = (char *)data->src;
231 while (blocks) {
232 start = get_timer(0);
233 size = data->blocksize;
234 irqstat = esdhc_read32(&regs->irqstat);
235 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {
236 if (get_timer(start) > PIO_TIMEOUT) {
237 printf("\nData Write Failed in PIO Mode.");
238 return;
239 }
240 }
241 while (size && (!(irqstat & IRQSTAT_TC))) {
242 udelay(100); /* Wait before last byte transfer complete */
243 databuf = *((uint *)buffer);
244 buffer += 4;
245 size -= 4;
246 irqstat = esdhc_read32(&regs->irqstat);
247 out_le32(&regs->datport, databuf);
248 }
249 blocks--;
250 }
251 }
252 }
253 #endif
254
255 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
256 struct mmc_data *data)
257 {
258 int timeout;
259 struct fsl_esdhc *regs = priv->esdhc_regs;
260 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
261 defined(CONFIG_MX8M)
262 dma_addr_t addr;
263 #endif
264 uint wml_value;
265
266 wml_value = data->blocksize/4;
267
268 if (data->flags & MMC_DATA_READ) {
269 if (wml_value > WML_RD_WML_MAX)
270 wml_value = WML_RD_WML_MAX_VAL;
271
272 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
273 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
274 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
275 defined(CONFIG_MX8M)
276 addr = virt_to_phys((void *)(data->dest));
277 if (upper_32_bits(addr))
278 printf("Error found for upper 32 bits\n");
279 else
280 esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
281 #else
282 esdhc_write32(&regs->dsaddr, (u32)data->dest);
283 #endif
284 #endif
285 } else {
286 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
287 flush_dcache_range((ulong)data->src,
288 (ulong)data->src+data->blocks
289 *data->blocksize);
290 #endif
291 if (wml_value > WML_WR_WML_MAX)
292 wml_value = WML_WR_WML_MAX_VAL;
293 if (priv->wp_enable) {
294 if ((esdhc_read32(&regs->prsstat) &
295 PRSSTAT_WPSPL) == 0) {
296 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
297 return -ETIMEDOUT;
298 }
299 }
300
301 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
302 wml_value << 16);
303 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
304 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
305 defined(CONFIG_MX8M)
306 addr = virt_to_phys((void *)(data->src));
307 if (upper_32_bits(addr))
308 printf("Error found for upper 32 bits\n");
309 else
310 esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
311 #else
312 esdhc_write32(&regs->dsaddr, (u32)data->src);
313 #endif
314 #endif
315 }
316
317 esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
318
319 /* Calculate the timeout period for data transactions */
320 /*
321 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
322 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
323 * So, Number of SD Clock cycles for 0.25sec should be minimum
324 * (SD Clock/sec * 0.25 sec) SD Clock cycles
325 * = (mmc->clock * 1/4) SD Clock cycles
326 * As 1) >= 2)
327 * => (2^(timeout+13)) >= mmc->clock * 1/4
328 * Taking log2 both the sides
329 * => timeout + 13 >= log2(mmc->clock/4)
330 * Rounding up to next power of 2
331 * => timeout + 13 = log2(mmc->clock/4) + 1
332 * => timeout + 13 = fls(mmc->clock/4)
333 *
334 * However, the MMC spec "It is strongly recommended for hosts to
335 * implement more than 500ms timeout value even if the card
336 * indicates the 250ms maximum busy length." Even the previous
337 * value of 300ms is known to be insufficient for some cards.
338 * So, we use
339 * => timeout + 13 = fls(mmc->clock/2)
340 */
341 timeout = fls(mmc->clock/2);
342 timeout -= 13;
343
344 if (timeout > 14)
345 timeout = 14;
346
347 if (timeout < 0)
348 timeout = 0;
349
350 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
351 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
352 timeout++;
353 #endif
354
355 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
356 timeout = 0xE;
357 #endif
358 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
359
360 return 0;
361 }
362
363 static void check_and_invalidate_dcache_range
364 (struct mmc_cmd *cmd,
365 struct mmc_data *data) {
366 unsigned start = 0;
367 unsigned end = 0;
368 unsigned size = roundup(ARCH_DMA_MINALIGN,
369 data->blocks*data->blocksize);
370 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
371 defined(CONFIG_MX8M)
372 dma_addr_t addr;
373
374 addr = virt_to_phys((void *)(data->dest));
375 if (upper_32_bits(addr))
376 printf("Error found for upper 32 bits\n");
377 else
378 start = lower_32_bits(addr);
379 #else
380 start = (unsigned)data->dest;
381 #endif
382 end = start + size;
383 invalidate_dcache_range(start, end);
384 }
385
386 /*
387 * Sends a command out on the bus. Takes the mmc pointer,
388 * a command pointer, and an optional data pointer.
389 */
390 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
391 struct mmc_cmd *cmd, struct mmc_data *data)
392 {
393 int err = 0;
394 uint xfertyp;
395 uint irqstat;
396 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
397 struct fsl_esdhc *regs = priv->esdhc_regs;
398
399 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
400 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
401 return 0;
402 #endif
403
404 esdhc_write32(&regs->irqstat, -1);
405
406 sync();
407
408 /* Wait for the bus to be idle */
409 while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
410 (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
411 ;
412
413 while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
414 ;
415
416 /* Wait at least 8 SD clock cycles before the next command */
417 /*
418 * Note: This is way more than 8 cycles, but 1ms seems to
419 * resolve timing issues with some cards
420 */
421 udelay(1000);
422
423 /* Set up for a data transfer if we have one */
424 if (data) {
425 err = esdhc_setup_data(priv, mmc, data);
426 if(err)
427 return err;
428
429 if (data->flags & MMC_DATA_READ)
430 check_and_invalidate_dcache_range(cmd, data);
431 }
432
433 /* Figure out the transfer arguments */
434 xfertyp = esdhc_xfertyp(cmd, data);
435
436 /* Mask all irqs */
437 esdhc_write32(&regs->irqsigen, 0);
438
439 /* Send the command */
440 esdhc_write32(&regs->cmdarg, cmd->cmdarg);
441 #if defined(CONFIG_FSL_USDHC)
442 esdhc_write32(&regs->mixctrl,
443 (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
444 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
445 esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
446 #else
447 esdhc_write32(&regs->xfertyp, xfertyp);
448 #endif
449
450 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
451 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
452 flags = IRQSTAT_BRR;
453
454 /* Wait for the command to complete */
455 while (!(esdhc_read32(&regs->irqstat) & flags))
456 ;
457
458 irqstat = esdhc_read32(&regs->irqstat);
459
460 if (irqstat & CMD_ERR) {
461 err = -ECOMM;
462 goto out;
463 }
464
465 if (irqstat & IRQSTAT_CTOE) {
466 err = -ETIMEDOUT;
467 goto out;
468 }
469
470 /* Switch voltage to 1.8V if CMD11 succeeded */
471 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
472 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
473
474 printf("Run CMD11 1.8V switch\n");
475 /* Sleep for 5 ms - max time for card to switch to 1.8V */
476 udelay(5000);
477 }
478
479 /* Workaround for ESDHC errata ENGcm03648 */
480 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
481 int timeout = 6000;
482
483 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
484 while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
485 PRSSTAT_DAT0)) {
486 udelay(100);
487 timeout--;
488 }
489
490 if (timeout <= 0) {
491 printf("Timeout waiting for DAT0 to go high!\n");
492 err = -ETIMEDOUT;
493 goto out;
494 }
495 }
496
497 /* Copy the response to the response buffer */
498 if (cmd->resp_type & MMC_RSP_136) {
499 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
500
501 cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
502 cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
503 cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
504 cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
505 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
506 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
507 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
508 cmd->response[3] = (cmdrsp0 << 8);
509 } else
510 cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
511
512 /* Wait until all of the blocks are transferred */
513 if (data) {
514 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
515 esdhc_pio_read_write(priv, data);
516 #else
517 flags = DATA_COMPLETE;
518 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
519 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
520 flags = IRQSTAT_BRR;
521 }
522
523 do {
524 irqstat = esdhc_read32(&regs->irqstat);
525
526 if (irqstat & IRQSTAT_DTOE) {
527 err = -ETIMEDOUT;
528 goto out;
529 }
530
531 if (irqstat & DATA_ERR) {
532 err = -ECOMM;
533 goto out;
534 }
535 } while ((irqstat & flags) != flags);
536
537 /*
538 * Need invalidate the dcache here again to avoid any
539 * cache-fill during the DMA operations such as the
540 * speculative pre-fetching etc.
541 */
542 if (data->flags & MMC_DATA_READ)
543 check_and_invalidate_dcache_range(cmd, data);
544 #endif
545 }
546
547 out:
548 /* Reset CMD and DATA portions on error */
549 if (err) {
550 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
551 SYSCTL_RSTC);
552 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
553 ;
554
555 if (data) {
556 esdhc_write32(&regs->sysctl,
557 esdhc_read32(&regs->sysctl) |
558 SYSCTL_RSTD);
559 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
560 ;
561 }
562
563 /* If this was CMD11, then notify that power cycle is needed */
564 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
565 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
566 }
567
568 esdhc_write32(&regs->irqstat, -1);
569
570 return err;
571 }
572
573 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
574 {
575 struct fsl_esdhc *regs = priv->esdhc_regs;
576 int div = 1;
577 #ifdef ARCH_MXC
578 #ifdef CONFIG_MX53
579 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
580 int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
581 #else
582 int pre_div = 1;
583 #endif
584 #else
585 int pre_div = 2;
586 #endif
587 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
588 int sdhc_clk = priv->sdhc_clk;
589 uint clk;
590
591 if (clock < mmc->cfg->f_min)
592 clock = mmc->cfg->f_min;
593
594 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
595 pre_div *= 2;
596
597 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
598 div++;
599
600 pre_div >>= 1;
601 div -= 1;
602
603 clk = (pre_div << 8) | (div << 4);
604
605 #ifdef CONFIG_FSL_USDHC
606 esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
607 #else
608 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
609 #endif
610
611 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
612
613 udelay(10000);
614
615 #ifdef CONFIG_FSL_USDHC
616 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
617 #else
618 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
619 #endif
620
621 priv->clock = clock;
622 }
623
624 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
625 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
626 {
627 struct fsl_esdhc *regs = priv->esdhc_regs;
628 u32 value;
629 u32 time_out;
630
631 value = esdhc_read32(&regs->sysctl);
632
633 if (enable)
634 value |= SYSCTL_CKEN;
635 else
636 value &= ~SYSCTL_CKEN;
637
638 esdhc_write32(&regs->sysctl, value);
639
640 time_out = 20;
641 value = PRSSTAT_SDSTB;
642 while (!(esdhc_read32(&regs->prsstat) & value)) {
643 if (time_out == 0) {
644 printf("fsl_esdhc: Internal clock never stabilised.\n");
645 break;
646 }
647 time_out--;
648 mdelay(1);
649 }
650 }
651 #endif
652
653 #ifdef MMC_SUPPORTS_TUNING
654 static int esdhc_change_pinstate(struct udevice *dev)
655 {
656 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
657 int ret;
658
659 switch (priv->mode) {
660 case UHS_SDR50:
661 case UHS_DDR50:
662 ret = pinctrl_select_state(dev, "state_100mhz");
663 break;
664 case UHS_SDR104:
665 case MMC_HS_200:
666 ret = pinctrl_select_state(dev, "state_200mhz");
667 break;
668 default:
669 ret = pinctrl_select_state(dev, "default");
670 break;
671 }
672
673 if (ret)
674 printf("%s %d error\n", __func__, priv->mode);
675
676 return ret;
677 }
678
679 static void esdhc_reset_tuning(struct mmc *mmc)
680 {
681 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
682 struct fsl_esdhc *regs = priv->esdhc_regs;
683
684 if (priv->flags & ESDHC_FLAG_USDHC) {
685 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
686 esdhc_clrbits32(&regs->autoc12err,
687 MIX_CTRL_SMPCLK_SEL |
688 MIX_CTRL_EXE_TUNE);
689 }
690 }
691 }
692
693 static int esdhc_set_timing(struct mmc *mmc)
694 {
695 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
696 struct fsl_esdhc *regs = priv->esdhc_regs;
697 u32 mixctrl;
698
699 mixctrl = readl(&regs->mixctrl);
700 mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
701
702 switch (mmc->selected_mode) {
703 case MMC_LEGACY:
704 case SD_LEGACY:
705 esdhc_reset_tuning(mmc);
706 break;
707 case MMC_HS:
708 case MMC_HS_52:
709 case MMC_HS_200:
710 case SD_HS:
711 case UHS_SDR12:
712 case UHS_SDR25:
713 case UHS_SDR50:
714 case UHS_SDR104:
715 writel(mixctrl, &regs->mixctrl);
716 break;
717 case UHS_DDR50:
718 case MMC_DDR_52:
719 mixctrl |= MIX_CTRL_DDREN;
720 writel(mixctrl, &regs->mixctrl);
721 break;
722 default:
723 printf("Not supported %d\n", mmc->selected_mode);
724 return -EINVAL;
725 }
726
727 priv->mode = mmc->selected_mode;
728
729 return esdhc_change_pinstate(mmc->dev);
730 }
731
732 static int esdhc_set_voltage(struct mmc *mmc)
733 {
734 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
735 struct fsl_esdhc *regs = priv->esdhc_regs;
736 int ret;
737
738 priv->signal_voltage = mmc->signal_voltage;
739 switch (mmc->signal_voltage) {
740 case MMC_SIGNAL_VOLTAGE_330:
741 if (priv->vs18_enable)
742 return -EIO;
743 #ifdef CONFIG_DM_REGULATOR
744 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
745 ret = regulator_set_value(priv->vqmmc_dev, 3300000);
746 if (ret) {
747 printf("Setting to 3.3V error");
748 return -EIO;
749 }
750 /* Wait for 5ms */
751 mdelay(5);
752 }
753 #endif
754
755 esdhc_clrbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
756 if (!(esdhc_read32(&regs->vendorspec) &
757 ESDHC_VENDORSPEC_VSELECT))
758 return 0;
759
760 return -EAGAIN;
761 case MMC_SIGNAL_VOLTAGE_180:
762 #ifdef CONFIG_DM_REGULATOR
763 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
764 ret = regulator_set_value(priv->vqmmc_dev, 1800000);
765 if (ret) {
766 printf("Setting to 1.8V error");
767 return -EIO;
768 }
769 }
770 #endif
771 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
772 if (esdhc_read32(&regs->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
773 return 0;
774
775 return -EAGAIN;
776 case MMC_SIGNAL_VOLTAGE_120:
777 return -ENOTSUPP;
778 default:
779 return 0;
780 }
781 }
782
783 static void esdhc_stop_tuning(struct mmc *mmc)
784 {
785 struct mmc_cmd cmd;
786
787 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
788 cmd.cmdarg = 0;
789 cmd.resp_type = MMC_RSP_R1b;
790
791 dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
792 }
793
794 static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
795 {
796 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
797 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
798 struct fsl_esdhc *regs = priv->esdhc_regs;
799 struct mmc *mmc = &plat->mmc;
800 u32 irqstaten = readl(&regs->irqstaten);
801 u32 irqsigen = readl(&regs->irqsigen);
802 int i, ret = -ETIMEDOUT;
803 u32 val, mixctrl;
804
805 /* clock tuning is not needed for upto 52MHz */
806 if (mmc->clock <= 52000000)
807 return 0;
808
809 /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
810 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
811 val = readl(&regs->autoc12err);
812 mixctrl = readl(&regs->mixctrl);
813 val &= ~MIX_CTRL_SMPCLK_SEL;
814 mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
815
816 val |= MIX_CTRL_EXE_TUNE;
817 mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
818
819 writel(val, &regs->autoc12err);
820 writel(mixctrl, &regs->mixctrl);
821 }
822
823 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
824 mixctrl = readl(&regs->mixctrl);
825 mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
826 writel(mixctrl, &regs->mixctrl);
827
828 writel(IRQSTATEN_BRR, &regs->irqstaten);
829 writel(IRQSTATEN_BRR, &regs->irqsigen);
830
831 /*
832 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
833 * of loops reaches 40 times.
834 */
835 for (i = 0; i < MAX_TUNING_LOOP; i++) {
836 u32 ctrl;
837
838 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
839 if (mmc->bus_width == 8)
840 writel(0x7080, &regs->blkattr);
841 else if (mmc->bus_width == 4)
842 writel(0x7040, &regs->blkattr);
843 } else {
844 writel(0x7040, &regs->blkattr);
845 }
846
847 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
848 val = readl(&regs->mixctrl);
849 val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
850 writel(val, &regs->mixctrl);
851
852 /* We are using STD tuning, no need to check return value */
853 mmc_send_tuning(mmc, opcode, NULL);
854
855 ctrl = readl(&regs->autoc12err);
856 if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
857 (ctrl & MIX_CTRL_SMPCLK_SEL)) {
858 /*
859 * need to wait some time, make sure sd/mmc fininsh
860 * send out tuning data, otherwise, the sd/mmc can't
861 * response to any command when the card still out
862 * put the tuning data.
863 */
864 mdelay(1);
865 ret = 0;
866 break;
867 }
868
869 /* Add 1ms delay for SD and eMMC */
870 mdelay(1);
871 }
872
873 writel(irqstaten, &regs->irqstaten);
874 writel(irqsigen, &regs->irqsigen);
875
876 esdhc_stop_tuning(mmc);
877
878 return ret;
879 }
880 #endif
881
882 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
883 {
884 struct fsl_esdhc *regs = priv->esdhc_regs;
885 int ret __maybe_unused;
886
887 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
888 /* Select to use peripheral clock */
889 esdhc_clock_control(priv, false);
890 esdhc_setbits32(&regs->scr, ESDHCCTL_PCS);
891 esdhc_clock_control(priv, true);
892 #endif
893 /* Set the clock speed */
894 if (priv->clock != mmc->clock)
895 set_sysctl(priv, mmc, mmc->clock);
896
897 #ifdef MMC_SUPPORTS_TUNING
898 if (mmc->clk_disable) {
899 #ifdef CONFIG_FSL_USDHC
900 esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
901 #else
902 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
903 #endif
904 } else {
905 #ifdef CONFIG_FSL_USDHC
906 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
907 VENDORSPEC_CKEN);
908 #else
909 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
910 #endif
911 }
912
913 if (priv->mode != mmc->selected_mode) {
914 ret = esdhc_set_timing(mmc);
915 if (ret) {
916 printf("esdhc_set_timing error %d\n", ret);
917 return ret;
918 }
919 }
920
921 if (priv->signal_voltage != mmc->signal_voltage) {
922 ret = esdhc_set_voltage(mmc);
923 if (ret) {
924 printf("esdhc_set_voltage error %d\n", ret);
925 return ret;
926 }
927 }
928 #endif
929
930 /* Set the bus width */
931 esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
932
933 if (mmc->bus_width == 4)
934 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
935 else if (mmc->bus_width == 8)
936 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
937
938 return 0;
939 }
940
941 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
942 {
943 struct fsl_esdhc *regs = priv->esdhc_regs;
944 ulong start;
945
946 /* Reset the entire host controller */
947 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
948
949 /* Wait until the controller is available */
950 start = get_timer(0);
951 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
952 if (get_timer(start) > 1000)
953 return -ETIMEDOUT;
954 }
955
956 #if defined(CONFIG_FSL_USDHC)
957 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
958 esdhc_write32(&regs->mmcboot, 0x0);
959 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
960 esdhc_write32(&regs->mixctrl, 0x0);
961 esdhc_write32(&regs->clktunectrlstatus, 0x0);
962
963 /* Put VEND_SPEC to default value */
964 if (priv->vs18_enable)
965 esdhc_write32(&regs->vendorspec, (VENDORSPEC_INIT |
966 ESDHC_VENDORSPEC_VSELECT));
967 else
968 esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
969
970 /* Disable DLL_CTRL delay line */
971 esdhc_write32(&regs->dllctrl, 0x0);
972 #endif
973
974 #ifndef ARCH_MXC
975 /* Enable cache snooping */
976 esdhc_write32(&regs->scr, 0x00000040);
977 #endif
978
979 #ifndef CONFIG_FSL_USDHC
980 esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
981 #else
982 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
983 #endif
984
985 /* Set the initial clock speed */
986 mmc_set_clock(mmc, 400000, false);
987
988 /* Disable the BRR and BWR bits in IRQSTAT */
989 esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
990
991 /* Put the PROCTL reg back to the default */
992 esdhc_write32(&regs->proctl, PROCTL_INIT);
993
994 /* Set timout to the maximum value */
995 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
996
997 return 0;
998 }
999
1000 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
1001 {
1002 struct fsl_esdhc *regs = priv->esdhc_regs;
1003 int timeout = 1000;
1004
1005 #ifdef CONFIG_ESDHC_DETECT_QUIRK
1006 if (CONFIG_ESDHC_DETECT_QUIRK)
1007 return 1;
1008 #endif
1009
1010 #if CONFIG_IS_ENABLED(DM_MMC)
1011 if (priv->non_removable)
1012 return 1;
1013 #ifdef CONFIG_DM_GPIO
1014 if (dm_gpio_is_valid(&priv->cd_gpio))
1015 return dm_gpio_get_value(&priv->cd_gpio);
1016 #endif
1017 #endif
1018
1019 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
1020 udelay(1000);
1021
1022 return timeout > 0;
1023 }
1024
1025 static int esdhc_reset(struct fsl_esdhc *regs)
1026 {
1027 ulong start;
1028
1029 /* reset the controller */
1030 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
1031
1032 /* hardware clears the bit when it is done */
1033 start = get_timer(0);
1034 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
1035 if (get_timer(start) > 100) {
1036 printf("MMC/SD: Reset never completed.\n");
1037 return -ETIMEDOUT;
1038 }
1039 }
1040
1041 return 0;
1042 }
1043
1044 #if !CONFIG_IS_ENABLED(DM_MMC)
1045 static int esdhc_getcd(struct mmc *mmc)
1046 {
1047 struct fsl_esdhc_priv *priv = mmc->priv;
1048
1049 return esdhc_getcd_common(priv);
1050 }
1051
1052 static int esdhc_init(struct mmc *mmc)
1053 {
1054 struct fsl_esdhc_priv *priv = mmc->priv;
1055
1056 return esdhc_init_common(priv, mmc);
1057 }
1058
1059 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1060 struct mmc_data *data)
1061 {
1062 struct fsl_esdhc_priv *priv = mmc->priv;
1063
1064 return esdhc_send_cmd_common(priv, mmc, cmd, data);
1065 }
1066
1067 static int esdhc_set_ios(struct mmc *mmc)
1068 {
1069 struct fsl_esdhc_priv *priv = mmc->priv;
1070
1071 return esdhc_set_ios_common(priv, mmc);
1072 }
1073
1074 static const struct mmc_ops esdhc_ops = {
1075 .getcd = esdhc_getcd,
1076 .init = esdhc_init,
1077 .send_cmd = esdhc_send_cmd,
1078 .set_ios = esdhc_set_ios,
1079 };
1080 #endif
1081
1082 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
1083 struct fsl_esdhc_plat *plat)
1084 {
1085 struct mmc_config *cfg;
1086 struct fsl_esdhc *regs;
1087 u32 caps, voltage_caps;
1088 int ret;
1089
1090 if (!priv)
1091 return -EINVAL;
1092
1093 regs = priv->esdhc_regs;
1094
1095 /* First reset the eSDHC controller */
1096 ret = esdhc_reset(regs);
1097 if (ret)
1098 return ret;
1099
1100 #ifndef CONFIG_FSL_USDHC
1101 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
1102 | SYSCTL_IPGEN | SYSCTL_CKEN);
1103 /* Clearing tuning bits in case ROM has set it already */
1104 esdhc_write32(&regs->mixctrl, 0);
1105 esdhc_write32(&regs->autoc12err, 0);
1106 esdhc_write32(&regs->clktunectrlstatus, 0);
1107 #else
1108 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
1109 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
1110 #endif
1111
1112 if (priv->vs18_enable)
1113 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
1114
1115 writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
1116 cfg = &plat->cfg;
1117 #ifndef CONFIG_DM_MMC
1118 memset(cfg, '\0', sizeof(*cfg));
1119 #endif
1120
1121 voltage_caps = 0;
1122 caps = esdhc_read32(&regs->hostcapblt);
1123
1124 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
1125 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
1126 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
1127 #endif
1128
1129 /* T4240 host controller capabilities register should have VS33 bit */
1130 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
1131 caps = caps | ESDHC_HOSTCAPBLT_VS33;
1132 #endif
1133
1134 if (caps & ESDHC_HOSTCAPBLT_VS18)
1135 voltage_caps |= MMC_VDD_165_195;
1136 if (caps & ESDHC_HOSTCAPBLT_VS30)
1137 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
1138 if (caps & ESDHC_HOSTCAPBLT_VS33)
1139 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
1140
1141 cfg->name = "FSL_SDHC";
1142 #if !CONFIG_IS_ENABLED(DM_MMC)
1143 cfg->ops = &esdhc_ops;
1144 #endif
1145 #ifdef CONFIG_SYS_SD_VOLTAGE
1146 cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
1147 #else
1148 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1149 #endif
1150 if ((cfg->voltages & voltage_caps) == 0) {
1151 printf("voltage not supported by controller\n");
1152 return -1;
1153 }
1154
1155 if (priv->bus_width == 8)
1156 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1157 else if (priv->bus_width == 4)
1158 cfg->host_caps = MMC_MODE_4BIT;
1159
1160 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1161 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
1162 cfg->host_caps |= MMC_MODE_DDR_52MHz;
1163 #endif
1164
1165 if (priv->bus_width > 0) {
1166 if (priv->bus_width < 8)
1167 cfg->host_caps &= ~MMC_MODE_8BIT;
1168 if (priv->bus_width < 4)
1169 cfg->host_caps &= ~MMC_MODE_4BIT;
1170 }
1171
1172 if (caps & ESDHC_HOSTCAPBLT_HSS)
1173 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1174
1175 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
1176 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
1177 cfg->host_caps &= ~MMC_MODE_8BIT;
1178 #endif
1179
1180 cfg->host_caps |= priv->caps;
1181
1182 cfg->f_min = 400000;
1183 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
1184
1185 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1186
1187 writel(0, &regs->dllctrl);
1188 if (priv->flags & ESDHC_FLAG_USDHC) {
1189 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
1190 u32 val = readl(&regs->tuning_ctrl);
1191
1192 val |= ESDHC_STD_TUNING_EN;
1193 val &= ~ESDHC_TUNING_START_TAP_MASK;
1194 val |= priv->tuning_start_tap;
1195 val &= ~ESDHC_TUNING_STEP_MASK;
1196 val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
1197 writel(val, &regs->tuning_ctrl);
1198 }
1199 }
1200
1201 return 0;
1202 }
1203
1204 #if !CONFIG_IS_ENABLED(DM_MMC)
1205 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
1206 struct fsl_esdhc_priv *priv)
1207 {
1208 if (!cfg || !priv)
1209 return -EINVAL;
1210
1211 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
1212 priv->bus_width = cfg->max_bus_width;
1213 priv->sdhc_clk = cfg->sdhc_clk;
1214 priv->wp_enable = cfg->wp_enable;
1215 priv->vs18_enable = cfg->vs18_enable;
1216
1217 return 0;
1218 };
1219
1220 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
1221 {
1222 struct fsl_esdhc_plat *plat;
1223 struct fsl_esdhc_priv *priv;
1224 struct mmc *mmc;
1225 int ret;
1226
1227 if (!cfg)
1228 return -EINVAL;
1229
1230 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
1231 if (!priv)
1232 return -ENOMEM;
1233 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
1234 if (!plat) {
1235 free(priv);
1236 return -ENOMEM;
1237 }
1238
1239 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
1240 if (ret) {
1241 debug("%s xlate failure\n", __func__);
1242 free(plat);
1243 free(priv);
1244 return ret;
1245 }
1246
1247 ret = fsl_esdhc_init(priv, plat);
1248 if (ret) {
1249 debug("%s init failure\n", __func__);
1250 free(plat);
1251 free(priv);
1252 return ret;
1253 }
1254
1255 mmc = mmc_create(&plat->cfg, priv);
1256 if (!mmc)
1257 return -EIO;
1258
1259 priv->mmc = mmc;
1260
1261 return 0;
1262 }
1263
1264 int fsl_esdhc_mmc_init(bd_t *bis)
1265 {
1266 struct fsl_esdhc_cfg *cfg;
1267
1268 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
1269 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
1270 cfg->sdhc_clk = gd->arch.sdhc_clk;
1271 return fsl_esdhc_initialize(bis, cfg);
1272 }
1273 #endif
1274
1275 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1276 void mmc_adapter_card_type_ident(void)
1277 {
1278 u8 card_id;
1279 u8 value;
1280
1281 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
1282 gd->arch.sdhc_adapter = card_id;
1283
1284 switch (card_id) {
1285 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
1286 value = QIXIS_READ(brdcfg[5]);
1287 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
1288 QIXIS_WRITE(brdcfg[5], value);
1289 break;
1290 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
1291 value = QIXIS_READ(pwr_ctl[1]);
1292 value |= QIXIS_EVDD_BY_SDHC_VS;
1293 QIXIS_WRITE(pwr_ctl[1], value);
1294 break;
1295 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
1296 value = QIXIS_READ(brdcfg[5]);
1297 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
1298 QIXIS_WRITE(brdcfg[5], value);
1299 break;
1300 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
1301 break;
1302 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
1303 break;
1304 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
1305 break;
1306 case QIXIS_ESDHC_NO_ADAPTER:
1307 break;
1308 default:
1309 break;
1310 }
1311 }
1312 #endif
1313
1314 #ifdef CONFIG_OF_LIBFDT
1315 __weak int esdhc_status_fixup(void *blob, const char *compat)
1316 {
1317 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
1318 if (!hwconfig("esdhc")) {
1319 do_fixup_by_compat(blob, compat, "status", "disabled",
1320 sizeof("disabled"), 1);
1321 return 1;
1322 }
1323 #endif
1324 return 0;
1325 }
1326
1327 void fdt_fixup_esdhc(void *blob, bd_t *bd)
1328 {
1329 const char *compat = "fsl,esdhc";
1330
1331 if (esdhc_status_fixup(blob, compat))
1332 return;
1333
1334 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
1335 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
1336 gd->arch.sdhc_clk, 1);
1337 #else
1338 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
1339 gd->arch.sdhc_clk, 1);
1340 #endif
1341 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1342 do_fixup_by_compat_u32(blob, compat, "adapter-type",
1343 (u32)(gd->arch.sdhc_adapter), 1);
1344 #endif
1345 }
1346 #endif
1347
1348 #if CONFIG_IS_ENABLED(DM_MMC)
1349 #include <asm/arch/clock.h>
1350 __weak void init_clk_usdhc(u32 index)
1351 {
1352 }
1353
1354 static int fsl_esdhc_probe(struct udevice *dev)
1355 {
1356 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1357 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1358 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1359 const void *fdt = gd->fdt_blob;
1360 int node = dev_of_offset(dev);
1361 struct esdhc_soc_data *data =
1362 (struct esdhc_soc_data *)dev_get_driver_data(dev);
1363 #ifdef CONFIG_DM_REGULATOR
1364 struct udevice *vqmmc_dev;
1365 #endif
1366 fdt_addr_t addr;
1367 unsigned int val;
1368 struct mmc *mmc;
1369 int ret;
1370
1371 addr = dev_read_addr(dev);
1372 if (addr == FDT_ADDR_T_NONE)
1373 return -EINVAL;
1374
1375 priv->esdhc_regs = (struct fsl_esdhc *)addr;
1376 priv->dev = dev;
1377 priv->mode = -1;
1378 if (data) {
1379 priv->flags = data->flags;
1380 priv->caps = data->caps;
1381 }
1382
1383 val = dev_read_u32_default(dev, "bus-width", -1);
1384 if (val == 8)
1385 priv->bus_width = 8;
1386 else if (val == 4)
1387 priv->bus_width = 4;
1388 else
1389 priv->bus_width = 1;
1390
1391 val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
1392 priv->tuning_step = val;
1393 val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
1394 ESDHC_TUNING_START_TAP_DEFAULT);
1395 priv->tuning_start_tap = val;
1396 val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
1397 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
1398 priv->strobe_dll_delay_target = val;
1399
1400 if (dev_read_bool(dev, "non-removable")) {
1401 priv->non_removable = 1;
1402 } else {
1403 priv->non_removable = 0;
1404 #ifdef CONFIG_DM_GPIO
1405 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1406 GPIOD_IS_IN);
1407 #endif
1408 }
1409
1410 priv->wp_enable = 1;
1411
1412 #ifdef CONFIG_DM_GPIO
1413 ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1414 GPIOD_IS_IN);
1415 if (ret)
1416 priv->wp_enable = 0;
1417 #endif
1418
1419 priv->vs18_enable = 0;
1420
1421 #ifdef CONFIG_DM_REGULATOR
1422 /*
1423 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1424 * otherwise, emmc will work abnormally.
1425 */
1426 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1427 if (ret) {
1428 dev_dbg(dev, "no vqmmc-supply\n");
1429 } else {
1430 ret = regulator_set_enable(vqmmc_dev, true);
1431 if (ret) {
1432 dev_err(dev, "fail to enable vqmmc-supply\n");
1433 return ret;
1434 }
1435
1436 if (regulator_get_value(vqmmc_dev) == 1800000)
1437 priv->vs18_enable = 1;
1438 }
1439 #endif
1440
1441 if (fdt_get_property(fdt, node, "no-1-8-v", NULL))
1442 priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200);
1443
1444 /*
1445 * TODO:
1446 * Because lack of clk driver, if SDHC clk is not enabled,
1447 * need to enable it first before this driver is invoked.
1448 *
1449 * we use MXC_ESDHC_CLK to get clk freq.
1450 * If one would like to make this function work,
1451 * the aliases should be provided in dts as this:
1452 *
1453 * aliases {
1454 * mmc0 = &usdhc1;
1455 * mmc1 = &usdhc2;
1456 * mmc2 = &usdhc3;
1457 * mmc3 = &usdhc4;
1458 * };
1459 * Then if your board only supports mmc2 and mmc3, but we can
1460 * correctly get the seq as 2 and 3, then let mxc_get_clock
1461 * work as expected.
1462 */
1463
1464 init_clk_usdhc(dev->seq);
1465
1466 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1467 if (priv->sdhc_clk <= 0) {
1468 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1469 return -EINVAL;
1470 }
1471
1472 ret = fsl_esdhc_init(priv, plat);
1473 if (ret) {
1474 dev_err(dev, "fsl_esdhc_init failure\n");
1475 return ret;
1476 }
1477
1478 mmc = &plat->mmc;
1479 mmc->cfg = &plat->cfg;
1480 mmc->dev = dev;
1481 upriv->mmc = mmc;
1482
1483 return esdhc_init_common(priv, mmc);
1484 }
1485
1486 #if CONFIG_IS_ENABLED(DM_MMC)
1487 static int fsl_esdhc_get_cd(struct udevice *dev)
1488 {
1489 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1490
1491 return true;
1492 return esdhc_getcd_common(priv);
1493 }
1494
1495 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1496 struct mmc_data *data)
1497 {
1498 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1499 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1500
1501 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1502 }
1503
1504 static int fsl_esdhc_set_ios(struct udevice *dev)
1505 {
1506 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1507 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1508
1509 return esdhc_set_ios_common(priv, &plat->mmc);
1510 }
1511
1512 static const struct dm_mmc_ops fsl_esdhc_ops = {
1513 .get_cd = fsl_esdhc_get_cd,
1514 .send_cmd = fsl_esdhc_send_cmd,
1515 .set_ios = fsl_esdhc_set_ios,
1516 #ifdef MMC_SUPPORTS_TUNING
1517 .execute_tuning = fsl_esdhc_execute_tuning,
1518 #endif
1519 };
1520 #endif
1521
1522 static struct esdhc_soc_data usdhc_imx7d_data = {
1523 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
1524 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
1525 | ESDHC_FLAG_HS400,
1526 .caps = UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_DDR_52MHz |
1527 MMC_MODE_HS_52MHz | MMC_MODE_HS,
1528 };
1529
1530 static const struct udevice_id fsl_esdhc_ids[] = {
1531 { .compatible = "fsl,imx6ul-usdhc", },
1532 { .compatible = "fsl,imx6sx-usdhc", },
1533 { .compatible = "fsl,imx6sl-usdhc", },
1534 { .compatible = "fsl,imx6q-usdhc", },
1535 { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
1536 { .compatible = "fsl,imx7ulp-usdhc", },
1537 { .compatible = "fsl,esdhc", },
1538 { /* sentinel */ }
1539 };
1540
1541 #if CONFIG_IS_ENABLED(BLK)
1542 static int fsl_esdhc_bind(struct udevice *dev)
1543 {
1544 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1545
1546 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1547 }
1548 #endif
1549
1550 U_BOOT_DRIVER(fsl_esdhc) = {
1551 .name = "fsl-esdhc-mmc",
1552 .id = UCLASS_MMC,
1553 .of_match = fsl_esdhc_ids,
1554 .ops = &fsl_esdhc_ops,
1555 #if CONFIG_IS_ENABLED(BLK)
1556 .bind = fsl_esdhc_bind,
1557 #endif
1558 .probe = fsl_esdhc_probe,
1559 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
1560 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
1561 };
1562 #endif
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