2 * Copyright 2007,2010 Freescale Semiconductor, Inc
5 * Based vaguely on the pxa mmc code:
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #include <fsl_esdhc.h>
37 #include <fdt_support.h>
40 DECLARE_GLOBAL_DATA_PTR
;
69 /* Return the XFERTYP flags for a given command and data packet */
70 uint
esdhc_xfertyp(struct mmc_cmd
*cmd
, struct mmc_data
*data
)
75 xfertyp
|= XFERTYP_DPSEL
;
76 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
77 xfertyp
|= XFERTYP_DMAEN
;
79 if (data
->blocks
> 1) {
80 xfertyp
|= XFERTYP_MSBSEL
;
81 xfertyp
|= XFERTYP_BCEN
;
84 if (data
->flags
& MMC_DATA_READ
)
85 xfertyp
|= XFERTYP_DTDSEL
;
88 if (cmd
->resp_type
& MMC_RSP_CRC
)
89 xfertyp
|= XFERTYP_CCCEN
;
90 if (cmd
->resp_type
& MMC_RSP_OPCODE
)
91 xfertyp
|= XFERTYP_CICEN
;
92 if (cmd
->resp_type
& MMC_RSP_136
)
93 xfertyp
|= XFERTYP_RSPTYP_136
;
94 else if (cmd
->resp_type
& MMC_RSP_BUSY
)
95 xfertyp
|= XFERTYP_RSPTYP_48_BUSY
;
96 else if (cmd
->resp_type
& MMC_RSP_PRESENT
)
97 xfertyp
|= XFERTYP_RSPTYP_48
;
99 return XFERTYP_CMD(cmd
->cmdidx
) | xfertyp
;
102 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
104 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
107 esdhc_pio_read_write(struct mmc
*mmc
, struct mmc_data
*data
)
109 struct fsl_esdhc
*regs
= mmc
->priv
;
117 if (data
->flags
& MMC_DATA_READ
) {
118 blocks
= data
->blocks
;
121 timeout
= PIO_TIMEOUT
;
122 size
= data
->blocksize
;
123 irqstat
= esdhc_read32(®s
->irqstat
);
124 while (!(esdhc_read32(®s
->prsstat
) & PRSSTAT_BREN
)
127 printf("\nData Read Failed in PIO Mode.");
130 while (size
&& (!(irqstat
& IRQSTAT_TC
))) {
131 udelay(100); /* Wait before last byte transfer complete */
132 irqstat
= esdhc_read32(®s
->irqstat
);
133 databuf
= in_le32(®s
->datport
);
134 *((uint
*)buffer
) = databuf
;
141 blocks
= data
->blocks
;
142 buffer
= (char *)data
->src
;
144 timeout
= PIO_TIMEOUT
;
145 size
= data
->blocksize
;
146 irqstat
= esdhc_read32(®s
->irqstat
);
147 while (!(esdhc_read32(®s
->prsstat
) & PRSSTAT_BWEN
)
150 printf("\nData Write Failed in PIO Mode.");
153 while (size
&& (!(irqstat
& IRQSTAT_TC
))) {
154 udelay(100); /* Wait before last byte transfer complete */
155 databuf
= *((uint
*)buffer
);
158 irqstat
= esdhc_read32(®s
->irqstat
);
159 out_le32(®s
->datport
, databuf
);
167 static int esdhc_setup_data(struct mmc
*mmc
, struct mmc_data
*data
)
170 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
171 struct fsl_esdhc
*regs
= (struct fsl_esdhc
*)cfg
->esdhc_base
;
172 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
175 wml_value
= data
->blocksize
/4;
177 if (data
->flags
& MMC_DATA_READ
) {
178 if (wml_value
> 0x10)
181 esdhc_clrsetbits32(®s
->wml
, WML_RD_WML_MASK
, wml_value
);
182 esdhc_write32(®s
->dsaddr
, (u32
)data
->dest
);
184 if (wml_value
> 0x80)
186 if ((esdhc_read32(®s
->prsstat
) & PRSSTAT_WPSPL
) == 0) {
187 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
191 esdhc_clrsetbits32(®s
->wml
, WML_WR_WML_MASK
,
193 esdhc_write32(®s
->dsaddr
, (u32
)data
->src
);
195 #else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
196 if (!(data
->flags
& MMC_DATA_READ
)) {
197 if ((esdhc_read32(®s
->prsstat
) & PRSSTAT_WPSPL
) == 0) {
198 printf("\nThe SD card is locked. "
199 "Can not write to a locked card.\n\n");
202 esdhc_write32(®s
->dsaddr
, (u32
)data
->src
);
204 esdhc_write32(®s
->dsaddr
, (u32
)data
->dest
);
205 #endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
207 esdhc_write32(®s
->blkattr
, data
->blocks
<< 16 | data
->blocksize
);
209 /* Calculate the timeout period for data transactions */
210 timeout
= fls(mmc
->tran_speed
/10) - 1;
219 esdhc_clrsetbits32(®s
->sysctl
, SYSCTL_TIMEOUT_MASK
, timeout
<< 16);
226 * Sends a command out on the bus. Takes the mmc pointer,
227 * a command pointer, and an optional data pointer.
230 esdhc_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*cmd
, struct mmc_data
*data
)
234 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
235 volatile struct fsl_esdhc
*regs
= (struct fsl_esdhc
*)cfg
->esdhc_base
;
237 esdhc_write32(®s
->irqstat
, -1);
241 /* Wait for the bus to be idle */
242 while ((esdhc_read32(®s
->prsstat
) & PRSSTAT_CICHB
) ||
243 (esdhc_read32(®s
->prsstat
) & PRSSTAT_CIDHB
))
246 while (esdhc_read32(®s
->prsstat
) & PRSSTAT_DLA
)
249 /* Wait at least 8 SD clock cycles before the next command */
251 * Note: This is way more than 8 cycles, but 1ms seems to
252 * resolve timing issues with some cards
256 /* Set up for a data transfer if we have one */
260 err
= esdhc_setup_data(mmc
, data
);
265 /* Figure out the transfer arguments */
266 xfertyp
= esdhc_xfertyp(cmd
, data
);
268 /* Send the command */
269 esdhc_write32(®s
->cmdarg
, cmd
->cmdarg
);
270 esdhc_write32(®s
->xfertyp
, xfertyp
);
272 /* Wait for the command to complete */
273 while (!(esdhc_read32(®s
->irqstat
) & IRQSTAT_CC
))
276 irqstat
= esdhc_read32(®s
->irqstat
);
277 esdhc_write32(®s
->irqstat
, irqstat
);
279 if (irqstat
& CMD_ERR
)
282 if (irqstat
& IRQSTAT_CTOE
)
285 /* Copy the response to the response buffer */
286 if (cmd
->resp_type
& MMC_RSP_136
) {
287 u32 cmdrsp3
, cmdrsp2
, cmdrsp1
, cmdrsp0
;
289 cmdrsp3
= esdhc_read32(®s
->cmdrsp3
);
290 cmdrsp2
= esdhc_read32(®s
->cmdrsp2
);
291 cmdrsp1
= esdhc_read32(®s
->cmdrsp1
);
292 cmdrsp0
= esdhc_read32(®s
->cmdrsp0
);
293 cmd
->response
[0] = (cmdrsp3
<< 8) | (cmdrsp2
>> 24);
294 cmd
->response
[1] = (cmdrsp2
<< 8) | (cmdrsp1
>> 24);
295 cmd
->response
[2] = (cmdrsp1
<< 8) | (cmdrsp0
>> 24);
296 cmd
->response
[3] = (cmdrsp0
<< 8);
298 cmd
->response
[0] = esdhc_read32(®s
->cmdrsp0
);
300 /* Wait until all of the blocks are transferred */
302 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
303 esdhc_pio_read_write(mmc
, data
);
306 irqstat
= esdhc_read32(®s
->irqstat
);
308 if (irqstat
& DATA_ERR
)
311 if (irqstat
& IRQSTAT_DTOE
)
313 } while (!(irqstat
& IRQSTAT_TC
) &&
314 (esdhc_read32(®s
->prsstat
) & PRSSTAT_DLA
));
318 esdhc_write32(®s
->irqstat
, -1);
323 void set_sysctl(struct mmc
*mmc
, uint clock
)
325 int sdhc_clk
= gd
->sdhc_clk
;
327 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
328 volatile struct fsl_esdhc
*regs
= (struct fsl_esdhc
*)cfg
->esdhc_base
;
331 if (clock
< mmc
->f_min
)
334 if (sdhc_clk
/ 16 > clock
) {
335 for (pre_div
= 2; pre_div
< 256; pre_div
*= 2)
336 if ((sdhc_clk
/ pre_div
) <= (clock
* 16))
341 for (div
= 1; div
<= 16; div
++)
342 if ((sdhc_clk
/ (div
* pre_div
)) <= clock
)
348 clk
= (pre_div
<< 8) | (div
<< 4);
350 esdhc_clrbits32(®s
->sysctl
, SYSCTL_CKEN
);
352 esdhc_clrsetbits32(®s
->sysctl
, SYSCTL_CLOCK_MASK
, clk
);
356 clk
= SYSCTL_PEREN
| SYSCTL_CKEN
;
358 esdhc_setbits32(®s
->sysctl
, clk
);
361 static void esdhc_set_ios(struct mmc
*mmc
)
363 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
364 struct fsl_esdhc
*regs
= (struct fsl_esdhc
*)cfg
->esdhc_base
;
366 /* Set the clock speed */
367 set_sysctl(mmc
, mmc
->clock
);
369 /* Set the bus width */
370 esdhc_clrbits32(®s
->proctl
, PROCTL_DTW_4
| PROCTL_DTW_8
);
372 if (mmc
->bus_width
== 4)
373 esdhc_setbits32(®s
->proctl
, PROCTL_DTW_4
);
374 else if (mmc
->bus_width
== 8)
375 esdhc_setbits32(®s
->proctl
, PROCTL_DTW_8
);
379 static int esdhc_init(struct mmc
*mmc
)
381 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
382 struct fsl_esdhc
*regs
= (struct fsl_esdhc
*)cfg
->esdhc_base
;
387 /* Enable cache snooping */
388 if (cfg
&& !cfg
->no_snoop
)
389 esdhc_write32(®s
->scr
, 0x00000040);
391 /* Reset the entire host controller */
392 esdhc_write32(®s
->sysctl
, SYSCTL_RSTA
);
394 /* Wait until the controller is available */
395 while ((esdhc_read32(®s
->sysctl
) & SYSCTL_RSTA
) && --timeout
)
398 esdhc_write32(®s
->sysctl
, SYSCTL_HCKEN
| SYSCTL_IPGEN
);
400 /* Set the initial clock speed */
401 set_sysctl(mmc
, 400000);
403 /* Disable the BRR and BWR bits in IRQSTAT */
404 esdhc_clrbits32(®s
->irqstaten
, IRQSTATEN_BRR
| IRQSTATEN_BWR
);
406 /* Put the PROCTL reg back to the default */
407 esdhc_write32(®s
->proctl
, PROCTL_INIT
);
409 /* Set timout to the maximum value */
410 esdhc_clrsetbits32(®s
->sysctl
, SYSCTL_TIMEOUT_MASK
, 14 << 16);
412 /* Check if there is a callback for detecting the card */
413 if (board_mmc_getcd(&card_absent
, mmc
)) {
415 while (!(esdhc_read32(®s
->prsstat
) & PRSSTAT_CINS
) &&
429 static void esdhc_reset(struct fsl_esdhc
*regs
)
431 unsigned long timeout
= 100; /* wait max 100 ms */
433 /* reset the controller */
434 esdhc_write32(®s
->sysctl
, SYSCTL_RSTA
);
436 /* hardware clears the bit when it is done */
437 while ((esdhc_read32(®s
->sysctl
) & SYSCTL_RSTA
) && --timeout
)
440 printf("MMC/SD: Reset never completed.\n");
443 int fsl_esdhc_initialize(bd_t
*bis
, struct fsl_esdhc_cfg
*cfg
)
445 struct fsl_esdhc
*regs
;
452 mmc
= malloc(sizeof(struct mmc
));
454 sprintf(mmc
->name
, "FSL_ESDHC");
455 regs
= (struct fsl_esdhc
*)cfg
->esdhc_base
;
457 /* First reset the eSDHC controller */
461 mmc
->send_cmd
= esdhc_send_cmd
;
462 mmc
->set_ios
= esdhc_set_ios
;
463 mmc
->init
= esdhc_init
;
465 caps
= regs
->hostcapblt
;
467 if (caps
& ESDHC_HOSTCAPBLT_VS18
)
468 mmc
->voltages
|= MMC_VDD_165_195
;
469 if (caps
& ESDHC_HOSTCAPBLT_VS30
)
470 mmc
->voltages
|= MMC_VDD_29_30
| MMC_VDD_30_31
;
471 if (caps
& ESDHC_HOSTCAPBLT_VS33
)
472 mmc
->voltages
|= MMC_VDD_32_33
| MMC_VDD_33_34
;
474 mmc
->host_caps
= MMC_MODE_4BIT
| MMC_MODE_8BIT
;
476 if (caps
& ESDHC_HOSTCAPBLT_HSS
)
477 mmc
->host_caps
|= MMC_MODE_HS_52MHz
| MMC_MODE_HS
;
480 mmc
->f_max
= MIN(gd
->sdhc_clk
, 50000000);
487 int fsl_esdhc_mmc_init(bd_t
*bis
)
489 struct fsl_esdhc_cfg
*cfg
;
491 cfg
= malloc(sizeof(struct fsl_esdhc_cfg
));
492 memset(cfg
, 0, sizeof(struct fsl_esdhc_cfg
));
493 cfg
->esdhc_base
= CONFIG_SYS_FSL_ESDHC_ADDR
;
494 return fsl_esdhc_initialize(bis
, cfg
);
497 #ifdef CONFIG_OF_LIBFDT
498 void fdt_fixup_esdhc(void *blob
, bd_t
*bd
)
500 const char *compat
= "fsl,esdhc";
501 const char *status
= "okay";
503 if (!hwconfig("esdhc")) {
508 do_fixup_by_compat_u32(blob
, compat
, "clock-frequency",
511 do_fixup_by_compat(blob
, compat
, "status", status
,
512 strlen(status
) + 1, 1);