drivers/mmc/fsl_esdhc.c

   1 /*
   2  * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
   3  * Andy Fleming
   4  *
   5  * Based vaguely on the pxa mmc code:
   6  * (C) Copyright 2003
   7  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <config.h>
  13 #include <common.h>
  14 #include <command.h>
  15 #include <hwconfig.h>
  16 #include <mmc.h>
  17 #include <part.h>
  18 #include <malloc.h>
  19 #include <mmc.h>
  20 #include <fsl_esdhc.h>
  21 #include <fdt_support.h>
  22 #include <asm/io.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #define SDHCI_IRQ_EN_BITS               (IRQSTATEN_CC | IRQSTATEN_TC | \
  27                                 IRQSTATEN_CINT | \
  28                                 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
  29                                 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
  30                                 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
  31                                 IRQSTATEN_DINT)
  32
  33 struct fsl_esdhc {
  34         uint    dsaddr;         /* SDMA system address register */
  35         uint    blkattr;        /* Block attributes register */
  36         uint    cmdarg;         /* Command argument register */
  37         uint    xfertyp;        /* Transfer type register */
  38         uint    cmdrsp0;        /* Command response 0 register */
  39         uint    cmdrsp1;        /* Command response 1 register */
  40         uint    cmdrsp2;        /* Command response 2 register */
  41         uint    cmdrsp3;        /* Command response 3 register */
  42         uint    datport;        /* Buffer data port register */
  43         uint    prsstat;        /* Present state register */
  44         uint    proctl;         /* Protocol control register */
  45         uint    sysctl;         /* System Control Register */
  46         uint    irqstat;        /* Interrupt status register */
  47         uint    irqstaten;      /* Interrupt status enable register */
  48         uint    irqsigen;       /* Interrupt signal enable register */
  49         uint    autoc12err;     /* Auto CMD error status register */
  50         uint    hostcapblt;     /* Host controller capabilities register */
  51         uint    wml;            /* Watermark level register */
  52         uint    mixctrl;        /* For USDHC */
  53         char    reserved1[4];   /* reserved */
  54         uint    fevt;           /* Force event register */
  55         uint    admaes;         /* ADMA error status register */
  56         uint    adsaddr;        /* ADMA system address register */
  57         char    reserved2[100]; /* reserved */
  58         uint    vendorspec;     /* Vendor Specific register */
  59         char    reserved3[56];  /* reserved */
  60         uint    hostver;        /* Host controller version register */
  61         char    reserved4[4];   /* reserved */
  62         uint    dmaerraddr;     /* DMA error address register */
  63         char    reserved5[4];   /* reserved */
  64         uint    dmaerrattr;     /* DMA error attribute register */
  65         char    reserved6[4];   /* reserved */
  66         uint    hostcapblt2;    /* Host controller capabilities register 2 */
  67         char    reserved7[8];   /* reserved */
  68         uint    tcr;            /* Tuning control register */
  69         char    reserved8[28];  /* reserved */
  70         uint    sddirctl;       /* SD direction control register */
  71         char    reserved9[712]; /* reserved */
  72         uint    scr;            /* eSDHC control register */
  73 };
  74
  75 /* Return the XFERTYP flags for a given command and data packet */
  76 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
  77 {
  78         uint xfertyp = 0;
  79
  80         if (data) {
  81                 xfertyp |= XFERTYP_DPSEL;
  82 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  83                 xfertyp |= XFERTYP_DMAEN;
  84 #endif
  85                 if (data->blocks > 1) {
  86                         xfertyp |= XFERTYP_MSBSEL;
  87                         xfertyp |= XFERTYP_BCEN;
  88 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
  89                         xfertyp |= XFERTYP_AC12EN;
  90 #endif
  91                 }
  92
  93                 if (data->flags & MMC_DATA_READ)
  94                         xfertyp |= XFERTYP_DTDSEL;
  95         }
  96
  97         if (cmd->resp_type & MMC_RSP_CRC)
  98                 xfertyp |= XFERTYP_CCCEN;
  99         if (cmd->resp_type & MMC_RSP_OPCODE)
 100                 xfertyp |= XFERTYP_CICEN;
 101         if (cmd->resp_type & MMC_RSP_136)
 102                 xfertyp |= XFERTYP_RSPTYP_136;
 103         else if (cmd->resp_type & MMC_RSP_BUSY)
 104                 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
 105         else if (cmd->resp_type & MMC_RSP_PRESENT)
 106                 xfertyp |= XFERTYP_RSPTYP_48;
 107
 108 #if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \
 109         defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A)
 110         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 111                 xfertyp |= XFERTYP_CMDTYP_ABORT;
 112 #endif
 113         return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
 114 }
 115
 116 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
 117 /*
 118  * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
 119  */
 120 static void
 121 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
 122 {
 123         struct fsl_esdhc_cfg *cfg = mmc->priv;
 124         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 125         uint blocks;
 126         char *buffer;
 127         uint databuf;
 128         uint size;
 129         uint irqstat;
 130         uint timeout;
 131
 132         if (data->flags & MMC_DATA_READ) {
 133                 blocks = data->blocks;
 134                 buffer = data->dest;
 135                 while (blocks) {
 136                         timeout = PIO_TIMEOUT;
 137                         size = data->blocksize;
 138                         irqstat = esdhc_read32(&regs->irqstat);
 139                         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
 140                                 && --timeout);
 141                         if (timeout <= 0) {
 142                                 printf("\nData Read Failed in PIO Mode.");
 143                                 return;
 144                         }
 145                         while (size && (!(irqstat & IRQSTAT_TC))) {
 146                                 udelay(100); /* Wait before last byte transfer complete */
 147                                 irqstat = esdhc_read32(&regs->irqstat);
 148                                 databuf = in_le32(&regs->datport);
 149                                 *((uint *)buffer) = databuf;
 150                                 buffer += 4;
 151                                 size -= 4;
 152                         }
 153                         blocks--;
 154                 }
 155         } else {
 156                 blocks = data->blocks;
 157                 buffer = (char *)data->src;
 158                 while (blocks) {
 159                         timeout = PIO_TIMEOUT;
 160                         size = data->blocksize;
 161                         irqstat = esdhc_read32(&regs->irqstat);
 162                         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
 163                                 && --timeout);
 164                         if (timeout <= 0) {
 165                                 printf("\nData Write Failed in PIO Mode.");
 166                                 return;
 167                         }
 168                         while (size && (!(irqstat & IRQSTAT_TC))) {
 169                                 udelay(100); /* Wait before last byte transfer complete */
 170                                 databuf = *((uint *)buffer);
 171                                 buffer += 4;
 172                                 size -= 4;
 173                                 irqstat = esdhc_read32(&regs->irqstat);
 174                                 out_le32(&regs->datport, databuf);
 175                         }
 176                         blocks--;
 177                 }
 178         }
 179 }
 180 #endif
 181
 182 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 183 {
 184         int timeout;
 185         struct fsl_esdhc_cfg *cfg = mmc->priv;
 186         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 187 #ifdef CONFIG_LS2085A
 188         dma_addr_t addr;
 189 #endif
 190         uint wml_value;
 191
 192         wml_value = data->blocksize/4;
 193
 194         if (data->flags & MMC_DATA_READ) {
 195                 if (wml_value > WML_RD_WML_MAX)
 196                         wml_value = WML_RD_WML_MAX_VAL;
 197
 198                 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
 199 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 200 #ifdef CONFIG_LS2085A
 201                 addr = virt_to_phys((void *)(data->dest));
 202                 if (upper_32_bits(addr))
 203                         printf("Error found for upper 32 bits\n");
 204                 else
 205                         esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
 206 #else
 207                 esdhc_write32(&regs->dsaddr, (u32)data->dest);
 208 #endif
 209 #endif
 210         } else {
 211 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 212                 flush_dcache_range((ulong)data->src,
 213                                    (ulong)data->src+data->blocks
 214                                          *data->blocksize);
 215 #endif
 216                 if (wml_value > WML_WR_WML_MAX)
 217                         wml_value = WML_WR_WML_MAX_VAL;
 218                 if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
 219                         printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
 220                         return TIMEOUT;
 221                 }
 222
 223                 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
 224                                         wml_value << 16);
 225 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 226 #ifdef CONFIG_LS2085A
 227                 addr = virt_to_phys((void *)(data->src));
 228                 if (upper_32_bits(addr))
 229                         printf("Error found for upper 32 bits\n");
 230                 else
 231                         esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
 232 #else
 233                 esdhc_write32(&regs->dsaddr, (u32)data->src);
 234 #endif
 235 #endif
 236         }
 237
 238         esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
 239
 240         /* Calculate the timeout period for data transactions */
 241         /*
 242          * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
 243          * 2)Timeout period should be minimum 0.250sec as per SD Card spec
 244          *  So, Number of SD Clock cycles for 0.25sec should be minimum
 245          *              (SD Clock/sec * 0.25 sec) SD Clock cycles
 246          *              = (mmc->clock * 1/4) SD Clock cycles
 247          * As 1) >=  2)
 248          * => (2^(timeout+13)) >= mmc->clock * 1/4
 249          * Taking log2 both the sides
 250          * => timeout + 13 >= log2(mmc->clock/4)
 251          * Rounding up to next power of 2
 252          * => timeout + 13 = log2(mmc->clock/4) + 1
 253          * => timeout + 13 = fls(mmc->clock/4)
 254          */
 255         timeout = fls(mmc->clock/4);
 256         timeout -= 13;
 257
 258         if (timeout > 14)
 259                 timeout = 14;
 260
 261         if (timeout < 0)
 262                 timeout = 0;
 263
 264 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
 265         if ((timeout == 4) || (timeout == 8) || (timeout == 12))
 266                 timeout++;
 267 #endif
 268
 269 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 270         timeout = 0xE;
 271 #endif
 272         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
 273
 274         return 0;
 275 }
 276
 277 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 278 static void check_and_invalidate_dcache_range
 279         (struct mmc_cmd *cmd,
 280          struct mmc_data *data) {
 281 #ifdef CONFIG_LS2085A
 282         unsigned start = 0;
 283 #else
 284         unsigned start = (unsigned)data->dest ;
 285 #endif
 286         unsigned size = roundup(ARCH_DMA_MINALIGN,
 287                                 data->blocks*data->blocksize);
 288         unsigned end = start+size ;
 289 #ifdef CONFIG_LS2085A
 290         dma_addr_t addr;
 291
 292         addr = virt_to_phys((void *)(data->dest));
 293         if (upper_32_bits(addr))
 294                 printf("Error found for upper 32 bits\n");
 295         else
 296                 start = lower_32_bits(addr);
 297 #endif
 298         invalidate_dcache_range(start, end);
 299 }
 300 #endif
 301
 302 /*
 303  * Sends a command out on the bus.  Takes the mmc pointer,
 304  * a command pointer, and an optional data pointer.
 305  */
 306 static int
 307 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 308 {
 309         int     err = 0;
 310         uint    xfertyp;
 311         uint    irqstat;
 312         struct fsl_esdhc_cfg *cfg = mmc->priv;
 313         volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 314
 315 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
 316         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 317                 return 0;
 318 #endif
 319
 320         esdhc_write32(&regs->irqstat, -1);
 321
 322         sync();
 323
 324         /* Wait for the bus to be idle */
 325         while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
 326                         (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
 327                 ;
 328
 329         while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
 330                 ;
 331
 332         /* Wait at least 8 SD clock cycles before the next command */
 333         /*
 334          * Note: This is way more than 8 cycles, but 1ms seems to
 335          * resolve timing issues with some cards
 336          */
 337         udelay(1000);
 338
 339         /* Set up for a data transfer if we have one */
 340         if (data) {
 341                 err = esdhc_setup_data(mmc, data);
 342                 if(err)
 343                         return err;
 344         }
 345
 346         /* Figure out the transfer arguments */
 347         xfertyp = esdhc_xfertyp(cmd, data);
 348
 349         /* Mask all irqs */
 350         esdhc_write32(&regs->irqsigen, 0);
 351
 352         /* Send the command */
 353         esdhc_write32(&regs->cmdarg, cmd->cmdarg);
 354 #if defined(CONFIG_FSL_USDHC)
 355         esdhc_write32(&regs->mixctrl,
 356         (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
 357                         | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
 358         esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
 359 #else
 360         esdhc_write32(&regs->xfertyp, xfertyp);
 361 #endif
 362
 363         /* Wait for the command to complete */
 364         while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
 365                 ;
 366
 367         irqstat = esdhc_read32(&regs->irqstat);
 368
 369         if (irqstat & CMD_ERR) {
 370                 err = COMM_ERR;
 371                 goto out;
 372         }
 373
 374         if (irqstat & IRQSTAT_CTOE) {
 375                 err = TIMEOUT;
 376                 goto out;
 377         }
 378
 379         /* Switch voltage to 1.8V if CMD11 succeeded */
 380         if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
 381                 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
 382
 383                 printf("Run CMD11 1.8V switch\n");
 384                 /* Sleep for 5 ms - max time for card to switch to 1.8V */
 385                 udelay(5000);
 386         }
 387
 388         /* Workaround for ESDHC errata ENGcm03648 */
 389         if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
 390                 int timeout = 6000;
 391
 392                 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
 393                 while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
 394                                         PRSSTAT_DAT0)) {
 395                         udelay(100);
 396                         timeout--;
 397                 }
 398
 399                 if (timeout <= 0) {
 400                         printf("Timeout waiting for DAT0 to go high!\n");
 401                         err = TIMEOUT;
 402                         goto out;
 403                 }
 404         }
 405
 406         /* Copy the response to the response buffer */
 407         if (cmd->resp_type & MMC_RSP_136) {
 408                 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
 409
 410                 cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
 411                 cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
 412                 cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
 413                 cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
 414                 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
 415                 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
 416                 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
 417                 cmd->response[3] = (cmdrsp0 << 8);
 418         } else
 419                 cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
 420
 421         /* Wait until all of the blocks are transferred */
 422         if (data) {
 423 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
 424                 esdhc_pio_read_write(mmc, data);
 425 #else
 426                 do {
 427                         irqstat = esdhc_read32(&regs->irqstat);
 428
 429                         if (irqstat & IRQSTAT_DTOE) {
 430                                 err = TIMEOUT;
 431                                 goto out;
 432                         }
 433
 434                         if (irqstat & DATA_ERR) {
 435                                 err = COMM_ERR;
 436                                 goto out;
 437                         }
 438                 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
 439
 440                 if (data->flags & MMC_DATA_READ)
 441                         check_and_invalidate_dcache_range(cmd, data);
 442 #endif
 443         }
 444
 445 out:
 446         /* Reset CMD and DATA portions on error */
 447         if (err) {
 448                 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
 449                               SYSCTL_RSTC);
 450                 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
 451                         ;
 452
 453                 if (data) {
 454                         esdhc_write32(&regs->sysctl,
 455                                       esdhc_read32(&regs->sysctl) |
 456                                       SYSCTL_RSTD);
 457                         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
 458                                 ;
 459                 }
 460
 461                 /* If this was CMD11, then notify that power cycle is needed */
 462                 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
 463                         printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
 464         }
 465
 466         esdhc_write32(&regs->irqstat, -1);
 467
 468         return err;
 469 }
 470
 471 static void set_sysctl(struct mmc *mmc, uint clock)
 472 {
 473         int div, pre_div;
 474         struct fsl_esdhc_cfg *cfg = mmc->priv;
 475         volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 476         int sdhc_clk = cfg->sdhc_clk;
 477         uint clk;
 478
 479         if (clock < mmc->cfg->f_min)
 480                 clock = mmc->cfg->f_min;
 481
 482         if (sdhc_clk / 16 > clock) {
 483                 for (pre_div = 2; pre_div < 256; pre_div *= 2)
 484                         if ((sdhc_clk / pre_div) <= (clock * 16))
 485                                 break;
 486         } else
 487                 pre_div = 2;
 488
 489         for (div = 1; div <= 16; div++)
 490                 if ((sdhc_clk / (div * pre_div)) <= clock)
 491                         break;
 492
 493         pre_div >>= mmc->ddr_mode ? 2 : 1;
 494         div -= 1;
 495
 496         clk = (pre_div << 8) | (div << 4);
 497
 498         esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
 499
 500         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
 501
 502         udelay(10000);
 503
 504         clk = SYSCTL_PEREN | SYSCTL_CKEN;
 505
 506         esdhc_setbits32(&regs->sysctl, clk);
 507 }
 508
 509 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 510 static void esdhc_clock_control(struct mmc *mmc, bool enable)
 511 {
 512         struct fsl_esdhc_cfg *cfg = mmc->priv;
 513         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 514         u32 value;
 515         u32 time_out;
 516
 517         value = esdhc_read32(&regs->sysctl);
 518
 519         if (enable)
 520                 value |= SYSCTL_CKEN;
 521         else
 522                 value &= ~SYSCTL_CKEN;
 523
 524         esdhc_write32(&regs->sysctl, value);
 525
 526         time_out = 20;
 527         value = PRSSTAT_SDSTB;
 528         while (!(esdhc_read32(&regs->prsstat) & value)) {
 529                 if (time_out == 0) {
 530                         printf("fsl_esdhc: Internal clock never stabilised.\n");
 531                         break;
 532                 }
 533                 time_out--;
 534                 mdelay(1);
 535         }
 536 }
 537 #endif
 538
 539 static void esdhc_set_ios(struct mmc *mmc)
 540 {
 541         struct fsl_esdhc_cfg *cfg = mmc->priv;
 542         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 543
 544 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 545         /* Select to use peripheral clock */
 546         esdhc_clock_control(mmc, false);
 547         esdhc_setbits32(&regs->scr, ESDHCCTL_PCS);
 548         esdhc_clock_control(mmc, true);
 549 #endif
 550         /* Set the clock speed */
 551         set_sysctl(mmc, mmc->clock);
 552
 553         /* Set the bus width */
 554         esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
 555
 556         if (mmc->bus_width == 4)
 557                 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
 558         else if (mmc->bus_width == 8)
 559                 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
 560
 561 }
 562
 563 static int esdhc_init(struct mmc *mmc)
 564 {
 565         struct fsl_esdhc_cfg *cfg = mmc->priv;
 566         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 567         int timeout = 1000;
 568
 569         /* Reset the entire host controller */
 570         esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
 571
 572         /* Wait until the controller is available */
 573         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
 574                 udelay(1000);
 575
 576 #ifndef ARCH_MXC
 577         /* Enable cache snooping */
 578         esdhc_write32(&regs->scr, 0x00000040);
 579 #endif
 580
 581         esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
 582
 583         /* Set the initial clock speed */
 584         mmc_set_clock(mmc, 400000);
 585
 586         /* Disable the BRR and BWR bits in IRQSTAT */
 587         esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
 588
 589         /* Put the PROCTL reg back to the default */
 590         esdhc_write32(&regs->proctl, PROCTL_INIT);
 591
 592         /* Set timout to the maximum value */
 593         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
 594
 595 #ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
 596         esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
 597 #endif
 598
 599         return 0;
 600 }
 601
 602 static int esdhc_getcd(struct mmc *mmc)
 603 {
 604         struct fsl_esdhc_cfg *cfg = mmc->priv;
 605         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 606         int timeout = 1000;
 607
 608 #ifdef CONFIG_ESDHC_DETECT_QUIRK
 609         if (CONFIG_ESDHC_DETECT_QUIRK)
 610                 return 1;
 611 #endif
 612         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
 613                 udelay(1000);
 614
 615         return timeout > 0;
 616 }
 617
 618 static void esdhc_reset(struct fsl_esdhc *regs)
 619 {
 620         unsigned long timeout = 100; /* wait max 100 ms */
 621
 622         /* reset the controller */
 623         esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
 624
 625         /* hardware clears the bit when it is done */
 626         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
 627                 udelay(1000);
 628         if (!timeout)
 629                 printf("MMC/SD: Reset never completed.\n");
 630 }
 631
 632 static const struct mmc_ops esdhc_ops = {
 633         .send_cmd       = esdhc_send_cmd,
 634         .set_ios        = esdhc_set_ios,
 635         .init           = esdhc_init,
 636         .getcd          = esdhc_getcd,
 637 };
 638
 639 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 640 {
 641         struct fsl_esdhc *regs;
 642         struct mmc *mmc;
 643         u32 caps, voltage_caps;
 644
 645         if (!cfg)
 646                 return -1;
 647
 648         regs = (struct fsl_esdhc *)cfg->esdhc_base;
 649
 650         /* First reset the eSDHC controller */
 651         esdhc_reset(regs);
 652
 653         esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
 654                                 | SYSCTL_IPGEN | SYSCTL_CKEN);
 655
 656         writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
 657         memset(&cfg->cfg, 0, sizeof(cfg->cfg));
 658
 659         voltage_caps = 0;
 660         caps = esdhc_read32(&regs->hostcapblt);
 661
 662 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
 663         caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
 664                         ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
 665 #endif
 666
 667 /* T4240 host controller capabilities register should have VS33 bit */
 668 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 669         caps = caps | ESDHC_HOSTCAPBLT_VS33;
 670 #endif
 671
 672         if (caps & ESDHC_HOSTCAPBLT_VS18)
 673                 voltage_caps |= MMC_VDD_165_195;
 674         if (caps & ESDHC_HOSTCAPBLT_VS30)
 675                 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
 676         if (caps & ESDHC_HOSTCAPBLT_VS33)
 677                 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
 678
 679         cfg->cfg.name = "FSL_SDHC";
 680         cfg->cfg.ops = &esdhc_ops;
 681 #ifdef CONFIG_SYS_SD_VOLTAGE
 682         cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
 683 #else
 684         cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 685 #endif
 686         if ((cfg->cfg.voltages & voltage_caps) == 0) {
 687                 printf("voltage not supported by controller\n");
 688                 return -1;
 689         }
 690
 691         cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
 692 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
 693         cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz;
 694 #endif
 695
 696         if (cfg->max_bus_width > 0) {
 697                 if (cfg->max_bus_width < 8)
 698                         cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
 699                 if (cfg->max_bus_width < 4)
 700                         cfg->cfg.host_caps &= ~MMC_MODE_4BIT;
 701         }
 702
 703         if (caps & ESDHC_HOSTCAPBLT_HSS)
 704                 cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 705
 706 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
 707         if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
 708                 cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
 709 #endif
 710
 711         cfg->cfg.f_min = 400000;
 712         cfg->cfg.f_max = min(cfg->sdhc_clk, (u32)52000000);
 713
 714         cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 715
 716         mmc = mmc_create(&cfg->cfg, cfg);
 717         if (mmc == NULL)
 718                 return -1;
 719
 720         return 0;
 721 }
 722
 723 int fsl_esdhc_mmc_init(bd_t *bis)
 724 {
 725         struct fsl_esdhc_cfg *cfg;
 726
 727         cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
 728         cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
 729         cfg->sdhc_clk = gd->arch.sdhc_clk;
 730         return fsl_esdhc_initialize(bis, cfg);
 731 }
 732
 733 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
 734 void mmc_adapter_card_type_ident(void)
 735 {
 736         u8 card_id;
 737         u8 value;
 738
 739         card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
 740         gd->arch.sdhc_adapter = card_id;
 741
 742         switch (card_id) {
 743         case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
 744                 break;
 745         case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
 746                 break;
 747         case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
 748                 value = QIXIS_READ(brdcfg[5]);
 749                 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
 750                 QIXIS_WRITE(brdcfg[5], value);
 751                 break;
 752         case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
 753                 break;
 754         case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
 755                 break;
 756         case QIXIS_ESDHC_ADAPTER_TYPE_SD:
 757                 break;
 758         case QIXIS_ESDHC_NO_ADAPTER:
 759                 break;
 760         default:
 761                 break;
 762         }
 763 }
 764 #endif
 765
 766 #ifdef CONFIG_OF_LIBFDT
 767 void fdt_fixup_esdhc(void *blob, bd_t *bd)
 768 {
 769         const char *compat = "fsl,esdhc";
 770
 771 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
 772         if (!hwconfig("esdhc")) {
 773                 do_fixup_by_compat(blob, compat, "status", "disabled",
 774                                 8 + 1, 1);
 775                 return;
 776         }
 777 #endif
 778
 779 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 780         do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
 781                                gd->arch.sdhc_clk, 1);
 782 #else
 783         do_fixup_by_compat_u32(blob, compat, "clock-frequency",
 784                                gd->arch.sdhc_clk, 1);
 785 #endif
 786 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
 787         do_fixup_by_compat_u32(blob, compat, "adapter-type",
 788                                (u32)(gd->arch.sdhc_adapter), 1);
 789 #endif
 790         do_fixup_by_compat(blob, compat, "status", "okay",
 791                            4 + 1, 1);
 792 }
 793 #endif