drivers/mmc/fsl_esdhc.c

   1 /*
   2  * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
   3  * Andy Fleming
   4  *
   5  * Based vaguely on the pxa mmc code:
   6  * (C) Copyright 2003
   7  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <config.h>
  29 #include <common.h>
  30 #include <command.h>
  31 #include <hwconfig.h>
  32 #include <mmc.h>
  33 #include <part.h>
  34 #include <malloc.h>
  35 #include <mmc.h>
  36 #include <fsl_esdhc.h>
  37 #include <fdt_support.h>
  38 #include <asm/io.h>
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 struct fsl_esdhc {
  43         uint    dsaddr;
  44         uint    blkattr;
  45         uint    cmdarg;
  46         uint    xfertyp;
  47         uint    cmdrsp0;
  48         uint    cmdrsp1;
  49         uint    cmdrsp2;
  50         uint    cmdrsp3;
  51         uint    datport;
  52         uint    prsstat;
  53         uint    proctl;
  54         uint    sysctl;
  55         uint    irqstat;
  56         uint    irqstaten;
  57         uint    irqsigen;
  58         uint    autoc12err;
  59         uint    hostcapblt;
  60         uint    wml;
  61         uint    mixctrl;
  62         char    reserved1[4];
  63         uint    fevt;
  64         char    reserved2[168];
  65         uint    hostver;
  66         char    reserved3[780];
  67         uint    scr;
  68 };
  69
  70 /* Return the XFERTYP flags for a given command and data packet */
  71 uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
  72 {
  73         uint xfertyp = 0;
  74
  75         if (data) {
  76                 xfertyp |= XFERTYP_DPSEL;
  77 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  78                 xfertyp |= XFERTYP_DMAEN;
  79 #endif
  80                 if (data->blocks > 1) {
  81                         xfertyp |= XFERTYP_MSBSEL;
  82                         xfertyp |= XFERTYP_BCEN;
  83 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
  84                         xfertyp |= XFERTYP_AC12EN;
  85 #endif
  86                 }
  87
  88                 if (data->flags & MMC_DATA_READ)
  89                         xfertyp |= XFERTYP_DTDSEL;
  90         }
  91
  92         if (cmd->resp_type & MMC_RSP_CRC)
  93                 xfertyp |= XFERTYP_CCCEN;
  94         if (cmd->resp_type & MMC_RSP_OPCODE)
  95                 xfertyp |= XFERTYP_CICEN;
  96         if (cmd->resp_type & MMC_RSP_136)
  97                 xfertyp |= XFERTYP_RSPTYP_136;
  98         else if (cmd->resp_type & MMC_RSP_BUSY)
  99                 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
 100         else if (cmd->resp_type & MMC_RSP_PRESENT)
 101                 xfertyp |= XFERTYP_RSPTYP_48;
 102
 103 #ifdef CONFIG_MX53
 104         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 105                 xfertyp |= XFERTYP_CMDTYP_ABORT;
 106 #endif
 107         return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
 108 }
 109
 110 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
 111 /*
 112  * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
 113  */
 114 static void
 115 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
 116 {
 117         struct fsl_esdhc_cfg *cfg = mmc->priv;
 118         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 119         uint blocks;
 120         char *buffer;
 121         uint databuf;
 122         uint size;
 123         uint irqstat;
 124         uint timeout;
 125
 126         if (data->flags & MMC_DATA_READ) {
 127                 blocks = data->blocks;
 128                 buffer = data->dest;
 129                 while (blocks) {
 130                         timeout = PIO_TIMEOUT;
 131                         size = data->blocksize;
 132                         irqstat = esdhc_read32(&regs->irqstat);
 133                         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
 134                                 && --timeout);
 135                         if (timeout <= 0) {
 136                                 printf("\nData Read Failed in PIO Mode.");
 137                                 return;
 138                         }
 139                         while (size && (!(irqstat & IRQSTAT_TC))) {
 140                                 udelay(100); /* Wait before last byte transfer complete */
 141                                 irqstat = esdhc_read32(&regs->irqstat);
 142                                 databuf = in_le32(&regs->datport);
 143                                 *((uint *)buffer) = databuf;
 144                                 buffer += 4;
 145                                 size -= 4;
 146                         }
 147                         blocks--;
 148                 }
 149         } else {
 150                 blocks = data->blocks;
 151                 buffer = (char *)data->src;
 152                 while (blocks) {
 153                         timeout = PIO_TIMEOUT;
 154                         size = data->blocksize;
 155                         irqstat = esdhc_read32(&regs->irqstat);
 156                         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
 157                                 && --timeout);
 158                         if (timeout <= 0) {
 159                                 printf("\nData Write Failed in PIO Mode.");
 160                                 return;
 161                         }
 162                         while (size && (!(irqstat & IRQSTAT_TC))) {
 163                                 udelay(100); /* Wait before last byte transfer complete */
 164                                 databuf = *((uint *)buffer);
 165                                 buffer += 4;
 166                                 size -= 4;
 167                                 irqstat = esdhc_read32(&regs->irqstat);
 168                                 out_le32(&regs->datport, databuf);
 169                         }
 170                         blocks--;
 171                 }
 172         }
 173 }
 174 #endif
 175
 176 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 177 {
 178         int timeout;
 179         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 180         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 181 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 182         uint wml_value;
 183
 184         wml_value = data->blocksize/4;
 185
 186         if (data->flags & MMC_DATA_READ) {
 187                 if (wml_value > WML_RD_WML_MAX)
 188                         wml_value = WML_RD_WML_MAX_VAL;
 189
 190                 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
 191                 esdhc_write32(&regs->dsaddr, (u32)data->dest);
 192         } else {
 193                 if (wml_value > WML_WR_WML_MAX)
 194                         wml_value = WML_WR_WML_MAX_VAL;
 195                 if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
 196                         printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
 197                         return TIMEOUT;
 198                 }
 199
 200                 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
 201                                         wml_value << 16);
 202                 esdhc_write32(&regs->dsaddr, (u32)data->src);
 203         }
 204 #else   /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
 205         if (!(data->flags & MMC_DATA_READ)) {
 206                 if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
 207                         printf("\nThe SD card is locked. "
 208                                 "Can not write to a locked card.\n\n");
 209                         return TIMEOUT;
 210                 }
 211                 esdhc_write32(&regs->dsaddr, (u32)data->src);
 212         } else
 213                 esdhc_write32(&regs->dsaddr, (u32)data->dest);
 214 #endif  /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
 215
 216         esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
 217
 218         /* Calculate the timeout period for data transactions */
 219         /*
 220          * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
 221          * 2)Timeout period should be minimum 0.250sec as per SD Card spec
 222          *  So, Number of SD Clock cycles for 0.25sec should be minimum
 223          *              (SD Clock/sec * 0.25 sec) SD Clock cycles
 224          *              = (mmc->tran_speed * 1/4) SD Clock cycles
 225          * As 1) >=  2)
 226          * => (2^(timeout+13)) >= mmc->tran_speed * 1/4
 227          * Taking log2 both the sides
 228          * => timeout + 13 >= log2(mmc->tran_speed/4)
 229          * Rounding up to next power of 2
 230          * => timeout + 13 = log2(mmc->tran_speed/4) + 1
 231          * => timeout + 13 = fls(mmc->tran_speed/4)
 232          */
 233         timeout = fls(mmc->tran_speed/4);
 234         timeout -= 13;
 235
 236         if (timeout > 14)
 237                 timeout = 14;
 238
 239         if (timeout < 0)
 240                 timeout = 0;
 241
 242 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
 243         if ((timeout == 4) || (timeout == 8) || (timeout == 12))
 244                 timeout++;
 245 #endif
 246
 247         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
 248
 249         return 0;
 250 }
 251
 252
 253 /*
 254  * Sends a command out on the bus.  Takes the mmc pointer,
 255  * a command pointer, and an optional data pointer.
 256  */
 257 static int
 258 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 259 {
 260         uint    xfertyp;
 261         uint    irqstat;
 262         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 263         volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 264
 265 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
 266         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 267                 return 0;
 268 #endif
 269
 270         esdhc_write32(&regs->irqstat, -1);
 271
 272         sync();
 273
 274         /* Wait for the bus to be idle */
 275         while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
 276                         (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
 277                 ;
 278
 279         while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
 280                 ;
 281
 282         /* Wait at least 8 SD clock cycles before the next command */
 283         /*
 284          * Note: This is way more than 8 cycles, but 1ms seems to
 285          * resolve timing issues with some cards
 286          */
 287         udelay(1000);
 288
 289         /* Set up for a data transfer if we have one */
 290         if (data) {
 291                 int err;
 292
 293                 err = esdhc_setup_data(mmc, data);
 294                 if(err)
 295                         return err;
 296         }
 297
 298         /* Figure out the transfer arguments */
 299         xfertyp = esdhc_xfertyp(cmd, data);
 300
 301         /* Send the command */
 302         esdhc_write32(&regs->cmdarg, cmd->cmdarg);
 303 #if defined(CONFIG_FSL_USDHC)
 304         esdhc_write32(&regs->mixctrl,
 305         (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));
 306         esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
 307 #else
 308         esdhc_write32(&regs->xfertyp, xfertyp);
 309 #endif
 310         /* Wait for the command to complete */
 311         while (!(esdhc_read32(&regs->irqstat) & IRQSTAT_CC))
 312                 ;
 313
 314         irqstat = esdhc_read32(&regs->irqstat);
 315         esdhc_write32(&regs->irqstat, irqstat);
 316
 317         if (irqstat & CMD_ERR)
 318                 return COMM_ERR;
 319
 320         if (irqstat & IRQSTAT_CTOE)
 321                 return TIMEOUT;
 322
 323         /* Copy the response to the response buffer */
 324         if (cmd->resp_type & MMC_RSP_136) {
 325                 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
 326
 327                 cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
 328                 cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
 329                 cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
 330                 cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
 331                 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
 332                 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
 333                 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
 334                 cmd->response[3] = (cmdrsp0 << 8);
 335         } else
 336                 cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
 337
 338         /* Wait until all of the blocks are transferred */
 339         if (data) {
 340 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
 341                 esdhc_pio_read_write(mmc, data);
 342 #else
 343                 do {
 344                         irqstat = esdhc_read32(&regs->irqstat);
 345
 346                         if (irqstat & IRQSTAT_DTOE)
 347                                 return TIMEOUT;
 348
 349                         if (irqstat & DATA_ERR)
 350                                 return COMM_ERR;
 351                 } while (!(irqstat & IRQSTAT_TC) &&
 352                                 (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA));
 353 #endif
 354         }
 355
 356         esdhc_write32(&regs->irqstat, -1);
 357
 358         return 0;
 359 }
 360
 361 void set_sysctl(struct mmc *mmc, uint clock)
 362 {
 363         int sdhc_clk = gd->sdhc_clk;
 364         int div, pre_div;
 365         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 366         volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 367         uint clk;
 368
 369         if (clock < mmc->f_min)
 370                 clock = mmc->f_min;
 371
 372         if (sdhc_clk / 16 > clock) {
 373                 for (pre_div = 2; pre_div < 256; pre_div *= 2)
 374                         if ((sdhc_clk / pre_div) <= (clock * 16))
 375                                 break;
 376         } else
 377                 pre_div = 2;
 378
 379         for (div = 1; div <= 16; div++)
 380                 if ((sdhc_clk / (div * pre_div)) <= clock)
 381                         break;
 382
 383         pre_div >>= 1;
 384         div -= 1;
 385
 386         clk = (pre_div << 8) | (div << 4);
 387
 388         esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
 389
 390         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
 391
 392         udelay(10000);
 393
 394         clk = SYSCTL_PEREN | SYSCTL_CKEN;
 395
 396         esdhc_setbits32(&regs->sysctl, clk);
 397 }
 398
 399 static void esdhc_set_ios(struct mmc *mmc)
 400 {
 401         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 402         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 403
 404         /* Set the clock speed */
 405         set_sysctl(mmc, mmc->clock);
 406
 407         /* Set the bus width */
 408         esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
 409
 410         if (mmc->bus_width == 4)
 411                 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
 412         else if (mmc->bus_width == 8)
 413                 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
 414
 415 }
 416
 417 static int esdhc_init(struct mmc *mmc)
 418 {
 419         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 420         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 421         int timeout = 1000;
 422
 423         /* Reset the entire host controller */
 424         esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
 425
 426         /* Wait until the controller is available */
 427         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
 428                 udelay(1000);
 429
 430         /* Enable cache snooping */
 431         if (cfg && !cfg->no_snoop)
 432                 esdhc_write32(&regs->scr, 0x00000040);
 433
 434         esdhc_write32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
 435
 436         /* Set the initial clock speed */
 437         mmc_set_clock(mmc, 400000);
 438
 439         /* Disable the BRR and BWR bits in IRQSTAT */
 440         esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
 441
 442         /* Put the PROCTL reg back to the default */
 443         esdhc_write32(&regs->proctl, PROCTL_INIT);
 444
 445         /* Set timout to the maximum value */
 446         esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
 447
 448         return 0;
 449 }
 450
 451 static int esdhc_getcd(struct mmc *mmc)
 452 {
 453         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 454         struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 455         int timeout = 1000;
 456
 457         while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
 458                 udelay(1000);
 459
 460         return timeout > 0;
 461 }
 462
 463 static void esdhc_reset(struct fsl_esdhc *regs)
 464 {
 465         unsigned long timeout = 100; /* wait max 100 ms */
 466
 467         /* reset the controller */
 468         esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
 469
 470         /* hardware clears the bit when it is done */
 471         while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
 472                 udelay(1000);
 473         if (!timeout)
 474                 printf("MMC/SD: Reset never completed.\n");
 475 }
 476
 477 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 478 {
 479         struct fsl_esdhc *regs;
 480         struct mmc *mmc;
 481         u32 caps, voltage_caps;
 482
 483         if (!cfg)
 484                 return -1;
 485
 486         mmc = malloc(sizeof(struct mmc));
 487
 488         sprintf(mmc->name, "FSL_SDHC");
 489         regs = (struct fsl_esdhc *)cfg->esdhc_base;
 490
 491         /* First reset the eSDHC controller */
 492         esdhc_reset(regs);
 493
 494         mmc->priv = cfg;
 495         mmc->send_cmd = esdhc_send_cmd;
 496         mmc->set_ios = esdhc_set_ios;
 497         mmc->init = esdhc_init;
 498         mmc->getcd = esdhc_getcd;
 499
 500         voltage_caps = 0;
 501         caps = regs->hostcapblt;
 502
 503 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
 504         caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
 505                         ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
 506 #endif
 507         if (caps & ESDHC_HOSTCAPBLT_VS18)
 508                 voltage_caps |= MMC_VDD_165_195;
 509         if (caps & ESDHC_HOSTCAPBLT_VS30)
 510                 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
 511         if (caps & ESDHC_HOSTCAPBLT_VS33)
 512                 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
 513
 514 #ifdef CONFIG_SYS_SD_VOLTAGE
 515         mmc->voltages = CONFIG_SYS_SD_VOLTAGE;
 516 #else
 517         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 518 #endif
 519         if ((mmc->voltages & voltage_caps) == 0) {
 520                 printf("voltage not supported by controller\n");
 521                 return -1;
 522         }
 523
 524         mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
 525
 526         if (caps & ESDHC_HOSTCAPBLT_HSS)
 527                 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 528
 529         mmc->f_min = 400000;
 530         mmc->f_max = MIN(gd->sdhc_clk, 52000000);
 531
 532         mmc->b_max = 0;
 533         mmc_register(mmc);
 534
 535         return 0;
 536 }
 537
 538 int fsl_esdhc_mmc_init(bd_t *bis)
 539 {
 540         struct fsl_esdhc_cfg *cfg;
 541
 542         cfg = malloc(sizeof(struct fsl_esdhc_cfg));
 543         memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
 544         cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
 545         return fsl_esdhc_initialize(bis, cfg);
 546 }
 547
 548 #ifdef CONFIG_OF_LIBFDT
 549 void fdt_fixup_esdhc(void *blob, bd_t *bd)
 550 {
 551         const char *compat = "fsl,esdhc";
 552
 553 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
 554         if (!hwconfig("esdhc")) {
 555                 do_fixup_by_compat(blob, compat, "status", "disabled",
 556                                 8 + 1, 1);
 557                 return;
 558         }
 559 #endif
 560
 561         do_fixup_by_compat_u32(blob, compat, "clock-frequency",
 562                                gd->sdhc_clk, 1);
 563
 564         do_fixup_by_compat(blob, compat, "status", "okay",
 565                            4 + 1, 1);
 566 }
 567 #endif