2 * Faraday MMC/SD Host Controller
4 * (C) Copyright 2010 Faraday Technology
5 * Dante Su <dantesu@faraday-tech.com>
7 * SPDX-License-Identifier: GPL-2.0+
16 #include <linux/errno.h>
17 #include <asm/byteorder.h>
18 #include <faraday/ftsdc010.h>
19 #include "ftsdc010_mci.h"
21 #define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */
22 #define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */
24 static inline int ftsdc010_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*mmc_cmd
)
26 struct ftsdc010_chip
*chip
= mmc
->priv
;
27 struct ftsdc010_mmc __iomem
*regs
= chip
->regs
;
30 uint32_t cmd
= FTSDC010_CMD_IDX(mmc_cmd
->cmdidx
);
31 uint32_t arg
= mmc_cmd
->cmdarg
;
32 uint32_t flags
= mmc_cmd
->resp_type
;
34 cmd
|= FTSDC010_CMD_CMD_EN
;
37 cmd
|= FTSDC010_CMD_APP_CMD
;
41 if (flags
& MMC_RSP_PRESENT
)
42 cmd
|= FTSDC010_CMD_NEED_RSP
;
44 if (flags
& MMC_RSP_136
)
45 cmd
|= FTSDC010_CMD_LONG_RSP
;
47 writel(FTSDC010_STATUS_RSP_MASK
| FTSDC010_STATUS_CMD_SEND
,
49 writel(arg
, ®s
->argu
);
50 writel(cmd
, ®s
->cmd
);
52 if (!(flags
& (MMC_RSP_PRESENT
| MMC_RSP_136
))) {
53 for (ts
= get_timer(0); get_timer(ts
) < CFG_CMD_TIMEOUT
; ) {
54 if (readl(®s
->status
) & FTSDC010_STATUS_CMD_SEND
) {
55 writel(FTSDC010_STATUS_CMD_SEND
, ®s
->clr
);
62 for (ts
= get_timer(0); get_timer(ts
) < CFG_CMD_TIMEOUT
; ) {
63 st
= readl(®s
->status
);
64 writel(st
& FTSDC010_STATUS_RSP_MASK
, ®s
->clr
);
65 if (st
& FTSDC010_STATUS_RSP_MASK
)
68 if (st
& FTSDC010_STATUS_RSP_CRC_OK
) {
69 if (flags
& MMC_RSP_136
) {
70 mmc_cmd
->response
[0] = readl(®s
->rsp3
);
71 mmc_cmd
->response
[1] = readl(®s
->rsp2
);
72 mmc_cmd
->response
[2] = readl(®s
->rsp1
);
73 mmc_cmd
->response
[3] = readl(®s
->rsp0
);
75 mmc_cmd
->response
[0] = readl(®s
->rsp0
);
79 debug("ftsdc010: rsp err (cmd=%d, st=0x%x)\n",
85 debug("ftsdc010: cmd timeout (op code=%d)\n",
87 } else if (mmc_cmd
->cmdidx
== MMC_CMD_APP_CMD
) {
94 static void ftsdc010_clkset(struct mmc
*mmc
, uint32_t rate
)
96 struct ftsdc010_chip
*chip
= mmc
->priv
;
97 struct ftsdc010_mmc __iomem
*regs
= chip
->regs
;
100 for (div
= 0; div
< 0x7f; ++div
) {
101 if (rate
>= chip
->sclk
/ (2 * (div
+ 1)))
104 chip
->rate
= chip
->sclk
/ (2 * (div
+ 1));
106 writel(FTSDC010_CCR_CLK_DIV(div
), ®s
->ccr
);
109 setbits_le32(®s
->ccr
, FTSDC010_CCR_CLK_SD
);
111 if (chip
->rate
> 25000000)
112 setbits_le32(®s
->ccr
, FTSDC010_CCR_CLK_HISPD
);
114 clrbits_le32(®s
->ccr
, FTSDC010_CCR_CLK_HISPD
);
118 static int ftsdc010_wait(struct ftsdc010_mmc __iomem
*regs
, uint32_t mask
)
120 int ret
= -ETIMEDOUT
;
121 uint32_t st
, timeout
= 10000000;
123 st
= readl(®s
->status
);
126 writel(st
& mask
, ®s
->clr
);
132 debug("ftsdc010: wait st(0x%x) timeout\n", mask
);
142 static int ftsdc010_request(struct udevice
*dev
, struct mmc_cmd
*cmd
,
143 struct mmc_data
*data
)
145 struct mmc
*mmc
= mmc_get_mmc_dev(dev
);
147 static int ftsdc010_request(struct mmc
*mmc
, struct mmc_cmd
*cmd
,
148 struct mmc_data
*data
)
151 int ret
= -EOPNOTSUPP
;
153 struct ftsdc010_chip
*chip
= mmc
->priv
;
154 struct ftsdc010_mmc __iomem
*regs
= chip
->regs
;
156 if (data
&& (data
->flags
& MMC_DATA_WRITE
) && chip
->wprot
) {
157 printf("ftsdc010: the card is write protected!\n");
164 len
= data
->blocksize
* data
->blocks
;
166 /* 1. data disable + fifo reset */
168 #ifdef CONFIG_FTSDC010_SDIO
169 dcr
|= FTSDC010_DCR_FIFO_RST
;
171 writel(dcr
, ®s
->dcr
);
173 /* 2. clear status register */
174 writel(FTSDC010_STATUS_DATA_MASK
| FTSDC010_STATUS_FIFO_URUN
175 | FTSDC010_STATUS_FIFO_ORUN
, ®s
->clr
);
177 /* 3. data timeout (1 sec) */
178 writel(chip
->rate
, ®s
->dtr
);
180 /* 4. data length (bytes) */
181 writel(len
, ®s
->dlr
);
184 dcr
= (ffs(data
->blocksize
) - 1) | FTSDC010_DCR_DATA_EN
;
185 if (data
->flags
& MMC_DATA_WRITE
)
186 dcr
|= FTSDC010_DCR_DATA_WRITE
;
187 writel(dcr
, ®s
->dcr
);
190 ret
= ftsdc010_send_cmd(mmc
, cmd
);
192 printf("ftsdc010: CMD%d failed\n", cmd
->cmdidx
);
199 if (data
->flags
& MMC_DATA_WRITE
) {
200 const uint8_t *buf
= (const uint8_t *)data
->src
;
205 /* wait for tx ready */
206 ret
= ftsdc010_wait(regs
, FTSDC010_STATUS_FIFO_URUN
);
210 /* write bytes to ftsdc010 */
211 for (wlen
= 0; wlen
< len
&& wlen
< chip
->fifo
; ) {
212 writel(*(uint32_t *)buf
, ®s
->dwr
);
221 uint8_t *buf
= (uint8_t *)data
->dest
;
226 /* wait for rx ready */
227 ret
= ftsdc010_wait(regs
, FTSDC010_STATUS_FIFO_ORUN
);
231 /* fetch bytes from ftsdc010 */
232 for (rlen
= 0; rlen
< len
&& rlen
< chip
->fifo
; ) {
233 *(uint32_t *)buf
= readl(®s
->dwr
);
244 ret
= ftsdc010_wait(regs
,
245 FTSDC010_STATUS_DATA_END
| FTSDC010_STATUS_DATA_CRC_OK
);
252 static int ftsdc010_set_ios(struct udevice
*dev
)
254 struct mmc
*mmc
= mmc_get_mmc_dev(dev
);
256 static int ftsdc010_set_ios(struct mmc
*mmc
)
259 struct ftsdc010_chip
*chip
= mmc
->priv
;
260 struct ftsdc010_mmc __iomem
*regs
= chip
->regs
;
262 ftsdc010_clkset(mmc
, mmc
->clock
);
264 clrbits_le32(®s
->bwr
, FTSDC010_BWR_MODE_MASK
);
265 switch (mmc
->bus_width
) {
267 setbits_le32(®s
->bwr
, FTSDC010_BWR_MODE_4BIT
);
270 setbits_le32(®s
->bwr
, FTSDC010_BWR_MODE_8BIT
);
273 setbits_le32(®s
->bwr
, FTSDC010_BWR_MODE_1BIT
);
281 static int ftsdc010_get_cd(struct udevice
*dev
)
283 struct mmc
*mmc
= mmc_get_mmc_dev(dev
);
285 static int ftsdc010_get_cd(struct mmc
*mmc
)
288 struct ftsdc010_chip
*chip
= mmc
->priv
;
289 struct ftsdc010_mmc __iomem
*regs
= chip
->regs
;
290 return !(readl(®s
->status
) & FTSDC010_STATUS_CARD_DETECT
);
294 static int ftsdc010_get_wp(struct udevice
*dev
)
296 struct mmc
*mmc
= mmc_get_mmc_dev(dev
);
298 static int ftsdc010_get_wp(struct mmc
*mmc
)
301 struct ftsdc010_chip
*chip
= mmc
->priv
;
302 struct ftsdc010_mmc __iomem
*regs
= chip
->regs
;
303 if (readl(®s
->status
) & FTSDC010_STATUS_WRITE_PROT
) {
304 printf("ftsdc010: write protected\n");
311 static int ftsdc010_init(struct mmc
*mmc
)
313 struct ftsdc010_chip
*chip
= mmc
->priv
;
314 struct ftsdc010_mmc __iomem
*regs
= chip
->regs
;
317 chip
->fifo
= (readl(®s
->feature
) & 0xff) << 2;
320 writel(FTSDC010_CMD_SDC_RST
, ®s
->cmd
);
321 for (ts
= get_timer(0); get_timer(ts
) < CFG_RST_TIMEOUT
; ) {
322 if (readl(®s
->cmd
) & FTSDC010_CMD_SDC_RST
)
326 if (readl(®s
->cmd
) & FTSDC010_CMD_SDC_RST
) {
327 printf("ftsdc010: reset failed\n");
331 /* 2. enter low speed mode (400k card detection) */
332 ftsdc010_clkset(mmc
, 400000);
334 /* 3. interrupt disabled */
335 writel(0, ®s
->int_mask
);
341 int ftsdc010_probe(struct udevice
*dev
)
343 struct mmc
*mmc
= mmc_get_mmc_dev(dev
);
344 return ftsdc010_init(mmc
);
347 const struct dm_mmc_ops dm_ftsdc010_ops
= {
348 .send_cmd
= ftsdc010_request
,
349 .set_ios
= ftsdc010_set_ios
,
350 .get_cd
= ftsdc010_get_cd
,
351 .get_wp
= ftsdc010_get_wp
,
355 static const struct mmc_ops ftsdc010_ops
= {
356 .send_cmd
= ftsdc010_request
,
357 .set_ios
= ftsdc010_set_ios
,
358 .getcd
= ftsdc010_get_cd
,
359 .getwp
= ftsdc010_get_wp
,
360 .init
= ftsdc010_init
,
364 void ftsdc_setup_cfg(struct mmc_config
*cfg
, const char *name
, int buswidth
,
365 uint caps
, u32 max_clk
, u32 min_clk
)
368 cfg
->f_min
= min_clk
;
369 cfg
->f_max
= max_clk
;
370 cfg
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
;
371 cfg
->host_caps
= caps
;
373 cfg
->host_caps
|= MMC_MODE_8BIT
;
374 cfg
->host_caps
&= ~MMC_MODE_4BIT
;
376 cfg
->host_caps
|= MMC_MODE_4BIT
;
377 cfg
->host_caps
&= ~MMC_MODE_8BIT
;
379 cfg
->part_type
= PART_TYPE_DOS
;
380 cfg
->b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
383 void set_bus_width(struct ftsdc010_mmc __iomem
*regs
, struct mmc_config
*cfg
)
385 switch (readl(®s
->bwr
) & FTSDC010_BWR_CAPS_MASK
) {
386 case FTSDC010_BWR_CAPS_4BIT
:
387 cfg
->host_caps
|= MMC_MODE_4BIT
;
389 case FTSDC010_BWR_CAPS_8BIT
:
390 cfg
->host_caps
|= MMC_MODE_4BIT
| MMC_MODE_8BIT
;
398 int ftsdc010_bind(struct udevice
*dev
, struct mmc
*mmc
, struct mmc_config
*cfg
)
400 return mmc_bind(dev
, mmc
, cfg
);
404 int ftsdc010_mmc_init(int devid
)
407 struct ftsdc010_chip
*chip
;
408 struct ftsdc010_mmc __iomem
*regs
;
409 #ifdef CONFIG_FTSDC010_BASE_LIST
410 uint32_t base_list
[] = CONFIG_FTSDC010_BASE_LIST
;
412 if (devid
< 0 || devid
>= ARRAY_SIZE(base_list
))
414 regs
= (void __iomem
*)base_list
[devid
];
416 regs
= (void __iomem
*)(CONFIG_FTSDC010_BASE
+ (devid
<< 20));
419 chip
= malloc(sizeof(struct ftsdc010_chip
));
422 memset(chip
, 0, sizeof(struct ftsdc010_chip
));
425 #ifdef CONFIG_SYS_CLK_FREQ
426 chip
->sclk
= CONFIG_SYS_CLK_FREQ
;
428 chip
->sclk
= clk_get_rate("SDC");
431 chip
->cfg
.name
= "ftsdc010";
432 #ifndef CONFIG_DM_MMC
433 chip
->cfg
.ops
= &ftsdc010_ops
;
435 chip
->cfg
.host_caps
= MMC_MODE_HS
| MMC_MODE_HS_52MHz
;
436 set_bus_width(regs
, &chip
->cfg
);
437 chip
->cfg
.voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
;
438 chip
->cfg
.f_max
= chip
->sclk
/ 2;
439 chip
->cfg
.f_min
= chip
->sclk
/ 0x100;
441 chip
->cfg
.part_type
= PART_TYPE_DOS
;
442 chip
->cfg
.b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
444 mmc
= mmc_create(&chip
->cfg
, chip
);