3 * Rob Emanuele <rob@emanuele.us>
4 * Reinhard Meyer, EMK Elektronik <reinhard.meyer@emk-elektronik.de>
7 * Copyright (C) 2004-2006 Atmel Corporation
9 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/errno.h>
18 #include <asm/byteorder.h>
19 #include <asm/arch/clk.h>
20 #include <asm/arch/hardware.h>
21 #include "atmel_mci.h"
23 #ifndef CONFIG_SYS_MMC_CLK_OD
24 # define CONFIG_SYS_MMC_CLK_OD 150000
27 #define MMC_DEFAULT_BLKLEN 512
29 #if defined(CONFIG_ATMEL_MCI_PORTB)
35 static int initialized
= 0;
37 /* Read Atmel MCI IP version */
38 static unsigned int atmel_mci_get_version(struct atmel_mci
*mci
)
40 return readl(&mci
->version
) & 0x00000fff;
44 * Print command and status:
46 * - always when DEBUG is defined
49 static void dump_cmd(u32 cmdr
, u32 arg
, u32 status
, const char* msg
)
51 printf("gen_atmel_mci: CMDR %08x (%2u) ARGR %08x (SR: %08x) %s\n",
52 cmdr
, cmdr
&0x3F, arg
, status
, msg
);
55 /* Setup for MCI Clock and Block Size */
56 static void mci_set_mode(struct mmc
*mmc
, u32 hz
, u32 blklen
)
58 atmel_mci_t
*mci
= (atmel_mci_t
*)mmc
->priv
;
59 u32 bus_hz
= get_mci_clk_rate();
62 debug("mci: bus_hz is %u, setting clock %u Hz, block size %u\n",
65 /* find lowest clkdiv yielding a rate <= than requested */
66 for (clkdiv
=0; clkdiv
<255; clkdiv
++) {
67 if ((bus_hz
/ (clkdiv
+1) / 2) <= hz
)
71 printf("mci: setting clock %u Hz, block size %u\n",
72 (bus_hz
/ (clkdiv
+1)) / 2, blklen
);
75 /* On some platforms RDPROOF and WRPROOF are ignored */
76 writel((MMCI_BF(CLKDIV
, clkdiv
)
77 | MMCI_BF(BLKLEN
, blklen
)
79 | MMCI_BIT(WRPROOF
)), &mci
->mr
);
81 * On some new platforms BLKLEN in mci->mr is ignored.
82 * Should use the BLKLEN in the block register.
84 writel(MMCI_BF(BLKLEN
, blklen
), &mci
->blkr
);
88 /* Return the CMDR with flags for a given command and data packet */
89 static u32
mci_encode_cmd(
90 struct mmc_cmd
*cmd
, struct mmc_data
*data
, u32
* error_flags
)
94 /* Default Flags for Errors */
95 *error_flags
|= (MMCI_BIT(DTOE
) | MMCI_BIT(RDIRE
) | MMCI_BIT(RENDE
) |
96 MMCI_BIT(RINDE
) | MMCI_BIT(RTOE
));
98 /* Default Flags for the Command */
99 cmdr
|= MMCI_BIT(MAXLAT
);
102 cmdr
|= MMCI_BF(TRCMD
, 1);
103 if (data
->blocks
> 1)
104 cmdr
|= MMCI_BF(TRTYP
, 1);
105 if (data
->flags
& MMC_DATA_READ
)
106 cmdr
|= MMCI_BIT(TRDIR
);
109 if (cmd
->resp_type
& MMC_RSP_CRC
)
110 *error_flags
|= MMCI_BIT(RCRCE
);
111 if (cmd
->resp_type
& MMC_RSP_136
)
112 cmdr
|= MMCI_BF(RSPTYP
, 2);
113 else if (cmd
->resp_type
& MMC_RSP_BUSY
)
114 cmdr
|= MMCI_BF(RSPTYP
, 3);
115 else if (cmd
->resp_type
& MMC_RSP_PRESENT
)
116 cmdr
|= MMCI_BF(RSPTYP
, 1);
118 return cmdr
| MMCI_BF(CMDNB
, cmd
->cmdidx
);
121 /* Entered into function pointer in mci_send_cmd */
122 static u32
mci_data_read(atmel_mci_t
*mci
, u32
* data
, u32 error_flags
)
127 status
= readl(&mci
->sr
);
128 if (status
& (error_flags
| MMCI_BIT(OVRE
)))
130 } while (!(status
& MMCI_BIT(RXRDY
)));
132 if (status
& MMCI_BIT(RXRDY
)) {
133 *data
= readl(&mci
->rdr
);
140 /* Entered into function pointer in mci_send_cmd */
141 static u32
mci_data_write(atmel_mci_t
*mci
, u32
* data
, u32 error_flags
)
146 status
= readl(&mci
->sr
);
147 if (status
& (error_flags
| MMCI_BIT(UNRE
)))
149 } while (!(status
& MMCI_BIT(TXRDY
)));
151 if (status
& MMCI_BIT(TXRDY
)) {
152 writel(*data
, &mci
->tdr
);
160 * Entered into mmc structure during driver init
162 * Sends a command out on the bus and deals with the block data.
163 * Takes the mmc pointer, a command pointer, and an optional data pointer.
166 mci_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*cmd
, struct mmc_data
*data
)
168 atmel_mci_t
*mci
= (atmel_mci_t
*)mmc
->priv
;
174 puts ("MCI not initialized!\n");
178 /* Figure out the transfer arguments */
179 cmdr
= mci_encode_cmd(cmd
, data
, &error_flags
);
181 /* For multi blocks read/write, set the block register */
182 if ((cmd
->cmdidx
== MMC_CMD_READ_MULTIPLE_BLOCK
)
183 || (cmd
->cmdidx
== MMC_CMD_WRITE_MULTIPLE_BLOCK
))
184 writel(data
->blocks
| MMCI_BF(BLKLEN
, mmc
->read_bl_len
),
187 /* Send the command */
188 writel(cmd
->cmdarg
, &mci
->argr
);
189 writel(cmdr
, &mci
->cmdr
);
192 dump_cmd(cmdr
, cmd
->cmdarg
, 0, "DEBUG");
195 /* Wait for the command to complete */
196 while (!((status
= readl(&mci
->sr
)) & MMCI_BIT(CMDRDY
)));
198 if ((status
& error_flags
) & MMCI_BIT(RTOE
)) {
199 dump_cmd(cmdr
, cmd
->cmdarg
, status
, "Command Time Out");
201 } else if (status
& error_flags
) {
202 dump_cmd(cmdr
, cmd
->cmdarg
, status
, "Command Failed");
206 /* Copy the response to the response buffer */
207 if (cmd
->resp_type
& MMC_RSP_136
) {
208 cmd
->response
[0] = readl(&mci
->rspr
);
209 cmd
->response
[1] = readl(&mci
->rspr1
);
210 cmd
->response
[2] = readl(&mci
->rspr2
);
211 cmd
->response
[3] = readl(&mci
->rspr3
);
213 cmd
->response
[0] = readl(&mci
->rspr
);
215 /* transfer all of the blocks */
217 u32 word_count
, block_count
;
219 u32 sys_blocksize
, dummy
, i
;
221 (atmel_mci_t
*mci
, u32
* data
, u32 error_flags
);
223 if (data
->flags
& MMC_DATA_READ
) {
224 mci_data_op
= mci_data_read
;
225 sys_blocksize
= mmc
->read_bl_len
;
226 ioptr
= (u32
*)data
->dest
;
228 mci_data_op
= mci_data_write
;
229 sys_blocksize
= mmc
->write_bl_len
;
230 ioptr
= (u32
*)data
->src
;
234 for (block_count
= 0;
235 block_count
< data
->blocks
&& !status
;
239 status
= mci_data_op(mci
, ioptr
, error_flags
);
242 } while (!status
&& word_count
< (data
->blocksize
/4));
244 if (data
->flags
& MMC_DATA_READ
)
246 printf("Read Data:\n");
247 print_buffer(0, data
->dest
, 1,
252 if (!status
&& word_count
< (sys_blocksize
/ 4))
253 printf("filling rest of block...\n");
255 /* fill the rest of a full block */
256 while (!status
&& word_count
< (sys_blocksize
/ 4)) {
257 status
= mci_data_op(mci
, &dummy
,
262 dump_cmd(cmdr
, cmd
->cmdarg
, status
,
263 "Data Transfer Failed");
268 /* Wait for Transfer End */
271 status
= readl(&mci
->sr
);
273 if (status
& error_flags
) {
274 dump_cmd(cmdr
, cmd
->cmdarg
, status
,
279 } while ((status
& MMCI_BIT(DTIP
)) && i
< 10000);
280 if (status
& MMCI_BIT(DTIP
)) {
281 dump_cmd(cmdr
, cmd
->cmdarg
, status
,
282 "XFER DTIP never unset, ignoring");
289 /* Entered into mmc structure during driver init */
290 static void mci_set_ios(struct mmc
*mmc
)
292 atmel_mci_t
*mci
= (atmel_mci_t
*)mmc
->priv
;
293 int bus_width
= mmc
->bus_width
;
294 unsigned int version
= atmel_mci_get_version(mci
);
297 /* Set the clock speed */
298 mci_set_mode(mmc
, mmc
->clock
, MMC_DEFAULT_BLKLEN
);
301 * set the bus width and select slot for this interface
302 * there is no capability for multiple slots on the same interface yet
304 if ((version
& 0xf00) >= 0x300) {
317 writel(busw
<< 6 | MMCI_BF(SCDSEL
, MCI_BUS
), &mci
->sdcr
);
319 busw
= (bus_width
== 4) ? 1 : 0;
321 writel(busw
<< 7 | MMCI_BF(SCDSEL
, MCI_BUS
), &mci
->sdcr
);
325 /* Entered into mmc structure during driver init */
326 static int mci_init(struct mmc
*mmc
)
328 atmel_mci_t
*mci
= (atmel_mci_t
*)mmc
->priv
;
330 /* Initialize controller */
331 writel(MMCI_BIT(SWRST
), &mci
->cr
); /* soft reset */
332 writel(MMCI_BIT(PWSDIS
), &mci
->cr
); /* disable power save */
333 writel(MMCI_BIT(MCIEN
), &mci
->cr
); /* enable mci */
334 writel(MMCI_BF(SCDSEL
, MCI_BUS
), &mci
->sdcr
); /* select port */
336 /* This delay can be optimized, but stick with max value */
337 writel(0x7f, &mci
->dtor
);
338 /* Disable Interrupts */
339 writel(~0UL, &mci
->idr
);
341 /* Set default clocks and blocklen */
342 mci_set_mode(mmc
, CONFIG_SYS_MMC_CLK_OD
, MMC_DEFAULT_BLKLEN
);
347 static const struct mmc_ops atmel_mci_ops
= {
348 .send_cmd
= mci_send_cmd
,
349 .set_ios
= mci_set_ios
,
354 * This is the only exported function
356 * Call it with the MCI register base address
358 int atmel_mci_init(void *regs
)
360 struct mmc
*mmc
= malloc(sizeof(struct mmc
));
361 struct atmel_mci
*mci
;
362 unsigned int version
;
367 strcpy(mmc
->name
, "mci");
369 mmc
->ops
= &atmel_mci_ops
;
371 /* need to be able to pass these in on a board by board basis */
372 mmc
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
;
373 mci
= (struct atmel_mci
*)mmc
->priv
;
374 version
= atmel_mci_get_version(mci
);
375 if ((version
& 0xf00) >= 0x300)
376 mmc
->host_caps
= MMC_MODE_8BIT
;
378 mmc
->host_caps
|= MMC_MODE_4BIT
;
381 * min and max frequencies determined by
382 * max and min of clock divider
384 mmc
->f_min
= get_mci_clk_rate() / (2*256);
385 mmc
->f_max
= get_mci_clk_rate() / (2*1);