2 * Copyright 2008, Freescale Semiconductor, Inc
5 * Based vaguely on the Linux code
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <dm/device-internal.h>
18 #include <power/regulator.h>
21 #include <linux/list.h>
23 #include "mmc_private.h"
25 static const unsigned int sd_au_size
[] = {
26 0, SZ_16K
/ 512, SZ_32K
/ 512,
27 SZ_64K
/ 512, SZ_128K
/ 512, SZ_256K
/ 512,
28 SZ_512K
/ 512, SZ_1M
/ 512, SZ_2M
/ 512,
29 SZ_4M
/ 512, SZ_8M
/ 512, (SZ_8M
+ SZ_4M
) / 512,
30 SZ_16M
/ 512, (SZ_16M
+ SZ_8M
) / 512, SZ_32M
/ 512, SZ_64M
/ 512,
33 #if CONFIG_IS_ENABLED(MMC_TINY)
34 static struct mmc mmc_static
;
35 struct mmc
*find_mmc_device(int dev_num
)
40 void mmc_do_preinit(void)
42 struct mmc
*m
= &mmc_static
;
43 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
44 mmc_set_preinit(m
, 1);
50 struct blk_desc
*mmc_get_blk_desc(struct mmc
*mmc
)
52 return &mmc
->block_dev
;
56 #if !CONFIG_IS_ENABLED(DM_MMC)
57 __weak
int board_mmc_getwp(struct mmc
*mmc
)
62 int mmc_getwp(struct mmc
*mmc
)
66 wp
= board_mmc_getwp(mmc
);
69 if (mmc
->cfg
->ops
->getwp
)
70 wp
= mmc
->cfg
->ops
->getwp(mmc
);
78 __weak
int board_mmc_getcd(struct mmc
*mmc
)
84 #ifdef CONFIG_MMC_TRACE
85 void mmmc_trace_before_send(struct mmc
*mmc
, struct mmc_cmd
*cmd
)
87 printf("CMD_SEND:%d\n", cmd
->cmdidx
);
88 printf("\t\tARG\t\t\t 0x%08X\n", cmd
->cmdarg
);
91 void mmmc_trace_after_send(struct mmc
*mmc
, struct mmc_cmd
*cmd
, int ret
)
97 printf("\t\tRET\t\t\t %d\n", ret
);
99 switch (cmd
->resp_type
) {
101 printf("\t\tMMC_RSP_NONE\n");
104 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
108 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
112 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
114 printf("\t\t \t\t 0x%08X \n",
116 printf("\t\t \t\t 0x%08X \n",
118 printf("\t\t \t\t 0x%08X \n",
121 printf("\t\t\t\t\tDUMPING DATA\n");
122 for (i
= 0; i
< 4; i
++) {
124 printf("\t\t\t\t\t%03d - ", i
*4);
125 ptr
= (u8
*)&cmd
->response
[i
];
127 for (j
= 0; j
< 4; j
++)
128 printf("%02X ", *ptr
--);
133 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
137 printf("\t\tERROR MMC rsp not supported\n");
143 void mmc_trace_state(struct mmc
*mmc
, struct mmc_cmd
*cmd
)
147 status
= (cmd
->response
[0] & MMC_STATUS_CURR_STATE
) >> 9;
148 printf("CURR STATE:%d\n", status
);
152 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
153 const char *mmc_mode_name(enum bus_mode mode
)
155 static const char *const names
[] = {
156 [MMC_LEGACY
] = "MMC legacy",
157 [SD_LEGACY
] = "SD Legacy",
158 [MMC_HS
] = "MMC High Speed (26MHz)",
159 [SD_HS
] = "SD High Speed (50MHz)",
160 [UHS_SDR12
] = "UHS SDR12 (25MHz)",
161 [UHS_SDR25
] = "UHS SDR25 (50MHz)",
162 [UHS_SDR50
] = "UHS SDR50 (100MHz)",
163 [UHS_SDR104
] = "UHS SDR104 (208MHz)",
164 [UHS_DDR50
] = "UHS DDR50 (50MHz)",
165 [MMC_HS_52
] = "MMC High Speed (52MHz)",
166 [MMC_DDR_52
] = "MMC DDR52 (52MHz)",
167 [MMC_HS_200
] = "HS200 (200MHz)",
170 if (mode
>= MMC_MODES_END
)
171 return "Unknown mode";
177 static int mmc_select_mode(struct mmc
*mmc
, enum bus_mode mode
)
179 mmc
->selected_mode
= mode
;
180 debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode
),
181 mmc
->tran_speed
/ 1000000);
185 #if !CONFIG_IS_ENABLED(DM_MMC)
186 int mmc_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*cmd
, struct mmc_data
*data
)
190 mmmc_trace_before_send(mmc
, cmd
);
191 ret
= mmc
->cfg
->ops
->send_cmd(mmc
, cmd
, data
);
192 mmmc_trace_after_send(mmc
, cmd
, ret
);
198 int mmc_send_status(struct mmc
*mmc
, int timeout
)
201 int err
, retries
= 5;
203 cmd
.cmdidx
= MMC_CMD_SEND_STATUS
;
204 cmd
.resp_type
= MMC_RSP_R1
;
205 if (!mmc_host_is_spi(mmc
))
206 cmd
.cmdarg
= mmc
->rca
<< 16;
209 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
211 if ((cmd
.response
[0] & MMC_STATUS_RDY_FOR_DATA
) &&
212 (cmd
.response
[0] & MMC_STATUS_CURR_STATE
) !=
215 else if (cmd
.response
[0] & MMC_STATUS_MASK
) {
216 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
217 printf("Status Error: 0x%08X\n",
222 } else if (--retries
< 0)
231 mmc_trace_state(mmc
, &cmd
);
233 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
234 printf("Timeout waiting card ready\n");
242 int mmc_set_blocklen(struct mmc
*mmc
, int len
)
249 cmd
.cmdidx
= MMC_CMD_SET_BLOCKLEN
;
250 cmd
.resp_type
= MMC_RSP_R1
;
253 return mmc_send_cmd(mmc
, &cmd
, NULL
);
256 static int mmc_read_blocks(struct mmc
*mmc
, void *dst
, lbaint_t start
,
260 struct mmc_data data
;
263 cmd
.cmdidx
= MMC_CMD_READ_MULTIPLE_BLOCK
;
265 cmd
.cmdidx
= MMC_CMD_READ_SINGLE_BLOCK
;
267 if (mmc
->high_capacity
)
270 cmd
.cmdarg
= start
* mmc
->read_bl_len
;
272 cmd
.resp_type
= MMC_RSP_R1
;
275 data
.blocks
= blkcnt
;
276 data
.blocksize
= mmc
->read_bl_len
;
277 data
.flags
= MMC_DATA_READ
;
279 if (mmc_send_cmd(mmc
, &cmd
, &data
))
283 cmd
.cmdidx
= MMC_CMD_STOP_TRANSMISSION
;
285 cmd
.resp_type
= MMC_RSP_R1b
;
286 if (mmc_send_cmd(mmc
, &cmd
, NULL
)) {
287 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
288 printf("mmc fail to send stop cmd\n");
297 #if CONFIG_IS_ENABLED(BLK)
298 ulong
mmc_bread(struct udevice
*dev
, lbaint_t start
, lbaint_t blkcnt
, void *dst
)
300 ulong
mmc_bread(struct blk_desc
*block_dev
, lbaint_t start
, lbaint_t blkcnt
,
304 #if CONFIG_IS_ENABLED(BLK)
305 struct blk_desc
*block_dev
= dev_get_uclass_platdata(dev
);
307 int dev_num
= block_dev
->devnum
;
309 lbaint_t cur
, blocks_todo
= blkcnt
;
314 struct mmc
*mmc
= find_mmc_device(dev_num
);
318 if (CONFIG_IS_ENABLED(MMC_TINY
))
319 err
= mmc_switch_part(mmc
, block_dev
->hwpart
);
321 err
= blk_dselect_hwpart(block_dev
, block_dev
->hwpart
);
326 if ((start
+ blkcnt
) > block_dev
->lba
) {
327 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
328 printf("MMC: block number 0x" LBAF
" exceeds max(0x" LBAF
")\n",
329 start
+ blkcnt
, block_dev
->lba
);
334 if (mmc_set_blocklen(mmc
, mmc
->read_bl_len
)) {
335 debug("%s: Failed to set blocklen\n", __func__
);
340 cur
= (blocks_todo
> mmc
->cfg
->b_max
) ?
341 mmc
->cfg
->b_max
: blocks_todo
;
342 if (mmc_read_blocks(mmc
, dst
, start
, cur
) != cur
) {
343 debug("%s: Failed to read blocks\n", __func__
);
348 dst
+= cur
* mmc
->read_bl_len
;
349 } while (blocks_todo
> 0);
354 static int mmc_go_idle(struct mmc
*mmc
)
361 cmd
.cmdidx
= MMC_CMD_GO_IDLE_STATE
;
363 cmd
.resp_type
= MMC_RSP_NONE
;
365 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
375 static int sd_send_op_cond(struct mmc
*mmc
)
382 cmd
.cmdidx
= MMC_CMD_APP_CMD
;
383 cmd
.resp_type
= MMC_RSP_R1
;
386 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
391 cmd
.cmdidx
= SD_CMD_APP_SEND_OP_COND
;
392 cmd
.resp_type
= MMC_RSP_R3
;
395 * Most cards do not answer if some reserved bits
396 * in the ocr are set. However, Some controller
397 * can set bit 7 (reserved for low voltages), but
398 * how to manage low voltages SD card is not yet
401 cmd
.cmdarg
= mmc_host_is_spi(mmc
) ? 0 :
402 (mmc
->cfg
->voltages
& 0xff8000);
404 if (mmc
->version
== SD_VERSION_2
)
405 cmd
.cmdarg
|= OCR_HCS
;
407 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
412 if (cmd
.response
[0] & OCR_BUSY
)
421 if (mmc
->version
!= SD_VERSION_2
)
422 mmc
->version
= SD_VERSION_1_0
;
424 if (mmc_host_is_spi(mmc
)) { /* read OCR for spi */
425 cmd
.cmdidx
= MMC_CMD_SPI_READ_OCR
;
426 cmd
.resp_type
= MMC_RSP_R3
;
429 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
435 mmc
->ocr
= cmd
.response
[0];
437 mmc
->high_capacity
= ((mmc
->ocr
& OCR_HCS
) == OCR_HCS
);
443 static int mmc_send_op_cond_iter(struct mmc
*mmc
, int use_arg
)
448 cmd
.cmdidx
= MMC_CMD_SEND_OP_COND
;
449 cmd
.resp_type
= MMC_RSP_R3
;
451 if (use_arg
&& !mmc_host_is_spi(mmc
))
452 cmd
.cmdarg
= OCR_HCS
|
453 (mmc
->cfg
->voltages
&
454 (mmc
->ocr
& OCR_VOLTAGE_MASK
)) |
455 (mmc
->ocr
& OCR_ACCESS_MODE
);
457 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
460 mmc
->ocr
= cmd
.response
[0];
464 static int mmc_send_op_cond(struct mmc
*mmc
)
468 /* Some cards seem to need this */
471 /* Asking to the card its capabilities */
472 for (i
= 0; i
< 2; i
++) {
473 err
= mmc_send_op_cond_iter(mmc
, i
!= 0);
477 /* exit if not busy (flag seems to be inverted) */
478 if (mmc
->ocr
& OCR_BUSY
)
481 mmc
->op_cond_pending
= 1;
485 static int mmc_complete_op_cond(struct mmc
*mmc
)
492 mmc
->op_cond_pending
= 0;
493 if (!(mmc
->ocr
& OCR_BUSY
)) {
494 /* Some cards seem to need this */
497 start
= get_timer(0);
499 err
= mmc_send_op_cond_iter(mmc
, 1);
502 if (mmc
->ocr
& OCR_BUSY
)
504 if (get_timer(start
) > timeout
)
510 if (mmc_host_is_spi(mmc
)) { /* read OCR for spi */
511 cmd
.cmdidx
= MMC_CMD_SPI_READ_OCR
;
512 cmd
.resp_type
= MMC_RSP_R3
;
515 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
520 mmc
->ocr
= cmd
.response
[0];
523 mmc
->version
= MMC_VERSION_UNKNOWN
;
525 mmc
->high_capacity
= ((mmc
->ocr
& OCR_HCS
) == OCR_HCS
);
532 static int mmc_send_ext_csd(struct mmc
*mmc
, u8
*ext_csd
)
535 struct mmc_data data
;
538 /* Get the Card Status Register */
539 cmd
.cmdidx
= MMC_CMD_SEND_EXT_CSD
;
540 cmd
.resp_type
= MMC_RSP_R1
;
543 data
.dest
= (char *)ext_csd
;
545 data
.blocksize
= MMC_MAX_BLOCK_LEN
;
546 data
.flags
= MMC_DATA_READ
;
548 err
= mmc_send_cmd(mmc
, &cmd
, &data
);
553 int mmc_switch(struct mmc
*mmc
, u8 set
, u8 index
, u8 value
)
560 cmd
.cmdidx
= MMC_CMD_SWITCH
;
561 cmd
.resp_type
= MMC_RSP_R1b
;
562 cmd
.cmdarg
= (MMC_SWITCH_MODE_WRITE_BYTE
<< 24) |
566 while (retries
> 0) {
567 ret
= mmc_send_cmd(mmc
, &cmd
, NULL
);
569 /* Waiting for the ready status */
571 ret
= mmc_send_status(mmc
, timeout
);
582 static int mmc_change_freq(struct mmc
*mmc
)
584 ALLOC_CACHE_ALIGN_BUFFER(u8
, ext_csd
, MMC_MAX_BLOCK_LEN
);
590 if (mmc_host_is_spi(mmc
))
593 /* Only version 4 supports high-speed */
594 if (mmc
->version
< MMC_VERSION_4
)
597 mmc
->card_caps
|= MMC_MODE_4BIT
| MMC_MODE_8BIT
;
599 err
= mmc_send_ext_csd(mmc
, ext_csd
);
604 cardtype
= ext_csd
[EXT_CSD_CARD_TYPE
] & 0xf;
606 err
= mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
, EXT_CSD_HS_TIMING
, 1);
611 /* Now check to see that it worked */
612 err
= mmc_send_ext_csd(mmc
, ext_csd
);
617 /* No high-speed support */
618 if (!ext_csd
[EXT_CSD_HS_TIMING
])
621 /* High Speed is set, there are two types: 52MHz and 26MHz */
622 if (cardtype
& EXT_CSD_CARD_TYPE_52
) {
623 if (cardtype
& EXT_CSD_CARD_TYPE_DDR_1_8V
)
624 mmc
->card_caps
|= MMC_MODE_DDR_52MHz
;
625 mmc
->card_caps
|= MMC_MODE_HS_52MHz
| MMC_MODE_HS
;
627 mmc
->card_caps
|= MMC_MODE_HS
;
633 static int mmc_set_capacity(struct mmc
*mmc
, int part_num
)
637 mmc
->capacity
= mmc
->capacity_user
;
641 mmc
->capacity
= mmc
->capacity_boot
;
644 mmc
->capacity
= mmc
->capacity_rpmb
;
650 mmc
->capacity
= mmc
->capacity_gp
[part_num
- 4];
656 mmc_get_blk_desc(mmc
)->lba
= lldiv(mmc
->capacity
, mmc
->read_bl_len
);
661 int mmc_switch_part(struct mmc
*mmc
, unsigned int part_num
)
665 ret
= mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
, EXT_CSD_PART_CONF
,
666 (mmc
->part_config
& ~PART_ACCESS_MASK
)
667 | (part_num
& PART_ACCESS_MASK
));
670 * Set the capacity if the switch succeeded or was intended
671 * to return to representing the raw device.
673 if ((ret
== 0) || ((ret
== -ENODEV
) && (part_num
== 0))) {
674 ret
= mmc_set_capacity(mmc
, part_num
);
675 mmc_get_blk_desc(mmc
)->hwpart
= part_num
;
681 int mmc_hwpart_config(struct mmc
*mmc
,
682 const struct mmc_hwpart_conf
*conf
,
683 enum mmc_hwpart_conf_mode mode
)
689 u32 max_enh_size_mult
;
690 u32 tot_enh_size_mult
= 0;
693 ALLOC_CACHE_ALIGN_BUFFER(u8
, ext_csd
, MMC_MAX_BLOCK_LEN
);
695 if (mode
< MMC_HWPART_CONF_CHECK
|| mode
> MMC_HWPART_CONF_COMPLETE
)
698 if (IS_SD(mmc
) || (mmc
->version
< MMC_VERSION_4_41
)) {
699 printf("eMMC >= 4.4 required for enhanced user data area\n");
703 if (!(mmc
->part_support
& PART_SUPPORT
)) {
704 printf("Card does not support partitioning\n");
708 if (!mmc
->hc_wp_grp_size
) {
709 printf("Card does not define HC WP group size\n");
713 /* check partition alignment and total enhanced size */
714 if (conf
->user
.enh_size
) {
715 if (conf
->user
.enh_size
% mmc
->hc_wp_grp_size
||
716 conf
->user
.enh_start
% mmc
->hc_wp_grp_size
) {
717 printf("User data enhanced area not HC WP group "
721 part_attrs
|= EXT_CSD_ENH_USR
;
722 enh_size_mult
= conf
->user
.enh_size
/ mmc
->hc_wp_grp_size
;
723 if (mmc
->high_capacity
) {
724 enh_start_addr
= conf
->user
.enh_start
;
726 enh_start_addr
= (conf
->user
.enh_start
<< 9);
732 tot_enh_size_mult
+= enh_size_mult
;
734 for (pidx
= 0; pidx
< 4; pidx
++) {
735 if (conf
->gp_part
[pidx
].size
% mmc
->hc_wp_grp_size
) {
736 printf("GP%i partition not HC WP group size "
737 "aligned\n", pidx
+1);
740 gp_size_mult
[pidx
] = conf
->gp_part
[pidx
].size
/ mmc
->hc_wp_grp_size
;
741 if (conf
->gp_part
[pidx
].size
&& conf
->gp_part
[pidx
].enhanced
) {
742 part_attrs
|= EXT_CSD_ENH_GP(pidx
);
743 tot_enh_size_mult
+= gp_size_mult
[pidx
];
747 if (part_attrs
&& ! (mmc
->part_support
& ENHNCD_SUPPORT
)) {
748 printf("Card does not support enhanced attribute\n");
752 err
= mmc_send_ext_csd(mmc
, ext_csd
);
757 (ext_csd
[EXT_CSD_MAX_ENH_SIZE_MULT
+2] << 16) +
758 (ext_csd
[EXT_CSD_MAX_ENH_SIZE_MULT
+1] << 8) +
759 ext_csd
[EXT_CSD_MAX_ENH_SIZE_MULT
];
760 if (tot_enh_size_mult
> max_enh_size_mult
) {
761 printf("Total enhanced size exceeds maximum (%u > %u)\n",
762 tot_enh_size_mult
, max_enh_size_mult
);
766 /* The default value of EXT_CSD_WR_REL_SET is device
767 * dependent, the values can only be changed if the
768 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
769 * changed only once and before partitioning is completed. */
770 wr_rel_set
= ext_csd
[EXT_CSD_WR_REL_SET
];
771 if (conf
->user
.wr_rel_change
) {
772 if (conf
->user
.wr_rel_set
)
773 wr_rel_set
|= EXT_CSD_WR_DATA_REL_USR
;
775 wr_rel_set
&= ~EXT_CSD_WR_DATA_REL_USR
;
777 for (pidx
= 0; pidx
< 4; pidx
++) {
778 if (conf
->gp_part
[pidx
].wr_rel_change
) {
779 if (conf
->gp_part
[pidx
].wr_rel_set
)
780 wr_rel_set
|= EXT_CSD_WR_DATA_REL_GP(pidx
);
782 wr_rel_set
&= ~EXT_CSD_WR_DATA_REL_GP(pidx
);
786 if (wr_rel_set
!= ext_csd
[EXT_CSD_WR_REL_SET
] &&
787 !(ext_csd
[EXT_CSD_WR_REL_PARAM
] & EXT_CSD_HS_CTRL_REL
)) {
788 puts("Card does not support host controlled partition write "
789 "reliability settings\n");
793 if (ext_csd
[EXT_CSD_PARTITION_SETTING
] &
794 EXT_CSD_PARTITION_SETTING_COMPLETED
) {
795 printf("Card already partitioned\n");
799 if (mode
== MMC_HWPART_CONF_CHECK
)
802 /* Partitioning requires high-capacity size definitions */
803 if (!(ext_csd
[EXT_CSD_ERASE_GROUP_DEF
] & 0x01)) {
804 err
= mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
,
805 EXT_CSD_ERASE_GROUP_DEF
, 1);
810 ext_csd
[EXT_CSD_ERASE_GROUP_DEF
] = 1;
812 /* update erase group size to be high-capacity */
813 mmc
->erase_grp_size
=
814 ext_csd
[EXT_CSD_HC_ERASE_GRP_SIZE
] * 1024;
818 /* all OK, write the configuration */
819 for (i
= 0; i
< 4; i
++) {
820 err
= mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
,
821 EXT_CSD_ENH_START_ADDR
+i
,
822 (enh_start_addr
>> (i
*8)) & 0xFF);
826 for (i
= 0; i
< 3; i
++) {
827 err
= mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
,
828 EXT_CSD_ENH_SIZE_MULT
+i
,
829 (enh_size_mult
>> (i
*8)) & 0xFF);
833 for (pidx
= 0; pidx
< 4; pidx
++) {
834 for (i
= 0; i
< 3; i
++) {
835 err
= mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
,
836 EXT_CSD_GP_SIZE_MULT
+pidx
*3+i
,
837 (gp_size_mult
[pidx
] >> (i
*8)) & 0xFF);
842 err
= mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
,
843 EXT_CSD_PARTITIONS_ATTRIBUTE
, part_attrs
);
847 if (mode
== MMC_HWPART_CONF_SET
)
850 /* The WR_REL_SET is a write-once register but shall be
851 * written before setting PART_SETTING_COMPLETED. As it is
852 * write-once we can only write it when completing the
854 if (wr_rel_set
!= ext_csd
[EXT_CSD_WR_REL_SET
]) {
855 err
= mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
,
856 EXT_CSD_WR_REL_SET
, wr_rel_set
);
861 /* Setting PART_SETTING_COMPLETED confirms the partition
862 * configuration but it only becomes effective after power
863 * cycle, so we do not adjust the partition related settings
864 * in the mmc struct. */
866 err
= mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
,
867 EXT_CSD_PARTITION_SETTING
,
868 EXT_CSD_PARTITION_SETTING_COMPLETED
);
875 #if !CONFIG_IS_ENABLED(DM_MMC)
876 int mmc_getcd(struct mmc
*mmc
)
880 cd
= board_mmc_getcd(mmc
);
883 if (mmc
->cfg
->ops
->getcd
)
884 cd
= mmc
->cfg
->ops
->getcd(mmc
);
893 static int sd_switch(struct mmc
*mmc
, int mode
, int group
, u8 value
, u8
*resp
)
896 struct mmc_data data
;
898 /* Switch the frequency */
899 cmd
.cmdidx
= SD_CMD_SWITCH_FUNC
;
900 cmd
.resp_type
= MMC_RSP_R1
;
901 cmd
.cmdarg
= (mode
<< 31) | 0xffffff;
902 cmd
.cmdarg
&= ~(0xf << (group
* 4));
903 cmd
.cmdarg
|= value
<< (group
* 4);
905 data
.dest
= (char *)resp
;
908 data
.flags
= MMC_DATA_READ
;
910 return mmc_send_cmd(mmc
, &cmd
, &data
);
914 static int sd_change_freq(struct mmc
*mmc
)
918 ALLOC_CACHE_ALIGN_BUFFER(__be32
, scr
, 2);
919 ALLOC_CACHE_ALIGN_BUFFER(__be32
, switch_status
, 16);
920 struct mmc_data data
;
925 if (mmc_host_is_spi(mmc
))
928 /* Read the SCR to find out if this card supports higher speeds */
929 cmd
.cmdidx
= MMC_CMD_APP_CMD
;
930 cmd
.resp_type
= MMC_RSP_R1
;
931 cmd
.cmdarg
= mmc
->rca
<< 16;
933 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
938 cmd
.cmdidx
= SD_CMD_APP_SEND_SCR
;
939 cmd
.resp_type
= MMC_RSP_R1
;
945 data
.dest
= (char *)scr
;
948 data
.flags
= MMC_DATA_READ
;
950 err
= mmc_send_cmd(mmc
, &cmd
, &data
);
959 mmc
->scr
[0] = __be32_to_cpu(scr
[0]);
960 mmc
->scr
[1] = __be32_to_cpu(scr
[1]);
962 switch ((mmc
->scr
[0] >> 24) & 0xf) {
964 mmc
->version
= SD_VERSION_1_0
;
967 mmc
->version
= SD_VERSION_1_10
;
970 mmc
->version
= SD_VERSION_2
;
971 if ((mmc
->scr
[0] >> 15) & 0x1)
972 mmc
->version
= SD_VERSION_3
;
975 mmc
->version
= SD_VERSION_1_0
;
979 if (mmc
->scr
[0] & SD_DATA_4BIT
)
980 mmc
->card_caps
|= MMC_MODE_4BIT
;
982 /* Version 1.0 doesn't support switching */
983 if (mmc
->version
== SD_VERSION_1_0
)
988 err
= sd_switch(mmc
, SD_SWITCH_CHECK
, 0, 1,
989 (u8
*)switch_status
);
994 /* The high-speed function is busy. Try again */
995 if (!(__be32_to_cpu(switch_status
[7]) & SD_HIGHSPEED_BUSY
))
999 /* If high-speed isn't supported, we return */
1000 if (!(__be32_to_cpu(switch_status
[3]) & SD_HIGHSPEED_SUPPORTED
))
1004 * If the host doesn't support SD_HIGHSPEED, do not switch card to
1005 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
1006 * This can avoid furthur problem when the card runs in different
1007 * mode between the host.
1009 if (!((mmc
->cfg
->host_caps
& MMC_MODE_HS_52MHz
) &&
1010 (mmc
->cfg
->host_caps
& MMC_MODE_HS
)))
1013 err
= sd_switch(mmc
, SD_SWITCH_SWITCH
, 0, 1, (u8
*)switch_status
);
1018 if ((__be32_to_cpu(switch_status
[4]) & 0x0f000000) == 0x01000000)
1019 mmc
->card_caps
|= MMC_MODE_HS
;
1024 static int sd_read_ssr(struct mmc
*mmc
)
1028 ALLOC_CACHE_ALIGN_BUFFER(uint
, ssr
, 16);
1029 struct mmc_data data
;
1031 unsigned int au
, eo
, et
, es
;
1033 cmd
.cmdidx
= MMC_CMD_APP_CMD
;
1034 cmd
.resp_type
= MMC_RSP_R1
;
1035 cmd
.cmdarg
= mmc
->rca
<< 16;
1037 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
1041 cmd
.cmdidx
= SD_CMD_APP_SD_STATUS
;
1042 cmd
.resp_type
= MMC_RSP_R1
;
1046 data
.dest
= (char *)ssr
;
1047 data
.blocksize
= 64;
1049 data
.flags
= MMC_DATA_READ
;
1051 err
= mmc_send_cmd(mmc
, &cmd
, &data
);
1059 for (i
= 0; i
< 16; i
++)
1060 ssr
[i
] = be32_to_cpu(ssr
[i
]);
1062 au
= (ssr
[2] >> 12) & 0xF;
1063 if ((au
<= 9) || (mmc
->version
== SD_VERSION_3
)) {
1064 mmc
->ssr
.au
= sd_au_size
[au
];
1065 es
= (ssr
[3] >> 24) & 0xFF;
1066 es
|= (ssr
[2] & 0xFF) << 8;
1067 et
= (ssr
[3] >> 18) & 0x3F;
1069 eo
= (ssr
[3] >> 16) & 0x3;
1070 mmc
->ssr
.erase_timeout
= (et
* 1000) / es
;
1071 mmc
->ssr
.erase_offset
= eo
* 1000;
1074 debug("Invalid Allocation Unit Size.\n");
1080 /* frequency bases */
1081 /* divided by 10 to be nice to platforms without floating point */
1082 static const int fbase
[] = {
1089 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1090 * to platforms without floating point.
1092 static const u8 multipliers
[] = {
1111 #if !CONFIG_IS_ENABLED(DM_MMC)
1112 static void mmc_set_ios(struct mmc
*mmc
)
1114 if (mmc
->cfg
->ops
->set_ios
)
1115 mmc
->cfg
->ops
->set_ios(mmc
);
1119 void mmc_set_clock(struct mmc
*mmc
, uint clock
)
1121 if (clock
> mmc
->cfg
->f_max
)
1122 clock
= mmc
->cfg
->f_max
;
1124 if (clock
< mmc
->cfg
->f_min
)
1125 clock
= mmc
->cfg
->f_min
;
1132 static void mmc_set_bus_width(struct mmc
*mmc
, uint width
)
1134 mmc
->bus_width
= width
;
1139 static int sd_select_bus_freq_width(struct mmc
*mmc
)
1144 err
= sd_change_freq(mmc
);
1148 /* Restrict card's capabilities by what the host can do */
1149 mmc
->card_caps
&= mmc
->cfg
->host_caps
;
1151 if (mmc
->card_caps
& MMC_MODE_4BIT
) {
1152 cmd
.cmdidx
= MMC_CMD_APP_CMD
;
1153 cmd
.resp_type
= MMC_RSP_R1
;
1154 cmd
.cmdarg
= mmc
->rca
<< 16;
1156 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
1160 cmd
.cmdidx
= SD_CMD_APP_SET_BUS_WIDTH
;
1161 cmd
.resp_type
= MMC_RSP_R1
;
1163 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
1167 mmc_set_bus_width(mmc
, 4);
1170 err
= sd_read_ssr(mmc
);
1174 if (mmc
->card_caps
& MMC_MODE_HS
) {
1175 mmc_select_mode(mmc
, SD_HS
);
1176 mmc
->tran_speed
= 50000000;
1178 mmc_select_mode(mmc
, SD_LEGACY
);
1179 mmc
->tran_speed
= 25000000;
1186 * read the compare the part of ext csd that is constant.
1187 * This can be used to check that the transfer is working
1190 static int mmc_read_and_compare_ext_csd(struct mmc
*mmc
)
1193 const u8
*ext_csd
= mmc
->ext_csd
;
1194 ALLOC_CACHE_ALIGN_BUFFER(u8
, test_csd
, MMC_MAX_BLOCK_LEN
);
1196 err
= mmc_send_ext_csd(mmc
, test_csd
);
1200 /* Only compare read only fields */
1201 if (ext_csd
[EXT_CSD_PARTITIONING_SUPPORT
]
1202 == test_csd
[EXT_CSD_PARTITIONING_SUPPORT
] &&
1203 ext_csd
[EXT_CSD_HC_WP_GRP_SIZE
]
1204 == test_csd
[EXT_CSD_HC_WP_GRP_SIZE
] &&
1205 ext_csd
[EXT_CSD_REV
]
1206 == test_csd
[EXT_CSD_REV
] &&
1207 ext_csd
[EXT_CSD_HC_ERASE_GRP_SIZE
]
1208 == test_csd
[EXT_CSD_HC_ERASE_GRP_SIZE
] &&
1209 memcmp(&ext_csd
[EXT_CSD_SEC_CNT
],
1210 &test_csd
[EXT_CSD_SEC_CNT
], 4) == 0)
1216 static int mmc_select_bus_freq_width(struct mmc
*mmc
)
1218 /* An array of possible bus widths in order of preference */
1219 static const unsigned int ext_csd_bits
[] = {
1220 EXT_CSD_DDR_BUS_WIDTH_8
,
1221 EXT_CSD_DDR_BUS_WIDTH_4
,
1222 EXT_CSD_BUS_WIDTH_8
,
1223 EXT_CSD_BUS_WIDTH_4
,
1224 EXT_CSD_BUS_WIDTH_1
,
1226 /* An array to map CSD bus widths to host cap bits */
1227 static const unsigned int ext_to_hostcaps
[] = {
1228 [EXT_CSD_DDR_BUS_WIDTH_4
] =
1229 MMC_MODE_DDR_52MHz
| MMC_MODE_4BIT
,
1230 [EXT_CSD_DDR_BUS_WIDTH_8
] =
1231 MMC_MODE_DDR_52MHz
| MMC_MODE_8BIT
,
1232 [EXT_CSD_BUS_WIDTH_4
] = MMC_MODE_4BIT
,
1233 [EXT_CSD_BUS_WIDTH_8
] = MMC_MODE_8BIT
,
1235 /* An array to map chosen bus width to an integer */
1236 static const unsigned int widths
[] = {
1242 err
= mmc_change_freq(mmc
);
1246 /* Restrict card's capabilities by what the host can do */
1247 mmc
->card_caps
&= mmc
->cfg
->host_caps
;
1249 /* Only version 4 of MMC supports wider bus widths */
1250 if (mmc
->version
< MMC_VERSION_4
)
1253 if (!mmc
->ext_csd
) {
1254 debug("No ext_csd found!\n"); /* this should enver happen */
1258 for (idx
= 0; idx
< ARRAY_SIZE(ext_csd_bits
); idx
++) {
1259 unsigned int extw
= ext_csd_bits
[idx
];
1260 unsigned int caps
= ext_to_hostcaps
[extw
];
1262 * If the bus width is still not changed,
1263 * don't try to set the default again.
1264 * Otherwise, recover from switch attempts
1265 * by switching to 1-bit bus width.
1267 if (extw
== EXT_CSD_BUS_WIDTH_1
&&
1268 mmc
->bus_width
== 1) {
1274 * Check to make sure the card and controller support
1275 * these capabilities
1277 if ((mmc
->card_caps
& caps
) != caps
)
1280 err
= mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
,
1281 EXT_CSD_BUS_WIDTH
, extw
);
1286 mmc
->ddr_mode
= (caps
& MMC_MODE_DDR_52MHz
) ? 1 : 0;
1287 mmc_set_bus_width(mmc
, widths
[idx
]);
1289 err
= mmc_read_and_compare_ext_csd(mmc
);
1297 if (mmc
->card_caps
& MMC_MODE_HS_52MHz
) {
1299 mmc_select_mode(mmc
, MMC_DDR_52
);
1301 mmc_select_mode(mmc
, MMC_HS_52
);
1302 mmc
->tran_speed
= 52000000;
1303 } else if (mmc
->card_caps
& MMC_MODE_HS
) {
1304 mmc_select_mode(mmc
, MMC_HS
);
1305 mmc
->tran_speed
= 26000000;
1311 static int mmc_startup_v4(struct mmc
*mmc
)
1315 bool has_parts
= false;
1316 bool part_completed
;
1319 if (IS_SD(mmc
) || (mmc
->version
< MMC_VERSION_4
))
1322 ext_csd
= malloc_cache_aligned(MMC_MAX_BLOCK_LEN
);
1326 mmc
->ext_csd
= ext_csd
;
1328 /* check ext_csd version and capacity */
1329 err
= mmc_send_ext_csd(mmc
, ext_csd
);
1332 if (ext_csd
[EXT_CSD_REV
] >= 2) {
1334 * According to the JEDEC Standard, the value of
1335 * ext_csd's capacity is valid if the value is more
1338 capacity
= ext_csd
[EXT_CSD_SEC_CNT
] << 0
1339 | ext_csd
[EXT_CSD_SEC_CNT
+ 1] << 8
1340 | ext_csd
[EXT_CSD_SEC_CNT
+ 2] << 16
1341 | ext_csd
[EXT_CSD_SEC_CNT
+ 3] << 24;
1342 capacity
*= MMC_MAX_BLOCK_LEN
;
1343 if ((capacity
>> 20) > 2 * 1024)
1344 mmc
->capacity_user
= capacity
;
1347 switch (ext_csd
[EXT_CSD_REV
]) {
1349 mmc
->version
= MMC_VERSION_4_1
;
1352 mmc
->version
= MMC_VERSION_4_2
;
1355 mmc
->version
= MMC_VERSION_4_3
;
1358 mmc
->version
= MMC_VERSION_4_41
;
1361 mmc
->version
= MMC_VERSION_4_5
;
1364 mmc
->version
= MMC_VERSION_5_0
;
1367 mmc
->version
= MMC_VERSION_5_1
;
1371 /* The partition data may be non-zero but it is only
1372 * effective if PARTITION_SETTING_COMPLETED is set in
1373 * EXT_CSD, so ignore any data if this bit is not set,
1374 * except for enabling the high-capacity group size
1375 * definition (see below).
1377 part_completed
= !!(ext_csd
[EXT_CSD_PARTITION_SETTING
] &
1378 EXT_CSD_PARTITION_SETTING_COMPLETED
);
1380 /* store the partition info of emmc */
1381 mmc
->part_support
= ext_csd
[EXT_CSD_PARTITIONING_SUPPORT
];
1382 if ((ext_csd
[EXT_CSD_PARTITIONING_SUPPORT
] & PART_SUPPORT
) ||
1383 ext_csd
[EXT_CSD_BOOT_MULT
])
1384 mmc
->part_config
= ext_csd
[EXT_CSD_PART_CONF
];
1385 if (part_completed
&&
1386 (ext_csd
[EXT_CSD_PARTITIONING_SUPPORT
] & ENHNCD_SUPPORT
))
1387 mmc
->part_attr
= ext_csd
[EXT_CSD_PARTITIONS_ATTRIBUTE
];
1389 mmc
->capacity_boot
= ext_csd
[EXT_CSD_BOOT_MULT
] << 17;
1391 mmc
->capacity_rpmb
= ext_csd
[EXT_CSD_RPMB_MULT
] << 17;
1393 for (i
= 0; i
< 4; i
++) {
1394 int idx
= EXT_CSD_GP_SIZE_MULT
+ i
* 3;
1395 uint mult
= (ext_csd
[idx
+ 2] << 16) +
1396 (ext_csd
[idx
+ 1] << 8) + ext_csd
[idx
];
1399 if (!part_completed
)
1401 mmc
->capacity_gp
[i
] = mult
;
1402 mmc
->capacity_gp
[i
] *=
1403 ext_csd
[EXT_CSD_HC_ERASE_GRP_SIZE
];
1404 mmc
->capacity_gp
[i
] *= ext_csd
[EXT_CSD_HC_WP_GRP_SIZE
];
1405 mmc
->capacity_gp
[i
] <<= 19;
1408 if (part_completed
) {
1409 mmc
->enh_user_size
=
1410 (ext_csd
[EXT_CSD_ENH_SIZE_MULT
+ 2] << 16) +
1411 (ext_csd
[EXT_CSD_ENH_SIZE_MULT
+ 1] << 8) +
1412 ext_csd
[EXT_CSD_ENH_SIZE_MULT
];
1413 mmc
->enh_user_size
*= ext_csd
[EXT_CSD_HC_ERASE_GRP_SIZE
];
1414 mmc
->enh_user_size
*= ext_csd
[EXT_CSD_HC_WP_GRP_SIZE
];
1415 mmc
->enh_user_size
<<= 19;
1416 mmc
->enh_user_start
=
1417 (ext_csd
[EXT_CSD_ENH_START_ADDR
+ 3] << 24) +
1418 (ext_csd
[EXT_CSD_ENH_START_ADDR
+ 2] << 16) +
1419 (ext_csd
[EXT_CSD_ENH_START_ADDR
+ 1] << 8) +
1420 ext_csd
[EXT_CSD_ENH_START_ADDR
];
1421 if (mmc
->high_capacity
)
1422 mmc
->enh_user_start
<<= 9;
1426 * Host needs to enable ERASE_GRP_DEF bit if device is
1427 * partitioned. This bit will be lost every time after a reset
1428 * or power off. This will affect erase size.
1432 if ((ext_csd
[EXT_CSD_PARTITIONING_SUPPORT
] & PART_SUPPORT
) &&
1433 (ext_csd
[EXT_CSD_PARTITIONS_ATTRIBUTE
] & PART_ENH_ATTRIB
))
1436 err
= mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
,
1437 EXT_CSD_ERASE_GROUP_DEF
, 1);
1442 ext_csd
[EXT_CSD_ERASE_GROUP_DEF
] = 1;
1445 if (ext_csd
[EXT_CSD_ERASE_GROUP_DEF
] & 0x01) {
1446 /* Read out group size from ext_csd */
1447 mmc
->erase_grp_size
=
1448 ext_csd
[EXT_CSD_HC_ERASE_GRP_SIZE
] * 1024;
1450 * if high capacity and partition setting completed
1451 * SEC_COUNT is valid even if it is smaller than 2 GiB
1452 * JEDEC Standard JESD84-B45, 6.2.4
1454 if (mmc
->high_capacity
&& part_completed
) {
1455 capacity
= (ext_csd
[EXT_CSD_SEC_CNT
]) |
1456 (ext_csd
[EXT_CSD_SEC_CNT
+ 1] << 8) |
1457 (ext_csd
[EXT_CSD_SEC_CNT
+ 2] << 16) |
1458 (ext_csd
[EXT_CSD_SEC_CNT
+ 3] << 24);
1459 capacity
*= MMC_MAX_BLOCK_LEN
;
1460 mmc
->capacity_user
= capacity
;
1463 /* Calculate the group size from the csd value. */
1464 int erase_gsz
, erase_gmul
;
1466 erase_gsz
= (mmc
->csd
[2] & 0x00007c00) >> 10;
1467 erase_gmul
= (mmc
->csd
[2] & 0x000003e0) >> 5;
1468 mmc
->erase_grp_size
= (erase_gsz
+ 1)
1472 mmc
->hc_wp_grp_size
= 1024
1473 * ext_csd
[EXT_CSD_HC_ERASE_GRP_SIZE
]
1474 * ext_csd
[EXT_CSD_HC_WP_GRP_SIZE
];
1476 mmc
->wr_rel_set
= ext_csd
[EXT_CSD_WR_REL_SET
];
1481 static int mmc_startup(struct mmc
*mmc
)
1487 struct blk_desc
*bdesc
;
1489 #ifdef CONFIG_MMC_SPI_CRC_ON
1490 if (mmc_host_is_spi(mmc
)) { /* enable CRC check for spi */
1491 cmd
.cmdidx
= MMC_CMD_SPI_CRC_ON_OFF
;
1492 cmd
.resp_type
= MMC_RSP_R1
;
1494 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
1501 /* Put the Card in Identify Mode */
1502 cmd
.cmdidx
= mmc_host_is_spi(mmc
) ? MMC_CMD_SEND_CID
:
1503 MMC_CMD_ALL_SEND_CID
; /* cmd not supported in spi */
1504 cmd
.resp_type
= MMC_RSP_R2
;
1507 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
1512 memcpy(mmc
->cid
, cmd
.response
, 16);
1515 * For MMC cards, set the Relative Address.
1516 * For SD cards, get the Relatvie Address.
1517 * This also puts the cards into Standby State
1519 if (!mmc_host_is_spi(mmc
)) { /* cmd not supported in spi */
1520 cmd
.cmdidx
= SD_CMD_SEND_RELATIVE_ADDR
;
1521 cmd
.cmdarg
= mmc
->rca
<< 16;
1522 cmd
.resp_type
= MMC_RSP_R6
;
1524 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
1530 mmc
->rca
= (cmd
.response
[0] >> 16) & 0xffff;
1533 /* Get the Card-Specific Data */
1534 cmd
.cmdidx
= MMC_CMD_SEND_CSD
;
1535 cmd
.resp_type
= MMC_RSP_R2
;
1536 cmd
.cmdarg
= mmc
->rca
<< 16;
1538 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
1543 mmc
->csd
[0] = cmd
.response
[0];
1544 mmc
->csd
[1] = cmd
.response
[1];
1545 mmc
->csd
[2] = cmd
.response
[2];
1546 mmc
->csd
[3] = cmd
.response
[3];
1548 if (mmc
->version
== MMC_VERSION_UNKNOWN
) {
1549 int version
= (cmd
.response
[0] >> 26) & 0xf;
1553 mmc
->version
= MMC_VERSION_1_2
;
1556 mmc
->version
= MMC_VERSION_1_4
;
1559 mmc
->version
= MMC_VERSION_2_2
;
1562 mmc
->version
= MMC_VERSION_3
;
1565 mmc
->version
= MMC_VERSION_4
;
1568 mmc
->version
= MMC_VERSION_1_2
;
1573 /* divide frequency by 10, since the mults are 10x bigger */
1574 freq
= fbase
[(cmd
.response
[0] & 0x7)];
1575 mult
= multipliers
[((cmd
.response
[0] >> 3) & 0xf)];
1577 mmc
->legacy_speed
= freq
* mult
;
1578 mmc
->tran_speed
= mmc
->legacy_speed
;
1579 mmc_select_mode(mmc
, MMC_LEGACY
);
1581 mmc
->dsr_imp
= ((cmd
.response
[1] >> 12) & 0x1);
1582 mmc
->read_bl_len
= 1 << ((cmd
.response
[1] >> 16) & 0xf);
1585 mmc
->write_bl_len
= mmc
->read_bl_len
;
1587 mmc
->write_bl_len
= 1 << ((cmd
.response
[3] >> 22) & 0xf);
1589 if (mmc
->high_capacity
) {
1590 csize
= (mmc
->csd
[1] & 0x3f) << 16
1591 | (mmc
->csd
[2] & 0xffff0000) >> 16;
1594 csize
= (mmc
->csd
[1] & 0x3ff) << 2
1595 | (mmc
->csd
[2] & 0xc0000000) >> 30;
1596 cmult
= (mmc
->csd
[2] & 0x00038000) >> 15;
1599 mmc
->capacity_user
= (csize
+ 1) << (cmult
+ 2);
1600 mmc
->capacity_user
*= mmc
->read_bl_len
;
1601 mmc
->capacity_boot
= 0;
1602 mmc
->capacity_rpmb
= 0;
1603 for (i
= 0; i
< 4; i
++)
1604 mmc
->capacity_gp
[i
] = 0;
1606 if (mmc
->read_bl_len
> MMC_MAX_BLOCK_LEN
)
1607 mmc
->read_bl_len
= MMC_MAX_BLOCK_LEN
;
1609 if (mmc
->write_bl_len
> MMC_MAX_BLOCK_LEN
)
1610 mmc
->write_bl_len
= MMC_MAX_BLOCK_LEN
;
1612 if ((mmc
->dsr_imp
) && (0xffffffff != mmc
->dsr
)) {
1613 cmd
.cmdidx
= MMC_CMD_SET_DSR
;
1614 cmd
.cmdarg
= (mmc
->dsr
& 0xffff) << 16;
1615 cmd
.resp_type
= MMC_RSP_NONE
;
1616 if (mmc_send_cmd(mmc
, &cmd
, NULL
))
1617 printf("MMC: SET_DSR failed\n");
1620 /* Select the card, and put it into Transfer Mode */
1621 if (!mmc_host_is_spi(mmc
)) { /* cmd not supported in spi */
1622 cmd
.cmdidx
= MMC_CMD_SELECT_CARD
;
1623 cmd
.resp_type
= MMC_RSP_R1
;
1624 cmd
.cmdarg
= mmc
->rca
<< 16;
1625 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
1632 * For SD, its erase group is always one sector
1634 mmc
->erase_grp_size
= 1;
1635 mmc
->part_config
= MMCPART_NOAVAILABLE
;
1637 err
= mmc_startup_v4(mmc
);
1641 err
= mmc_set_capacity(mmc
, mmc_get_blk_desc(mmc
)->hwpart
);
1646 err
= sd_select_bus_freq_width(mmc
);
1648 err
= mmc_select_bus_freq_width(mmc
);
1653 mmc_set_clock(mmc
, mmc
->tran_speed
);
1655 /* Fix the block length for DDR mode */
1656 if (mmc
->ddr_mode
) {
1657 mmc
->read_bl_len
= MMC_MAX_BLOCK_LEN
;
1658 mmc
->write_bl_len
= MMC_MAX_BLOCK_LEN
;
1661 /* fill in device description */
1662 bdesc
= mmc_get_blk_desc(mmc
);
1666 bdesc
->blksz
= mmc
->read_bl_len
;
1667 bdesc
->log2blksz
= LOG2(bdesc
->blksz
);
1668 bdesc
->lba
= lldiv(mmc
->capacity
, mmc
->read_bl_len
);
1669 #if !defined(CONFIG_SPL_BUILD) || \
1670 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
1671 !defined(CONFIG_USE_TINY_PRINTF))
1672 sprintf(bdesc
->vendor
, "Man %06x Snr %04x%04x",
1673 mmc
->cid
[0] >> 24, (mmc
->cid
[2] & 0xffff),
1674 (mmc
->cid
[3] >> 16) & 0xffff);
1675 sprintf(bdesc
->product
, "%c%c%c%c%c%c", mmc
->cid
[0] & 0xff,
1676 (mmc
->cid
[1] >> 24), (mmc
->cid
[1] >> 16) & 0xff,
1677 (mmc
->cid
[1] >> 8) & 0xff, mmc
->cid
[1] & 0xff,
1678 (mmc
->cid
[2] >> 24) & 0xff);
1679 sprintf(bdesc
->revision
, "%d.%d", (mmc
->cid
[2] >> 20) & 0xf,
1680 (mmc
->cid
[2] >> 16) & 0xf);
1682 bdesc
->vendor
[0] = 0;
1683 bdesc
->product
[0] = 0;
1684 bdesc
->revision
[0] = 0;
1686 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
1693 static int mmc_send_if_cond(struct mmc
*mmc
)
1698 cmd
.cmdidx
= SD_CMD_SEND_IF_COND
;
1699 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
1700 cmd
.cmdarg
= ((mmc
->cfg
->voltages
& 0xff8000) != 0) << 8 | 0xaa;
1701 cmd
.resp_type
= MMC_RSP_R7
;
1703 err
= mmc_send_cmd(mmc
, &cmd
, NULL
);
1708 if ((cmd
.response
[0] & 0xff) != 0xaa)
1711 mmc
->version
= SD_VERSION_2
;
1716 #if !CONFIG_IS_ENABLED(DM_MMC)
1717 /* board-specific MMC power initializations. */
1718 __weak
void board_mmc_power_init(void)
1723 static int mmc_power_init(struct mmc
*mmc
)
1725 #if CONFIG_IS_ENABLED(DM_MMC)
1726 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1729 ret
= device_get_supply_regulator(mmc
->dev
, "vmmc-supply",
1732 debug("%s: No vmmc supply\n", mmc
->dev
->name
);
1734 ret
= device_get_supply_regulator(mmc
->dev
, "vqmmc-supply",
1735 &mmc
->vqmmc_supply
);
1737 debug("%s: No vqmmc supply\n", mmc
->dev
->name
);
1739 if (mmc
->vmmc_supply
) {
1740 ret
= regulator_set_enable(mmc
->vmmc_supply
, true);
1742 puts("Error enabling VMMC supply\n");
1747 #else /* !CONFIG_DM_MMC */
1749 * Driver model should use a regulator, as above, rather than calling
1750 * out to board code.
1752 board_mmc_power_init();
1757 int mmc_start_init(struct mmc
*mmc
)
1762 /* we pretend there's no card when init is NULL */
1763 no_card
= mmc_getcd(mmc
) == 0;
1764 #if !CONFIG_IS_ENABLED(DM_MMC)
1765 no_card
= no_card
|| (mmc
->cfg
->ops
->init
== NULL
);
1769 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1770 printf("MMC: no card present\n");
1778 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1779 mmc_adapter_card_type_ident();
1781 err
= mmc_power_init(mmc
);
1785 #if CONFIG_IS_ENABLED(DM_MMC)
1786 /* The device has already been probed ready for use */
1788 /* made sure it's not NULL earlier */
1789 err
= mmc
->cfg
->ops
->init(mmc
);
1794 mmc_set_bus_width(mmc
, 1);
1795 mmc_set_clock(mmc
, 1);
1797 /* Reset the Card */
1798 err
= mmc_go_idle(mmc
);
1803 /* The internal partition reset to user partition(0) at every CMD0*/
1804 mmc_get_blk_desc(mmc
)->hwpart
= 0;
1806 /* Test for SD version 2 */
1807 err
= mmc_send_if_cond(mmc
);
1809 /* Now try to get the SD card's operating condition */
1810 err
= sd_send_op_cond(mmc
);
1812 /* If the command timed out, we check for an MMC card */
1813 if (err
== -ETIMEDOUT
) {
1814 err
= mmc_send_op_cond(mmc
);
1817 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1818 printf("Card did not respond to voltage select!\n");
1825 mmc
->init_in_progress
= 1;
1830 static int mmc_complete_init(struct mmc
*mmc
)
1834 mmc
->init_in_progress
= 0;
1835 if (mmc
->op_cond_pending
)
1836 err
= mmc_complete_op_cond(mmc
);
1839 err
= mmc_startup(mmc
);
1847 int mmc_init(struct mmc
*mmc
)
1850 __maybe_unused
unsigned start
;
1851 #if CONFIG_IS_ENABLED(DM_MMC)
1852 struct mmc_uclass_priv
*upriv
= dev_get_uclass_priv(mmc
->dev
);
1859 start
= get_timer(0);
1861 if (!mmc
->init_in_progress
)
1862 err
= mmc_start_init(mmc
);
1865 err
= mmc_complete_init(mmc
);
1867 printf("%s: %d, time %lu\n", __func__
, err
, get_timer(start
));
1872 int mmc_set_dsr(struct mmc
*mmc
, u16 val
)
1878 /* CPU-specific MMC initializations */
1879 __weak
int cpu_mmc_init(bd_t
*bis
)
1884 /* board-specific MMC initializations. */
1885 __weak
int board_mmc_init(bd_t
*bis
)
1890 void mmc_set_preinit(struct mmc
*mmc
, int preinit
)
1892 mmc
->preinit
= preinit
;
1895 #if CONFIG_IS_ENABLED(DM_MMC) && defined(CONFIG_SPL_BUILD)
1896 static int mmc_probe(bd_t
*bis
)
1900 #elif CONFIG_IS_ENABLED(DM_MMC)
1901 static int mmc_probe(bd_t
*bis
)
1905 struct udevice
*dev
;
1907 ret
= uclass_get(UCLASS_MMC
, &uc
);
1912 * Try to add them in sequence order. Really with driver model we
1913 * should allow holes, but the current MMC list does not allow that.
1914 * So if we request 0, 1, 3 we will get 0, 1, 2.
1916 for (i
= 0; ; i
++) {
1917 ret
= uclass_get_device_by_seq(UCLASS_MMC
, i
, &dev
);
1921 uclass_foreach_dev(dev
, uc
) {
1922 ret
= device_probe(dev
);
1924 printf("%s - probe failed: %d\n", dev
->name
, ret
);
1930 static int mmc_probe(bd_t
*bis
)
1932 if (board_mmc_init(bis
) < 0)
1939 int mmc_initialize(bd_t
*bis
)
1941 static int initialized
= 0;
1943 if (initialized
) /* Avoid initializing mmc multiple times */
1947 #if !CONFIG_IS_ENABLED(BLK)
1948 #if !CONFIG_IS_ENABLED(MMC_TINY)
1952 ret
= mmc_probe(bis
);
1956 #ifndef CONFIG_SPL_BUILD
1957 print_mmc_devices(',');
1964 #ifdef CONFIG_CMD_BKOPS_ENABLE
1965 int mmc_set_bkops_enable(struct mmc
*mmc
)
1968 ALLOC_CACHE_ALIGN_BUFFER(u8
, ext_csd
, MMC_MAX_BLOCK_LEN
);
1970 err
= mmc_send_ext_csd(mmc
, ext_csd
);
1972 puts("Could not get ext_csd register values\n");
1976 if (!(ext_csd
[EXT_CSD_BKOPS_SUPPORT
] & 0x1)) {
1977 puts("Background operations not supported on device\n");
1978 return -EMEDIUMTYPE
;
1981 if (ext_csd
[EXT_CSD_BKOPS_EN
] & 0x1) {
1982 puts("Background operations already enabled\n");
1986 err
= mmc_switch(mmc
, EXT_CSD_CMD_SET_NORMAL
, EXT_CSD_BKOPS_EN
, 1);
1988 puts("Failed to enable manual background operations\n");
1992 puts("Enabled manual background operations\n");