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[people/ms/u-boot.git] / drivers / mmc / mmc.c
1 /*
2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based vaguely on the Linux code
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #include <config.h>
11 #include <common.h>
12 #include <command.h>
13 #include <dm.h>
14 #include <dm/device-internal.h>
15 #include <errno.h>
16 #include <mmc.h>
17 #include <part.h>
18 #include <malloc.h>
19 #include <memalign.h>
20 #include <linux/list.h>
21 #include <div64.h>
22 #include "mmc_private.h"
23
24 #ifndef CONFIG_DM_MMC_OPS
25 __weak int board_mmc_getwp(struct mmc *mmc)
26 {
27 return -1;
28 }
29
30 int mmc_getwp(struct mmc *mmc)
31 {
32 int wp;
33
34 wp = board_mmc_getwp(mmc);
35
36 if (wp < 0) {
37 if (mmc->cfg->ops->getwp)
38 wp = mmc->cfg->ops->getwp(mmc);
39 else
40 wp = 0;
41 }
42
43 return wp;
44 }
45
46 __weak int board_mmc_getcd(struct mmc *mmc)
47 {
48 return -1;
49 }
50 #endif
51
52 #ifdef CONFIG_MMC_TRACE
53 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
54 {
55 printf("CMD_SEND:%d\n", cmd->cmdidx);
56 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
57 }
58
59 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
60 {
61 int i;
62 u8 *ptr;
63
64 if (ret) {
65 printf("\t\tRET\t\t\t %d\n", ret);
66 } else {
67 switch (cmd->resp_type) {
68 case MMC_RSP_NONE:
69 printf("\t\tMMC_RSP_NONE\n");
70 break;
71 case MMC_RSP_R1:
72 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
73 cmd->response[0]);
74 break;
75 case MMC_RSP_R1b:
76 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
77 cmd->response[0]);
78 break;
79 case MMC_RSP_R2:
80 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
81 cmd->response[0]);
82 printf("\t\t \t\t 0x%08X \n",
83 cmd->response[1]);
84 printf("\t\t \t\t 0x%08X \n",
85 cmd->response[2]);
86 printf("\t\t \t\t 0x%08X \n",
87 cmd->response[3]);
88 printf("\n");
89 printf("\t\t\t\t\tDUMPING DATA\n");
90 for (i = 0; i < 4; i++) {
91 int j;
92 printf("\t\t\t\t\t%03d - ", i*4);
93 ptr = (u8 *)&cmd->response[i];
94 ptr += 3;
95 for (j = 0; j < 4; j++)
96 printf("%02X ", *ptr--);
97 printf("\n");
98 }
99 break;
100 case MMC_RSP_R3:
101 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
102 cmd->response[0]);
103 break;
104 default:
105 printf("\t\tERROR MMC rsp not supported\n");
106 break;
107 }
108 }
109 }
110
111 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
112 {
113 int status;
114
115 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
116 printf("CURR STATE:%d\n", status);
117 }
118 #endif
119
120 #ifndef CONFIG_DM_MMC_OPS
121 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
122 {
123 int ret;
124
125 mmmc_trace_before_send(mmc, cmd);
126 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
127 mmmc_trace_after_send(mmc, cmd, ret);
128
129 return ret;
130 }
131 #endif
132
133 int mmc_send_status(struct mmc *mmc, int timeout)
134 {
135 struct mmc_cmd cmd;
136 int err, retries = 5;
137
138 cmd.cmdidx = MMC_CMD_SEND_STATUS;
139 cmd.resp_type = MMC_RSP_R1;
140 if (!mmc_host_is_spi(mmc))
141 cmd.cmdarg = mmc->rca << 16;
142
143 while (1) {
144 err = mmc_send_cmd(mmc, &cmd, NULL);
145 if (!err) {
146 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
147 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
148 MMC_STATE_PRG)
149 break;
150 else if (cmd.response[0] & MMC_STATUS_MASK) {
151 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
152 printf("Status Error: 0x%08X\n",
153 cmd.response[0]);
154 #endif
155 return COMM_ERR;
156 }
157 } else if (--retries < 0)
158 return err;
159
160 if (timeout-- <= 0)
161 break;
162
163 udelay(1000);
164 }
165
166 mmc_trace_state(mmc, &cmd);
167 if (timeout <= 0) {
168 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
169 printf("Timeout waiting card ready\n");
170 #endif
171 return TIMEOUT;
172 }
173
174 return 0;
175 }
176
177 int mmc_set_blocklen(struct mmc *mmc, int len)
178 {
179 struct mmc_cmd cmd;
180
181 if (mmc->ddr_mode)
182 return 0;
183
184 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
185 cmd.resp_type = MMC_RSP_R1;
186 cmd.cmdarg = len;
187
188 return mmc_send_cmd(mmc, &cmd, NULL);
189 }
190
191 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
192 lbaint_t blkcnt)
193 {
194 struct mmc_cmd cmd;
195 struct mmc_data data;
196
197 if (blkcnt > 1)
198 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
199 else
200 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
201
202 if (mmc->high_capacity)
203 cmd.cmdarg = start;
204 else
205 cmd.cmdarg = start * mmc->read_bl_len;
206
207 cmd.resp_type = MMC_RSP_R1;
208
209 data.dest = dst;
210 data.blocks = blkcnt;
211 data.blocksize = mmc->read_bl_len;
212 data.flags = MMC_DATA_READ;
213
214 if (mmc_send_cmd(mmc, &cmd, &data))
215 return 0;
216
217 if (blkcnt > 1) {
218 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
219 cmd.cmdarg = 0;
220 cmd.resp_type = MMC_RSP_R1b;
221 if (mmc_send_cmd(mmc, &cmd, NULL)) {
222 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
223 printf("mmc fail to send stop cmd\n");
224 #endif
225 return 0;
226 }
227 }
228
229 return blkcnt;
230 }
231
232 #ifdef CONFIG_BLK
233 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
234 #else
235 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
236 void *dst)
237 #endif
238 {
239 #ifdef CONFIG_BLK
240 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
241 #endif
242 int dev_num = block_dev->devnum;
243 int err;
244 lbaint_t cur, blocks_todo = blkcnt;
245
246 if (blkcnt == 0)
247 return 0;
248
249 struct mmc *mmc = find_mmc_device(dev_num);
250 if (!mmc)
251 return 0;
252
253 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
254 if (err < 0)
255 return 0;
256
257 if ((start + blkcnt) > block_dev->lba) {
258 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
259 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
260 start + blkcnt, block_dev->lba);
261 #endif
262 return 0;
263 }
264
265 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
266 debug("%s: Failed to set blocklen\n", __func__);
267 return 0;
268 }
269
270 do {
271 cur = (blocks_todo > mmc->cfg->b_max) ?
272 mmc->cfg->b_max : blocks_todo;
273 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
274 debug("%s: Failed to read blocks\n", __func__);
275 return 0;
276 }
277 blocks_todo -= cur;
278 start += cur;
279 dst += cur * mmc->read_bl_len;
280 } while (blocks_todo > 0);
281
282 return blkcnt;
283 }
284
285 static int mmc_go_idle(struct mmc *mmc)
286 {
287 struct mmc_cmd cmd;
288 int err;
289
290 udelay(1000);
291
292 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
293 cmd.cmdarg = 0;
294 cmd.resp_type = MMC_RSP_NONE;
295
296 err = mmc_send_cmd(mmc, &cmd, NULL);
297
298 if (err)
299 return err;
300
301 udelay(2000);
302
303 return 0;
304 }
305
306 static int sd_send_op_cond(struct mmc *mmc)
307 {
308 int timeout = 1000;
309 int err;
310 struct mmc_cmd cmd;
311
312 while (1) {
313 cmd.cmdidx = MMC_CMD_APP_CMD;
314 cmd.resp_type = MMC_RSP_R1;
315 cmd.cmdarg = 0;
316
317 err = mmc_send_cmd(mmc, &cmd, NULL);
318
319 if (err)
320 return err;
321
322 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
323 cmd.resp_type = MMC_RSP_R3;
324
325 /*
326 * Most cards do not answer if some reserved bits
327 * in the ocr are set. However, Some controller
328 * can set bit 7 (reserved for low voltages), but
329 * how to manage low voltages SD card is not yet
330 * specified.
331 */
332 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
333 (mmc->cfg->voltages & 0xff8000);
334
335 if (mmc->version == SD_VERSION_2)
336 cmd.cmdarg |= OCR_HCS;
337
338 err = mmc_send_cmd(mmc, &cmd, NULL);
339
340 if (err)
341 return err;
342
343 if (cmd.response[0] & OCR_BUSY)
344 break;
345
346 if (timeout-- <= 0)
347 return UNUSABLE_ERR;
348
349 udelay(1000);
350 }
351
352 if (mmc->version != SD_VERSION_2)
353 mmc->version = SD_VERSION_1_0;
354
355 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
356 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
357 cmd.resp_type = MMC_RSP_R3;
358 cmd.cmdarg = 0;
359
360 err = mmc_send_cmd(mmc, &cmd, NULL);
361
362 if (err)
363 return err;
364 }
365
366 mmc->ocr = cmd.response[0];
367
368 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
369 mmc->rca = 0;
370
371 return 0;
372 }
373
374 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
375 {
376 struct mmc_cmd cmd;
377 int err;
378
379 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
380 cmd.resp_type = MMC_RSP_R3;
381 cmd.cmdarg = 0;
382 if (use_arg && !mmc_host_is_spi(mmc))
383 cmd.cmdarg = OCR_HCS |
384 (mmc->cfg->voltages &
385 (mmc->ocr & OCR_VOLTAGE_MASK)) |
386 (mmc->ocr & OCR_ACCESS_MODE);
387
388 err = mmc_send_cmd(mmc, &cmd, NULL);
389 if (err)
390 return err;
391 mmc->ocr = cmd.response[0];
392 return 0;
393 }
394
395 static int mmc_send_op_cond(struct mmc *mmc)
396 {
397 int err, i;
398
399 /* Some cards seem to need this */
400 mmc_go_idle(mmc);
401
402 /* Asking to the card its capabilities */
403 for (i = 0; i < 2; i++) {
404 err = mmc_send_op_cond_iter(mmc, i != 0);
405 if (err)
406 return err;
407
408 /* exit if not busy (flag seems to be inverted) */
409 if (mmc->ocr & OCR_BUSY)
410 break;
411 }
412 mmc->op_cond_pending = 1;
413 return 0;
414 }
415
416 static int mmc_complete_op_cond(struct mmc *mmc)
417 {
418 struct mmc_cmd cmd;
419 int timeout = 1000;
420 uint start;
421 int err;
422
423 mmc->op_cond_pending = 0;
424 if (!(mmc->ocr & OCR_BUSY)) {
425 start = get_timer(0);
426 while (1) {
427 err = mmc_send_op_cond_iter(mmc, 1);
428 if (err)
429 return err;
430 if (mmc->ocr & OCR_BUSY)
431 break;
432 if (get_timer(start) > timeout)
433 return UNUSABLE_ERR;
434 udelay(100);
435 }
436 }
437
438 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
439 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
440 cmd.resp_type = MMC_RSP_R3;
441 cmd.cmdarg = 0;
442
443 err = mmc_send_cmd(mmc, &cmd, NULL);
444
445 if (err)
446 return err;
447
448 mmc->ocr = cmd.response[0];
449 }
450
451 mmc->version = MMC_VERSION_UNKNOWN;
452
453 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
454 mmc->rca = 1;
455
456 return 0;
457 }
458
459
460 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
461 {
462 struct mmc_cmd cmd;
463 struct mmc_data data;
464 int err;
465
466 /* Get the Card Status Register */
467 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
468 cmd.resp_type = MMC_RSP_R1;
469 cmd.cmdarg = 0;
470
471 data.dest = (char *)ext_csd;
472 data.blocks = 1;
473 data.blocksize = MMC_MAX_BLOCK_LEN;
474 data.flags = MMC_DATA_READ;
475
476 err = mmc_send_cmd(mmc, &cmd, &data);
477
478 return err;
479 }
480
481 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
482 {
483 struct mmc_cmd cmd;
484 int timeout = 1000;
485 int ret;
486
487 cmd.cmdidx = MMC_CMD_SWITCH;
488 cmd.resp_type = MMC_RSP_R1b;
489 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
490 (index << 16) |
491 (value << 8);
492
493 ret = mmc_send_cmd(mmc, &cmd, NULL);
494
495 /* Waiting for the ready status */
496 if (!ret)
497 ret = mmc_send_status(mmc, timeout);
498
499 return ret;
500
501 }
502
503 static int mmc_change_freq(struct mmc *mmc)
504 {
505 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
506 char cardtype;
507 int err;
508
509 mmc->card_caps = 0;
510
511 if (mmc_host_is_spi(mmc))
512 return 0;
513
514 /* Only version 4 supports high-speed */
515 if (mmc->version < MMC_VERSION_4)
516 return 0;
517
518 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
519
520 err = mmc_send_ext_csd(mmc, ext_csd);
521
522 if (err)
523 return err;
524
525 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
526
527 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
528
529 if (err)
530 return err;
531
532 /* Now check to see that it worked */
533 err = mmc_send_ext_csd(mmc, ext_csd);
534
535 if (err)
536 return err;
537
538 /* No high-speed support */
539 if (!ext_csd[EXT_CSD_HS_TIMING])
540 return 0;
541
542 /* High Speed is set, there are two types: 52MHz and 26MHz */
543 if (cardtype & EXT_CSD_CARD_TYPE_52) {
544 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
545 mmc->card_caps |= MMC_MODE_DDR_52MHz;
546 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
547 } else {
548 mmc->card_caps |= MMC_MODE_HS;
549 }
550
551 return 0;
552 }
553
554 static int mmc_set_capacity(struct mmc *mmc, int part_num)
555 {
556 switch (part_num) {
557 case 0:
558 mmc->capacity = mmc->capacity_user;
559 break;
560 case 1:
561 case 2:
562 mmc->capacity = mmc->capacity_boot;
563 break;
564 case 3:
565 mmc->capacity = mmc->capacity_rpmb;
566 break;
567 case 4:
568 case 5:
569 case 6:
570 case 7:
571 mmc->capacity = mmc->capacity_gp[part_num - 4];
572 break;
573 default:
574 return -1;
575 }
576
577 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
578
579 return 0;
580 }
581
582 int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
583 {
584 int ret;
585
586 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
587 (mmc->part_config & ~PART_ACCESS_MASK)
588 | (part_num & PART_ACCESS_MASK));
589
590 /*
591 * Set the capacity if the switch succeeded or was intended
592 * to return to representing the raw device.
593 */
594 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
595 ret = mmc_set_capacity(mmc, part_num);
596 mmc_get_blk_desc(mmc)->hwpart = part_num;
597 }
598
599 return ret;
600 }
601
602 int mmc_hwpart_config(struct mmc *mmc,
603 const struct mmc_hwpart_conf *conf,
604 enum mmc_hwpart_conf_mode mode)
605 {
606 u8 part_attrs = 0;
607 u32 enh_size_mult;
608 u32 enh_start_addr;
609 u32 gp_size_mult[4];
610 u32 max_enh_size_mult;
611 u32 tot_enh_size_mult = 0;
612 u8 wr_rel_set;
613 int i, pidx, err;
614 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
615
616 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
617 return -EINVAL;
618
619 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
620 printf("eMMC >= 4.4 required for enhanced user data area\n");
621 return -EMEDIUMTYPE;
622 }
623
624 if (!(mmc->part_support & PART_SUPPORT)) {
625 printf("Card does not support partitioning\n");
626 return -EMEDIUMTYPE;
627 }
628
629 if (!mmc->hc_wp_grp_size) {
630 printf("Card does not define HC WP group size\n");
631 return -EMEDIUMTYPE;
632 }
633
634 /* check partition alignment and total enhanced size */
635 if (conf->user.enh_size) {
636 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
637 conf->user.enh_start % mmc->hc_wp_grp_size) {
638 printf("User data enhanced area not HC WP group "
639 "size aligned\n");
640 return -EINVAL;
641 }
642 part_attrs |= EXT_CSD_ENH_USR;
643 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
644 if (mmc->high_capacity) {
645 enh_start_addr = conf->user.enh_start;
646 } else {
647 enh_start_addr = (conf->user.enh_start << 9);
648 }
649 } else {
650 enh_size_mult = 0;
651 enh_start_addr = 0;
652 }
653 tot_enh_size_mult += enh_size_mult;
654
655 for (pidx = 0; pidx < 4; pidx++) {
656 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
657 printf("GP%i partition not HC WP group size "
658 "aligned\n", pidx+1);
659 return -EINVAL;
660 }
661 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
662 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
663 part_attrs |= EXT_CSD_ENH_GP(pidx);
664 tot_enh_size_mult += gp_size_mult[pidx];
665 }
666 }
667
668 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
669 printf("Card does not support enhanced attribute\n");
670 return -EMEDIUMTYPE;
671 }
672
673 err = mmc_send_ext_csd(mmc, ext_csd);
674 if (err)
675 return err;
676
677 max_enh_size_mult =
678 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
679 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
680 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
681 if (tot_enh_size_mult > max_enh_size_mult) {
682 printf("Total enhanced size exceeds maximum (%u > %u)\n",
683 tot_enh_size_mult, max_enh_size_mult);
684 return -EMEDIUMTYPE;
685 }
686
687 /* The default value of EXT_CSD_WR_REL_SET is device
688 * dependent, the values can only be changed if the
689 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
690 * changed only once and before partitioning is completed. */
691 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
692 if (conf->user.wr_rel_change) {
693 if (conf->user.wr_rel_set)
694 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
695 else
696 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
697 }
698 for (pidx = 0; pidx < 4; pidx++) {
699 if (conf->gp_part[pidx].wr_rel_change) {
700 if (conf->gp_part[pidx].wr_rel_set)
701 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
702 else
703 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
704 }
705 }
706
707 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
708 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
709 puts("Card does not support host controlled partition write "
710 "reliability settings\n");
711 return -EMEDIUMTYPE;
712 }
713
714 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
715 EXT_CSD_PARTITION_SETTING_COMPLETED) {
716 printf("Card already partitioned\n");
717 return -EPERM;
718 }
719
720 if (mode == MMC_HWPART_CONF_CHECK)
721 return 0;
722
723 /* Partitioning requires high-capacity size definitions */
724 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
725 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
726 EXT_CSD_ERASE_GROUP_DEF, 1);
727
728 if (err)
729 return err;
730
731 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
732
733 /* update erase group size to be high-capacity */
734 mmc->erase_grp_size =
735 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
736
737 }
738
739 /* all OK, write the configuration */
740 for (i = 0; i < 4; i++) {
741 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
742 EXT_CSD_ENH_START_ADDR+i,
743 (enh_start_addr >> (i*8)) & 0xFF);
744 if (err)
745 return err;
746 }
747 for (i = 0; i < 3; i++) {
748 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
749 EXT_CSD_ENH_SIZE_MULT+i,
750 (enh_size_mult >> (i*8)) & 0xFF);
751 if (err)
752 return err;
753 }
754 for (pidx = 0; pidx < 4; pidx++) {
755 for (i = 0; i < 3; i++) {
756 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
757 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
758 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
759 if (err)
760 return err;
761 }
762 }
763 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
764 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
765 if (err)
766 return err;
767
768 if (mode == MMC_HWPART_CONF_SET)
769 return 0;
770
771 /* The WR_REL_SET is a write-once register but shall be
772 * written before setting PART_SETTING_COMPLETED. As it is
773 * write-once we can only write it when completing the
774 * partitioning. */
775 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
776 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
777 EXT_CSD_WR_REL_SET, wr_rel_set);
778 if (err)
779 return err;
780 }
781
782 /* Setting PART_SETTING_COMPLETED confirms the partition
783 * configuration but it only becomes effective after power
784 * cycle, so we do not adjust the partition related settings
785 * in the mmc struct. */
786
787 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
788 EXT_CSD_PARTITION_SETTING,
789 EXT_CSD_PARTITION_SETTING_COMPLETED);
790 if (err)
791 return err;
792
793 return 0;
794 }
795
796 #ifndef CONFIG_DM_MMC_OPS
797 int mmc_getcd(struct mmc *mmc)
798 {
799 int cd;
800
801 cd = board_mmc_getcd(mmc);
802
803 if (cd < 0) {
804 if (mmc->cfg->ops->getcd)
805 cd = mmc->cfg->ops->getcd(mmc);
806 else
807 cd = 1;
808 }
809
810 return cd;
811 }
812 #endif
813
814 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
815 {
816 struct mmc_cmd cmd;
817 struct mmc_data data;
818
819 /* Switch the frequency */
820 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
821 cmd.resp_type = MMC_RSP_R1;
822 cmd.cmdarg = (mode << 31) | 0xffffff;
823 cmd.cmdarg &= ~(0xf << (group * 4));
824 cmd.cmdarg |= value << (group * 4);
825
826 data.dest = (char *)resp;
827 data.blocksize = 64;
828 data.blocks = 1;
829 data.flags = MMC_DATA_READ;
830
831 return mmc_send_cmd(mmc, &cmd, &data);
832 }
833
834
835 static int sd_change_freq(struct mmc *mmc)
836 {
837 int err;
838 struct mmc_cmd cmd;
839 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
840 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
841 struct mmc_data data;
842 int timeout;
843
844 mmc->card_caps = 0;
845
846 if (mmc_host_is_spi(mmc))
847 return 0;
848
849 /* Read the SCR to find out if this card supports higher speeds */
850 cmd.cmdidx = MMC_CMD_APP_CMD;
851 cmd.resp_type = MMC_RSP_R1;
852 cmd.cmdarg = mmc->rca << 16;
853
854 err = mmc_send_cmd(mmc, &cmd, NULL);
855
856 if (err)
857 return err;
858
859 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
860 cmd.resp_type = MMC_RSP_R1;
861 cmd.cmdarg = 0;
862
863 timeout = 3;
864
865 retry_scr:
866 data.dest = (char *)scr;
867 data.blocksize = 8;
868 data.blocks = 1;
869 data.flags = MMC_DATA_READ;
870
871 err = mmc_send_cmd(mmc, &cmd, &data);
872
873 if (err) {
874 if (timeout--)
875 goto retry_scr;
876
877 return err;
878 }
879
880 mmc->scr[0] = __be32_to_cpu(scr[0]);
881 mmc->scr[1] = __be32_to_cpu(scr[1]);
882
883 switch ((mmc->scr[0] >> 24) & 0xf) {
884 case 0:
885 mmc->version = SD_VERSION_1_0;
886 break;
887 case 1:
888 mmc->version = SD_VERSION_1_10;
889 break;
890 case 2:
891 mmc->version = SD_VERSION_2;
892 if ((mmc->scr[0] >> 15) & 0x1)
893 mmc->version = SD_VERSION_3;
894 break;
895 default:
896 mmc->version = SD_VERSION_1_0;
897 break;
898 }
899
900 if (mmc->scr[0] & SD_DATA_4BIT)
901 mmc->card_caps |= MMC_MODE_4BIT;
902
903 /* Version 1.0 doesn't support switching */
904 if (mmc->version == SD_VERSION_1_0)
905 return 0;
906
907 timeout = 4;
908 while (timeout--) {
909 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
910 (u8 *)switch_status);
911
912 if (err)
913 return err;
914
915 /* The high-speed function is busy. Try again */
916 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
917 break;
918 }
919
920 /* If high-speed isn't supported, we return */
921 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
922 return 0;
923
924 /*
925 * If the host doesn't support SD_HIGHSPEED, do not switch card to
926 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
927 * This can avoid furthur problem when the card runs in different
928 * mode between the host.
929 */
930 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
931 (mmc->cfg->host_caps & MMC_MODE_HS)))
932 return 0;
933
934 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
935
936 if (err)
937 return err;
938
939 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
940 mmc->card_caps |= MMC_MODE_HS;
941
942 return 0;
943 }
944
945 /* frequency bases */
946 /* divided by 10 to be nice to platforms without floating point */
947 static const int fbase[] = {
948 10000,
949 100000,
950 1000000,
951 10000000,
952 };
953
954 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
955 * to platforms without floating point.
956 */
957 static const u8 multipliers[] = {
958 0, /* reserved */
959 10,
960 12,
961 13,
962 15,
963 20,
964 25,
965 30,
966 35,
967 40,
968 45,
969 50,
970 55,
971 60,
972 70,
973 80,
974 };
975
976 #ifndef CONFIG_DM_MMC_OPS
977 static void mmc_set_ios(struct mmc *mmc)
978 {
979 if (mmc->cfg->ops->set_ios)
980 mmc->cfg->ops->set_ios(mmc);
981 }
982 #endif
983
984 void mmc_set_clock(struct mmc *mmc, uint clock)
985 {
986 if (clock > mmc->cfg->f_max)
987 clock = mmc->cfg->f_max;
988
989 if (clock < mmc->cfg->f_min)
990 clock = mmc->cfg->f_min;
991
992 mmc->clock = clock;
993
994 mmc_set_ios(mmc);
995 }
996
997 static void mmc_set_bus_width(struct mmc *mmc, uint width)
998 {
999 mmc->bus_width = width;
1000
1001 mmc_set_ios(mmc);
1002 }
1003
1004 static int mmc_startup(struct mmc *mmc)
1005 {
1006 int err, i;
1007 uint mult, freq;
1008 u64 cmult, csize, capacity;
1009 struct mmc_cmd cmd;
1010 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1011 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1012 int timeout = 1000;
1013 bool has_parts = false;
1014 bool part_completed;
1015 struct blk_desc *bdesc;
1016
1017 #ifdef CONFIG_MMC_SPI_CRC_ON
1018 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1019 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1020 cmd.resp_type = MMC_RSP_R1;
1021 cmd.cmdarg = 1;
1022 err = mmc_send_cmd(mmc, &cmd, NULL);
1023
1024 if (err)
1025 return err;
1026 }
1027 #endif
1028
1029 /* Put the Card in Identify Mode */
1030 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1031 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
1032 cmd.resp_type = MMC_RSP_R2;
1033 cmd.cmdarg = 0;
1034
1035 err = mmc_send_cmd(mmc, &cmd, NULL);
1036
1037 if (err)
1038 return err;
1039
1040 memcpy(mmc->cid, cmd.response, 16);
1041
1042 /*
1043 * For MMC cards, set the Relative Address.
1044 * For SD cards, get the Relatvie Address.
1045 * This also puts the cards into Standby State
1046 */
1047 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1048 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1049 cmd.cmdarg = mmc->rca << 16;
1050 cmd.resp_type = MMC_RSP_R6;
1051
1052 err = mmc_send_cmd(mmc, &cmd, NULL);
1053
1054 if (err)
1055 return err;
1056
1057 if (IS_SD(mmc))
1058 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1059 }
1060
1061 /* Get the Card-Specific Data */
1062 cmd.cmdidx = MMC_CMD_SEND_CSD;
1063 cmd.resp_type = MMC_RSP_R2;
1064 cmd.cmdarg = mmc->rca << 16;
1065
1066 err = mmc_send_cmd(mmc, &cmd, NULL);
1067
1068 /* Waiting for the ready status */
1069 mmc_send_status(mmc, timeout);
1070
1071 if (err)
1072 return err;
1073
1074 mmc->csd[0] = cmd.response[0];
1075 mmc->csd[1] = cmd.response[1];
1076 mmc->csd[2] = cmd.response[2];
1077 mmc->csd[3] = cmd.response[3];
1078
1079 if (mmc->version == MMC_VERSION_UNKNOWN) {
1080 int version = (cmd.response[0] >> 26) & 0xf;
1081
1082 switch (version) {
1083 case 0:
1084 mmc->version = MMC_VERSION_1_2;
1085 break;
1086 case 1:
1087 mmc->version = MMC_VERSION_1_4;
1088 break;
1089 case 2:
1090 mmc->version = MMC_VERSION_2_2;
1091 break;
1092 case 3:
1093 mmc->version = MMC_VERSION_3;
1094 break;
1095 case 4:
1096 mmc->version = MMC_VERSION_4;
1097 break;
1098 default:
1099 mmc->version = MMC_VERSION_1_2;
1100 break;
1101 }
1102 }
1103
1104 /* divide frequency by 10, since the mults are 10x bigger */
1105 freq = fbase[(cmd.response[0] & 0x7)];
1106 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
1107
1108 mmc->tran_speed = freq * mult;
1109
1110 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
1111 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
1112
1113 if (IS_SD(mmc))
1114 mmc->write_bl_len = mmc->read_bl_len;
1115 else
1116 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
1117
1118 if (mmc->high_capacity) {
1119 csize = (mmc->csd[1] & 0x3f) << 16
1120 | (mmc->csd[2] & 0xffff0000) >> 16;
1121 cmult = 8;
1122 } else {
1123 csize = (mmc->csd[1] & 0x3ff) << 2
1124 | (mmc->csd[2] & 0xc0000000) >> 30;
1125 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1126 }
1127
1128 mmc->capacity_user = (csize + 1) << (cmult + 2);
1129 mmc->capacity_user *= mmc->read_bl_len;
1130 mmc->capacity_boot = 0;
1131 mmc->capacity_rpmb = 0;
1132 for (i = 0; i < 4; i++)
1133 mmc->capacity_gp[i] = 0;
1134
1135 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1136 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1137
1138 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1139 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1140
1141 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1142 cmd.cmdidx = MMC_CMD_SET_DSR;
1143 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1144 cmd.resp_type = MMC_RSP_NONE;
1145 if (mmc_send_cmd(mmc, &cmd, NULL))
1146 printf("MMC: SET_DSR failed\n");
1147 }
1148
1149 /* Select the card, and put it into Transfer Mode */
1150 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1151 cmd.cmdidx = MMC_CMD_SELECT_CARD;
1152 cmd.resp_type = MMC_RSP_R1;
1153 cmd.cmdarg = mmc->rca << 16;
1154 err = mmc_send_cmd(mmc, &cmd, NULL);
1155
1156 if (err)
1157 return err;
1158 }
1159
1160 /*
1161 * For SD, its erase group is always one sector
1162 */
1163 mmc->erase_grp_size = 1;
1164 mmc->part_config = MMCPART_NOAVAILABLE;
1165 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
1166 /* check ext_csd version and capacity */
1167 err = mmc_send_ext_csd(mmc, ext_csd);
1168 if (err)
1169 return err;
1170 if (ext_csd[EXT_CSD_REV] >= 2) {
1171 /*
1172 * According to the JEDEC Standard, the value of
1173 * ext_csd's capacity is valid if the value is more
1174 * than 2GB
1175 */
1176 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1177 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1178 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1179 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1180 capacity *= MMC_MAX_BLOCK_LEN;
1181 if ((capacity >> 20) > 2 * 1024)
1182 mmc->capacity_user = capacity;
1183 }
1184
1185 switch (ext_csd[EXT_CSD_REV]) {
1186 case 1:
1187 mmc->version = MMC_VERSION_4_1;
1188 break;
1189 case 2:
1190 mmc->version = MMC_VERSION_4_2;
1191 break;
1192 case 3:
1193 mmc->version = MMC_VERSION_4_3;
1194 break;
1195 case 5:
1196 mmc->version = MMC_VERSION_4_41;
1197 break;
1198 case 6:
1199 mmc->version = MMC_VERSION_4_5;
1200 break;
1201 case 7:
1202 mmc->version = MMC_VERSION_5_0;
1203 break;
1204 case 8:
1205 mmc->version = MMC_VERSION_5_1;
1206 break;
1207 }
1208
1209 /* The partition data may be non-zero but it is only
1210 * effective if PARTITION_SETTING_COMPLETED is set in
1211 * EXT_CSD, so ignore any data if this bit is not set,
1212 * except for enabling the high-capacity group size
1213 * definition (see below). */
1214 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1215 EXT_CSD_PARTITION_SETTING_COMPLETED);
1216
1217 /* store the partition info of emmc */
1218 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1219 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1220 ext_csd[EXT_CSD_BOOT_MULT])
1221 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1222 if (part_completed &&
1223 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
1224 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1225
1226 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1227
1228 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1229
1230 for (i = 0; i < 4; i++) {
1231 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1232 uint mult = (ext_csd[idx + 2] << 16) +
1233 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1234 if (mult)
1235 has_parts = true;
1236 if (!part_completed)
1237 continue;
1238 mmc->capacity_gp[i] = mult;
1239 mmc->capacity_gp[i] *=
1240 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1241 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1242 mmc->capacity_gp[i] <<= 19;
1243 }
1244
1245 if (part_completed) {
1246 mmc->enh_user_size =
1247 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
1248 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
1249 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1250 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1251 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1252 mmc->enh_user_size <<= 19;
1253 mmc->enh_user_start =
1254 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
1255 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
1256 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
1257 ext_csd[EXT_CSD_ENH_START_ADDR];
1258 if (mmc->high_capacity)
1259 mmc->enh_user_start <<= 9;
1260 }
1261
1262 /*
1263 * Host needs to enable ERASE_GRP_DEF bit if device is
1264 * partitioned. This bit will be lost every time after a reset
1265 * or power off. This will affect erase size.
1266 */
1267 if (part_completed)
1268 has_parts = true;
1269 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1270 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1271 has_parts = true;
1272 if (has_parts) {
1273 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1274 EXT_CSD_ERASE_GROUP_DEF, 1);
1275
1276 if (err)
1277 return err;
1278 else
1279 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1280 }
1281
1282 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1283 /* Read out group size from ext_csd */
1284 mmc->erase_grp_size =
1285 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1286 /*
1287 * if high capacity and partition setting completed
1288 * SEC_COUNT is valid even if it is smaller than 2 GiB
1289 * JEDEC Standard JESD84-B45, 6.2.4
1290 */
1291 if (mmc->high_capacity && part_completed) {
1292 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1293 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1294 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1295 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1296 capacity *= MMC_MAX_BLOCK_LEN;
1297 mmc->capacity_user = capacity;
1298 }
1299 } else {
1300 /* Calculate the group size from the csd value. */
1301 int erase_gsz, erase_gmul;
1302 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1303 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1304 mmc->erase_grp_size = (erase_gsz + 1)
1305 * (erase_gmul + 1);
1306 }
1307
1308 mmc->hc_wp_grp_size = 1024
1309 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1310 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1311
1312 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1313 }
1314
1315 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
1316 if (err)
1317 return err;
1318
1319 if (IS_SD(mmc))
1320 err = sd_change_freq(mmc);
1321 else
1322 err = mmc_change_freq(mmc);
1323
1324 if (err)
1325 return err;
1326
1327 /* Restrict card's capabilities by what the host can do */
1328 mmc->card_caps &= mmc->cfg->host_caps;
1329
1330 if (IS_SD(mmc)) {
1331 if (mmc->card_caps & MMC_MODE_4BIT) {
1332 cmd.cmdidx = MMC_CMD_APP_CMD;
1333 cmd.resp_type = MMC_RSP_R1;
1334 cmd.cmdarg = mmc->rca << 16;
1335
1336 err = mmc_send_cmd(mmc, &cmd, NULL);
1337 if (err)
1338 return err;
1339
1340 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1341 cmd.resp_type = MMC_RSP_R1;
1342 cmd.cmdarg = 2;
1343 err = mmc_send_cmd(mmc, &cmd, NULL);
1344 if (err)
1345 return err;
1346
1347 mmc_set_bus_width(mmc, 4);
1348 }
1349
1350 if (mmc->card_caps & MMC_MODE_HS)
1351 mmc->tran_speed = 50000000;
1352 else
1353 mmc->tran_speed = 25000000;
1354 } else if (mmc->version >= MMC_VERSION_4) {
1355 /* Only version 4 of MMC supports wider bus widths */
1356 int idx;
1357
1358 /* An array of possible bus widths in order of preference */
1359 static unsigned ext_csd_bits[] = {
1360 EXT_CSD_DDR_BUS_WIDTH_8,
1361 EXT_CSD_DDR_BUS_WIDTH_4,
1362 EXT_CSD_BUS_WIDTH_8,
1363 EXT_CSD_BUS_WIDTH_4,
1364 EXT_CSD_BUS_WIDTH_1,
1365 };
1366
1367 /* An array to map CSD bus widths to host cap bits */
1368 static unsigned ext_to_hostcaps[] = {
1369 [EXT_CSD_DDR_BUS_WIDTH_4] =
1370 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1371 [EXT_CSD_DDR_BUS_WIDTH_8] =
1372 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
1373 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1374 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1375 };
1376
1377 /* An array to map chosen bus width to an integer */
1378 static unsigned widths[] = {
1379 8, 4, 8, 4, 1,
1380 };
1381
1382 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1383 unsigned int extw = ext_csd_bits[idx];
1384 unsigned int caps = ext_to_hostcaps[extw];
1385
1386 /*
1387 * If the bus width is still not changed,
1388 * don't try to set the default again.
1389 * Otherwise, recover from switch attempts
1390 * by switching to 1-bit bus width.
1391 */
1392 if (extw == EXT_CSD_BUS_WIDTH_1 &&
1393 mmc->bus_width == 1) {
1394 err = 0;
1395 break;
1396 }
1397
1398 /*
1399 * Check to make sure the card and controller support
1400 * these capabilities
1401 */
1402 if ((mmc->card_caps & caps) != caps)
1403 continue;
1404
1405 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1406 EXT_CSD_BUS_WIDTH, extw);
1407
1408 if (err)
1409 continue;
1410
1411 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
1412 mmc_set_bus_width(mmc, widths[idx]);
1413
1414 err = mmc_send_ext_csd(mmc, test_csd);
1415
1416 if (err)
1417 continue;
1418
1419 /* Only compare read only fields */
1420 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1421 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1422 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1423 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1424 ext_csd[EXT_CSD_REV]
1425 == test_csd[EXT_CSD_REV] &&
1426 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1427 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1428 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1429 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1430 break;
1431 else
1432 err = SWITCH_ERR;
1433 }
1434
1435 if (err)
1436 return err;
1437
1438 if (mmc->card_caps & MMC_MODE_HS) {
1439 if (mmc->card_caps & MMC_MODE_HS_52MHz)
1440 mmc->tran_speed = 52000000;
1441 else
1442 mmc->tran_speed = 26000000;
1443 }
1444 }
1445
1446 mmc_set_clock(mmc, mmc->tran_speed);
1447
1448 /* Fix the block length for DDR mode */
1449 if (mmc->ddr_mode) {
1450 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1451 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1452 }
1453
1454 /* fill in device description */
1455 bdesc = mmc_get_blk_desc(mmc);
1456 bdesc->lun = 0;
1457 bdesc->hwpart = 0;
1458 bdesc->type = 0;
1459 bdesc->blksz = mmc->read_bl_len;
1460 bdesc->log2blksz = LOG2(bdesc->blksz);
1461 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
1462 #if !defined(CONFIG_SPL_BUILD) || \
1463 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
1464 !defined(CONFIG_USE_TINY_PRINTF))
1465 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
1466 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1467 (mmc->cid[3] >> 16) & 0xffff);
1468 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1469 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1470 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1471 (mmc->cid[2] >> 24) & 0xff);
1472 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1473 (mmc->cid[2] >> 16) & 0xf);
1474 #else
1475 bdesc->vendor[0] = 0;
1476 bdesc->product[0] = 0;
1477 bdesc->revision[0] = 0;
1478 #endif
1479 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
1480 part_init(bdesc);
1481 #endif
1482
1483 return 0;
1484 }
1485
1486 static int mmc_send_if_cond(struct mmc *mmc)
1487 {
1488 struct mmc_cmd cmd;
1489 int err;
1490
1491 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1492 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
1493 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
1494 cmd.resp_type = MMC_RSP_R7;
1495
1496 err = mmc_send_cmd(mmc, &cmd, NULL);
1497
1498 if (err)
1499 return err;
1500
1501 if ((cmd.response[0] & 0xff) != 0xaa)
1502 return UNUSABLE_ERR;
1503 else
1504 mmc->version = SD_VERSION_2;
1505
1506 return 0;
1507 }
1508
1509 /* board-specific MMC power initializations. */
1510 __weak void board_mmc_power_init(void)
1511 {
1512 }
1513
1514 int mmc_start_init(struct mmc *mmc)
1515 {
1516 bool no_card;
1517 int err;
1518
1519 /* we pretend there's no card when init is NULL */
1520 no_card = mmc_getcd(mmc) == 0;
1521 #ifndef CONFIG_DM_MMC_OPS
1522 no_card = no_card || (mmc->cfg->ops->init == NULL);
1523 #endif
1524 if (no_card) {
1525 mmc->has_init = 0;
1526 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1527 printf("MMC: no card present\n");
1528 #endif
1529 return NO_CARD_ERR;
1530 }
1531
1532 if (mmc->has_init)
1533 return 0;
1534
1535 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1536 mmc_adapter_card_type_ident();
1537 #endif
1538 board_mmc_power_init();
1539
1540 #ifdef CONFIG_DM_MMC_OPS
1541 /* The device has already been probed ready for use */
1542 #else
1543 /* made sure it's not NULL earlier */
1544 err = mmc->cfg->ops->init(mmc);
1545 if (err)
1546 return err;
1547 #endif
1548 mmc->ddr_mode = 0;
1549 mmc_set_bus_width(mmc, 1);
1550 mmc_set_clock(mmc, 1);
1551
1552 /* Reset the Card */
1553 err = mmc_go_idle(mmc);
1554
1555 if (err)
1556 return err;
1557
1558 /* The internal partition reset to user partition(0) at every CMD0*/
1559 mmc_get_blk_desc(mmc)->hwpart = 0;
1560
1561 /* Test for SD version 2 */
1562 err = mmc_send_if_cond(mmc);
1563
1564 /* Now try to get the SD card's operating condition */
1565 err = sd_send_op_cond(mmc);
1566
1567 /* If the command timed out, we check for an MMC card */
1568 if (err == TIMEOUT) {
1569 err = mmc_send_op_cond(mmc);
1570
1571 if (err) {
1572 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1573 printf("Card did not respond to voltage select!\n");
1574 #endif
1575 return UNUSABLE_ERR;
1576 }
1577 }
1578
1579 if (!err)
1580 mmc->init_in_progress = 1;
1581
1582 return err;
1583 }
1584
1585 static int mmc_complete_init(struct mmc *mmc)
1586 {
1587 int err = 0;
1588
1589 mmc->init_in_progress = 0;
1590 if (mmc->op_cond_pending)
1591 err = mmc_complete_op_cond(mmc);
1592
1593 if (!err)
1594 err = mmc_startup(mmc);
1595 if (err)
1596 mmc->has_init = 0;
1597 else
1598 mmc->has_init = 1;
1599 return err;
1600 }
1601
1602 int mmc_init(struct mmc *mmc)
1603 {
1604 int err = 0;
1605 unsigned start;
1606 #ifdef CONFIG_DM_MMC
1607 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
1608
1609 upriv->mmc = mmc;
1610 #endif
1611 if (mmc->has_init)
1612 return 0;
1613
1614 start = get_timer(0);
1615
1616 if (!mmc->init_in_progress)
1617 err = mmc_start_init(mmc);
1618
1619 if (!err)
1620 err = mmc_complete_init(mmc);
1621 debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
1622 return err;
1623 }
1624
1625 int mmc_set_dsr(struct mmc *mmc, u16 val)
1626 {
1627 mmc->dsr = val;
1628 return 0;
1629 }
1630
1631 /* CPU-specific MMC initializations */
1632 __weak int cpu_mmc_init(bd_t *bis)
1633 {
1634 return -1;
1635 }
1636
1637 /* board-specific MMC initializations. */
1638 __weak int board_mmc_init(bd_t *bis)
1639 {
1640 return -1;
1641 }
1642
1643 void mmc_set_preinit(struct mmc *mmc, int preinit)
1644 {
1645 mmc->preinit = preinit;
1646 }
1647
1648 #if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD)
1649 static int mmc_probe(bd_t *bis)
1650 {
1651 return 0;
1652 }
1653 #elif defined(CONFIG_DM_MMC)
1654 static int mmc_probe(bd_t *bis)
1655 {
1656 int ret, i;
1657 struct uclass *uc;
1658 struct udevice *dev;
1659
1660 ret = uclass_get(UCLASS_MMC, &uc);
1661 if (ret)
1662 return ret;
1663
1664 /*
1665 * Try to add them in sequence order. Really with driver model we
1666 * should allow holes, but the current MMC list does not allow that.
1667 * So if we request 0, 1, 3 we will get 0, 1, 2.
1668 */
1669 for (i = 0; ; i++) {
1670 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
1671 if (ret == -ENODEV)
1672 break;
1673 }
1674 uclass_foreach_dev(dev, uc) {
1675 ret = device_probe(dev);
1676 if (ret)
1677 printf("%s - probe failed: %d\n", dev->name, ret);
1678 }
1679
1680 return 0;
1681 }
1682 #else
1683 static int mmc_probe(bd_t *bis)
1684 {
1685 if (board_mmc_init(bis) < 0)
1686 cpu_mmc_init(bis);
1687
1688 return 0;
1689 }
1690 #endif
1691
1692 int mmc_initialize(bd_t *bis)
1693 {
1694 static int initialized = 0;
1695 int ret;
1696 if (initialized) /* Avoid initializing mmc multiple times */
1697 return 0;
1698 initialized = 1;
1699
1700 #ifndef CONFIG_BLK
1701 mmc_list_init();
1702 #endif
1703 ret = mmc_probe(bis);
1704 if (ret)
1705 return ret;
1706
1707 #ifndef CONFIG_SPL_BUILD
1708 print_mmc_devices(',');
1709 #endif
1710
1711 mmc_do_preinit();
1712 return 0;
1713 }
"Das U-Boot" Source Tree