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mmc: refactor SD startup to make it easier to support new modes
[people/ms/u-boot.git] / drivers / mmc / mmc.c
1 /*
2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based vaguely on the Linux code
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #include <config.h>
11 #include <common.h>
12 #include <command.h>
13 #include <dm.h>
14 #include <dm/device-internal.h>
15 #include <errno.h>
16 #include <mmc.h>
17 #include <part.h>
18 #include <power/regulator.h>
19 #include <malloc.h>
20 #include <memalign.h>
21 #include <linux/list.h>
22 #include <div64.h>
23 #include "mmc_private.h"
24
25 static const unsigned int sd_au_size[] = {
26 0, SZ_16K / 512, SZ_32K / 512,
27 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
28 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
29 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
30 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512,
31 };
32
33 #if CONFIG_IS_ENABLED(MMC_TINY)
34 static struct mmc mmc_static;
35 struct mmc *find_mmc_device(int dev_num)
36 {
37 return &mmc_static;
38 }
39
40 void mmc_do_preinit(void)
41 {
42 struct mmc *m = &mmc_static;
43 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
44 mmc_set_preinit(m, 1);
45 #endif
46 if (m->preinit)
47 mmc_start_init(m);
48 }
49
50 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
51 {
52 return &mmc->block_dev;
53 }
54 #endif
55
56 #if !CONFIG_IS_ENABLED(DM_MMC)
57 __weak int board_mmc_getwp(struct mmc *mmc)
58 {
59 return -1;
60 }
61
62 int mmc_getwp(struct mmc *mmc)
63 {
64 int wp;
65
66 wp = board_mmc_getwp(mmc);
67
68 if (wp < 0) {
69 if (mmc->cfg->ops->getwp)
70 wp = mmc->cfg->ops->getwp(mmc);
71 else
72 wp = 0;
73 }
74
75 return wp;
76 }
77
78 __weak int board_mmc_getcd(struct mmc *mmc)
79 {
80 return -1;
81 }
82 #endif
83
84 #ifdef CONFIG_MMC_TRACE
85 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
86 {
87 printf("CMD_SEND:%d\n", cmd->cmdidx);
88 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
89 }
90
91 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
92 {
93 int i;
94 u8 *ptr;
95
96 if (ret) {
97 printf("\t\tRET\t\t\t %d\n", ret);
98 } else {
99 switch (cmd->resp_type) {
100 case MMC_RSP_NONE:
101 printf("\t\tMMC_RSP_NONE\n");
102 break;
103 case MMC_RSP_R1:
104 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
105 cmd->response[0]);
106 break;
107 case MMC_RSP_R1b:
108 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
109 cmd->response[0]);
110 break;
111 case MMC_RSP_R2:
112 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
113 cmd->response[0]);
114 printf("\t\t \t\t 0x%08X \n",
115 cmd->response[1]);
116 printf("\t\t \t\t 0x%08X \n",
117 cmd->response[2]);
118 printf("\t\t \t\t 0x%08X \n",
119 cmd->response[3]);
120 printf("\n");
121 printf("\t\t\t\t\tDUMPING DATA\n");
122 for (i = 0; i < 4; i++) {
123 int j;
124 printf("\t\t\t\t\t%03d - ", i*4);
125 ptr = (u8 *)&cmd->response[i];
126 ptr += 3;
127 for (j = 0; j < 4; j++)
128 printf("%02X ", *ptr--);
129 printf("\n");
130 }
131 break;
132 case MMC_RSP_R3:
133 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
134 cmd->response[0]);
135 break;
136 default:
137 printf("\t\tERROR MMC rsp not supported\n");
138 break;
139 }
140 }
141 }
142
143 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
144 {
145 int status;
146
147 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
148 printf("CURR STATE:%d\n", status);
149 }
150 #endif
151
152 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
153 const char *mmc_mode_name(enum bus_mode mode)
154 {
155 static const char *const names[] = {
156 [MMC_LEGACY] = "MMC legacy",
157 [SD_LEGACY] = "SD Legacy",
158 [MMC_HS] = "MMC High Speed (26MHz)",
159 [SD_HS] = "SD High Speed (50MHz)",
160 [UHS_SDR12] = "UHS SDR12 (25MHz)",
161 [UHS_SDR25] = "UHS SDR25 (50MHz)",
162 [UHS_SDR50] = "UHS SDR50 (100MHz)",
163 [UHS_SDR104] = "UHS SDR104 (208MHz)",
164 [UHS_DDR50] = "UHS DDR50 (50MHz)",
165 [MMC_HS_52] = "MMC High Speed (52MHz)",
166 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
167 [MMC_HS_200] = "HS200 (200MHz)",
168 };
169
170 if (mode >= MMC_MODES_END)
171 return "Unknown mode";
172 else
173 return names[mode];
174 }
175 #endif
176
177 static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
178 {
179 static const int freqs[] = {
180 [SD_LEGACY] = 25000000,
181 [MMC_HS] = 26000000,
182 [SD_HS] = 50000000,
183 [UHS_SDR12] = 25000000,
184 [UHS_SDR25] = 50000000,
185 [UHS_SDR50] = 100000000,
186 [UHS_SDR104] = 208000000,
187 [UHS_DDR50] = 50000000,
188 [MMC_HS_52] = 52000000,
189 [MMC_DDR_52] = 52000000,
190 [MMC_HS_200] = 200000000,
191 };
192
193 if (mode == MMC_LEGACY)
194 return mmc->legacy_speed;
195 else if (mode >= MMC_MODES_END)
196 return 0;
197 else
198 return freqs[mode];
199 }
200
201 static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
202 {
203 mmc->selected_mode = mode;
204 mmc->tran_speed = mmc_mode2freq(mmc, mode);
205 debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
206 mmc->tran_speed / 1000000);
207 return 0;
208 }
209
210 #if !CONFIG_IS_ENABLED(DM_MMC)
211 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
212 {
213 int ret;
214
215 mmmc_trace_before_send(mmc, cmd);
216 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
217 mmmc_trace_after_send(mmc, cmd, ret);
218
219 return ret;
220 }
221 #endif
222
223 int mmc_send_status(struct mmc *mmc, int timeout)
224 {
225 struct mmc_cmd cmd;
226 int err, retries = 5;
227
228 cmd.cmdidx = MMC_CMD_SEND_STATUS;
229 cmd.resp_type = MMC_RSP_R1;
230 if (!mmc_host_is_spi(mmc))
231 cmd.cmdarg = mmc->rca << 16;
232
233 while (1) {
234 err = mmc_send_cmd(mmc, &cmd, NULL);
235 if (!err) {
236 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
237 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
238 MMC_STATE_PRG)
239 break;
240
241 if (cmd.response[0] & MMC_STATUS_MASK) {
242 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
243 printf("Status Error: 0x%08X\n",
244 cmd.response[0]);
245 #endif
246 return -ECOMM;
247 }
248 } else if (--retries < 0)
249 return err;
250
251 if (timeout-- <= 0)
252 break;
253
254 udelay(1000);
255 }
256
257 mmc_trace_state(mmc, &cmd);
258 if (timeout <= 0) {
259 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
260 printf("Timeout waiting card ready\n");
261 #endif
262 return -ETIMEDOUT;
263 }
264
265 return 0;
266 }
267
268 int mmc_set_blocklen(struct mmc *mmc, int len)
269 {
270 struct mmc_cmd cmd;
271
272 if (mmc->ddr_mode)
273 return 0;
274
275 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
276 cmd.resp_type = MMC_RSP_R1;
277 cmd.cmdarg = len;
278
279 return mmc_send_cmd(mmc, &cmd, NULL);
280 }
281
282 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
283 lbaint_t blkcnt)
284 {
285 struct mmc_cmd cmd;
286 struct mmc_data data;
287
288 if (blkcnt > 1)
289 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
290 else
291 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
292
293 if (mmc->high_capacity)
294 cmd.cmdarg = start;
295 else
296 cmd.cmdarg = start * mmc->read_bl_len;
297
298 cmd.resp_type = MMC_RSP_R1;
299
300 data.dest = dst;
301 data.blocks = blkcnt;
302 data.blocksize = mmc->read_bl_len;
303 data.flags = MMC_DATA_READ;
304
305 if (mmc_send_cmd(mmc, &cmd, &data))
306 return 0;
307
308 if (blkcnt > 1) {
309 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
310 cmd.cmdarg = 0;
311 cmd.resp_type = MMC_RSP_R1b;
312 if (mmc_send_cmd(mmc, &cmd, NULL)) {
313 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
314 printf("mmc fail to send stop cmd\n");
315 #endif
316 return 0;
317 }
318 }
319
320 return blkcnt;
321 }
322
323 #if CONFIG_IS_ENABLED(BLK)
324 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
325 #else
326 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
327 void *dst)
328 #endif
329 {
330 #if CONFIG_IS_ENABLED(BLK)
331 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
332 #endif
333 int dev_num = block_dev->devnum;
334 int err;
335 lbaint_t cur, blocks_todo = blkcnt;
336
337 if (blkcnt == 0)
338 return 0;
339
340 struct mmc *mmc = find_mmc_device(dev_num);
341 if (!mmc)
342 return 0;
343
344 if (CONFIG_IS_ENABLED(MMC_TINY))
345 err = mmc_switch_part(mmc, block_dev->hwpart);
346 else
347 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
348
349 if (err < 0)
350 return 0;
351
352 if ((start + blkcnt) > block_dev->lba) {
353 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
354 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
355 start + blkcnt, block_dev->lba);
356 #endif
357 return 0;
358 }
359
360 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
361 debug("%s: Failed to set blocklen\n", __func__);
362 return 0;
363 }
364
365 do {
366 cur = (blocks_todo > mmc->cfg->b_max) ?
367 mmc->cfg->b_max : blocks_todo;
368 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
369 debug("%s: Failed to read blocks\n", __func__);
370 return 0;
371 }
372 blocks_todo -= cur;
373 start += cur;
374 dst += cur * mmc->read_bl_len;
375 } while (blocks_todo > 0);
376
377 return blkcnt;
378 }
379
380 static int mmc_go_idle(struct mmc *mmc)
381 {
382 struct mmc_cmd cmd;
383 int err;
384
385 udelay(1000);
386
387 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
388 cmd.cmdarg = 0;
389 cmd.resp_type = MMC_RSP_NONE;
390
391 err = mmc_send_cmd(mmc, &cmd, NULL);
392
393 if (err)
394 return err;
395
396 udelay(2000);
397
398 return 0;
399 }
400
401 static int sd_send_op_cond(struct mmc *mmc)
402 {
403 int timeout = 1000;
404 int err;
405 struct mmc_cmd cmd;
406
407 while (1) {
408 cmd.cmdidx = MMC_CMD_APP_CMD;
409 cmd.resp_type = MMC_RSP_R1;
410 cmd.cmdarg = 0;
411
412 err = mmc_send_cmd(mmc, &cmd, NULL);
413
414 if (err)
415 return err;
416
417 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
418 cmd.resp_type = MMC_RSP_R3;
419
420 /*
421 * Most cards do not answer if some reserved bits
422 * in the ocr are set. However, Some controller
423 * can set bit 7 (reserved for low voltages), but
424 * how to manage low voltages SD card is not yet
425 * specified.
426 */
427 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
428 (mmc->cfg->voltages & 0xff8000);
429
430 if (mmc->version == SD_VERSION_2)
431 cmd.cmdarg |= OCR_HCS;
432
433 err = mmc_send_cmd(mmc, &cmd, NULL);
434
435 if (err)
436 return err;
437
438 if (cmd.response[0] & OCR_BUSY)
439 break;
440
441 if (timeout-- <= 0)
442 return -EOPNOTSUPP;
443
444 udelay(1000);
445 }
446
447 if (mmc->version != SD_VERSION_2)
448 mmc->version = SD_VERSION_1_0;
449
450 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
451 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
452 cmd.resp_type = MMC_RSP_R3;
453 cmd.cmdarg = 0;
454
455 err = mmc_send_cmd(mmc, &cmd, NULL);
456
457 if (err)
458 return err;
459 }
460
461 mmc->ocr = cmd.response[0];
462
463 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
464 mmc->rca = 0;
465
466 return 0;
467 }
468
469 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
470 {
471 struct mmc_cmd cmd;
472 int err;
473
474 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
475 cmd.resp_type = MMC_RSP_R3;
476 cmd.cmdarg = 0;
477 if (use_arg && !mmc_host_is_spi(mmc))
478 cmd.cmdarg = OCR_HCS |
479 (mmc->cfg->voltages &
480 (mmc->ocr & OCR_VOLTAGE_MASK)) |
481 (mmc->ocr & OCR_ACCESS_MODE);
482
483 err = mmc_send_cmd(mmc, &cmd, NULL);
484 if (err)
485 return err;
486 mmc->ocr = cmd.response[0];
487 return 0;
488 }
489
490 static int mmc_send_op_cond(struct mmc *mmc)
491 {
492 int err, i;
493
494 /* Some cards seem to need this */
495 mmc_go_idle(mmc);
496
497 /* Asking to the card its capabilities */
498 for (i = 0; i < 2; i++) {
499 err = mmc_send_op_cond_iter(mmc, i != 0);
500 if (err)
501 return err;
502
503 /* exit if not busy (flag seems to be inverted) */
504 if (mmc->ocr & OCR_BUSY)
505 break;
506 }
507 mmc->op_cond_pending = 1;
508 return 0;
509 }
510
511 static int mmc_complete_op_cond(struct mmc *mmc)
512 {
513 struct mmc_cmd cmd;
514 int timeout = 1000;
515 uint start;
516 int err;
517
518 mmc->op_cond_pending = 0;
519 if (!(mmc->ocr & OCR_BUSY)) {
520 /* Some cards seem to need this */
521 mmc_go_idle(mmc);
522
523 start = get_timer(0);
524 while (1) {
525 err = mmc_send_op_cond_iter(mmc, 1);
526 if (err)
527 return err;
528 if (mmc->ocr & OCR_BUSY)
529 break;
530 if (get_timer(start) > timeout)
531 return -EOPNOTSUPP;
532 udelay(100);
533 }
534 }
535
536 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
537 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
538 cmd.resp_type = MMC_RSP_R3;
539 cmd.cmdarg = 0;
540
541 err = mmc_send_cmd(mmc, &cmd, NULL);
542
543 if (err)
544 return err;
545
546 mmc->ocr = cmd.response[0];
547 }
548
549 mmc->version = MMC_VERSION_UNKNOWN;
550
551 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
552 mmc->rca = 1;
553
554 return 0;
555 }
556
557
558 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
559 {
560 struct mmc_cmd cmd;
561 struct mmc_data data;
562 int err;
563
564 /* Get the Card Status Register */
565 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
566 cmd.resp_type = MMC_RSP_R1;
567 cmd.cmdarg = 0;
568
569 data.dest = (char *)ext_csd;
570 data.blocks = 1;
571 data.blocksize = MMC_MAX_BLOCK_LEN;
572 data.flags = MMC_DATA_READ;
573
574 err = mmc_send_cmd(mmc, &cmd, &data);
575
576 return err;
577 }
578
579 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
580 {
581 struct mmc_cmd cmd;
582 int timeout = 1000;
583 int retries = 3;
584 int ret;
585
586 cmd.cmdidx = MMC_CMD_SWITCH;
587 cmd.resp_type = MMC_RSP_R1b;
588 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
589 (index << 16) |
590 (value << 8);
591
592 while (retries > 0) {
593 ret = mmc_send_cmd(mmc, &cmd, NULL);
594
595 /* Waiting for the ready status */
596 if (!ret) {
597 ret = mmc_send_status(mmc, timeout);
598 return ret;
599 }
600
601 retries--;
602 }
603
604 return ret;
605
606 }
607
608 static int mmc_change_freq(struct mmc *mmc)
609 {
610 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
611 char cardtype;
612 int err;
613
614 mmc->card_caps = MMC_MODE_1BIT;
615
616 if (mmc_host_is_spi(mmc))
617 return 0;
618
619 /* Only version 4 supports high-speed */
620 if (mmc->version < MMC_VERSION_4)
621 return 0;
622
623 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
624
625 err = mmc_send_ext_csd(mmc, ext_csd);
626
627 if (err)
628 return err;
629
630 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
631
632 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
633
634 if (err)
635 return err;
636
637 /* Now check to see that it worked */
638 err = mmc_send_ext_csd(mmc, ext_csd);
639
640 if (err)
641 return err;
642
643 /* No high-speed support */
644 if (!ext_csd[EXT_CSD_HS_TIMING])
645 return 0;
646
647 /* High Speed is set, there are two types: 52MHz and 26MHz */
648 if (cardtype & EXT_CSD_CARD_TYPE_52) {
649 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
650 mmc->card_caps |= MMC_MODE_DDR_52MHz;
651 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
652 } else {
653 mmc->card_caps |= MMC_MODE_HS;
654 }
655
656 return 0;
657 }
658
659 static int mmc_set_capacity(struct mmc *mmc, int part_num)
660 {
661 switch (part_num) {
662 case 0:
663 mmc->capacity = mmc->capacity_user;
664 break;
665 case 1:
666 case 2:
667 mmc->capacity = mmc->capacity_boot;
668 break;
669 case 3:
670 mmc->capacity = mmc->capacity_rpmb;
671 break;
672 case 4:
673 case 5:
674 case 6:
675 case 7:
676 mmc->capacity = mmc->capacity_gp[part_num - 4];
677 break;
678 default:
679 return -1;
680 }
681
682 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
683
684 return 0;
685 }
686
687 int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
688 {
689 int ret;
690
691 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
692 (mmc->part_config & ~PART_ACCESS_MASK)
693 | (part_num & PART_ACCESS_MASK));
694
695 /*
696 * Set the capacity if the switch succeeded or was intended
697 * to return to representing the raw device.
698 */
699 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
700 ret = mmc_set_capacity(mmc, part_num);
701 mmc_get_blk_desc(mmc)->hwpart = part_num;
702 }
703
704 return ret;
705 }
706
707 int mmc_hwpart_config(struct mmc *mmc,
708 const struct mmc_hwpart_conf *conf,
709 enum mmc_hwpart_conf_mode mode)
710 {
711 u8 part_attrs = 0;
712 u32 enh_size_mult;
713 u32 enh_start_addr;
714 u32 gp_size_mult[4];
715 u32 max_enh_size_mult;
716 u32 tot_enh_size_mult = 0;
717 u8 wr_rel_set;
718 int i, pidx, err;
719 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
720
721 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
722 return -EINVAL;
723
724 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
725 printf("eMMC >= 4.4 required for enhanced user data area\n");
726 return -EMEDIUMTYPE;
727 }
728
729 if (!(mmc->part_support & PART_SUPPORT)) {
730 printf("Card does not support partitioning\n");
731 return -EMEDIUMTYPE;
732 }
733
734 if (!mmc->hc_wp_grp_size) {
735 printf("Card does not define HC WP group size\n");
736 return -EMEDIUMTYPE;
737 }
738
739 /* check partition alignment and total enhanced size */
740 if (conf->user.enh_size) {
741 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
742 conf->user.enh_start % mmc->hc_wp_grp_size) {
743 printf("User data enhanced area not HC WP group "
744 "size aligned\n");
745 return -EINVAL;
746 }
747 part_attrs |= EXT_CSD_ENH_USR;
748 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
749 if (mmc->high_capacity) {
750 enh_start_addr = conf->user.enh_start;
751 } else {
752 enh_start_addr = (conf->user.enh_start << 9);
753 }
754 } else {
755 enh_size_mult = 0;
756 enh_start_addr = 0;
757 }
758 tot_enh_size_mult += enh_size_mult;
759
760 for (pidx = 0; pidx < 4; pidx++) {
761 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
762 printf("GP%i partition not HC WP group size "
763 "aligned\n", pidx+1);
764 return -EINVAL;
765 }
766 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
767 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
768 part_attrs |= EXT_CSD_ENH_GP(pidx);
769 tot_enh_size_mult += gp_size_mult[pidx];
770 }
771 }
772
773 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
774 printf("Card does not support enhanced attribute\n");
775 return -EMEDIUMTYPE;
776 }
777
778 err = mmc_send_ext_csd(mmc, ext_csd);
779 if (err)
780 return err;
781
782 max_enh_size_mult =
783 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
784 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
785 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
786 if (tot_enh_size_mult > max_enh_size_mult) {
787 printf("Total enhanced size exceeds maximum (%u > %u)\n",
788 tot_enh_size_mult, max_enh_size_mult);
789 return -EMEDIUMTYPE;
790 }
791
792 /* The default value of EXT_CSD_WR_REL_SET is device
793 * dependent, the values can only be changed if the
794 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
795 * changed only once and before partitioning is completed. */
796 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
797 if (conf->user.wr_rel_change) {
798 if (conf->user.wr_rel_set)
799 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
800 else
801 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
802 }
803 for (pidx = 0; pidx < 4; pidx++) {
804 if (conf->gp_part[pidx].wr_rel_change) {
805 if (conf->gp_part[pidx].wr_rel_set)
806 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
807 else
808 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
809 }
810 }
811
812 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
813 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
814 puts("Card does not support host controlled partition write "
815 "reliability settings\n");
816 return -EMEDIUMTYPE;
817 }
818
819 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
820 EXT_CSD_PARTITION_SETTING_COMPLETED) {
821 printf("Card already partitioned\n");
822 return -EPERM;
823 }
824
825 if (mode == MMC_HWPART_CONF_CHECK)
826 return 0;
827
828 /* Partitioning requires high-capacity size definitions */
829 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
830 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
831 EXT_CSD_ERASE_GROUP_DEF, 1);
832
833 if (err)
834 return err;
835
836 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
837
838 /* update erase group size to be high-capacity */
839 mmc->erase_grp_size =
840 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
841
842 }
843
844 /* all OK, write the configuration */
845 for (i = 0; i < 4; i++) {
846 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
847 EXT_CSD_ENH_START_ADDR+i,
848 (enh_start_addr >> (i*8)) & 0xFF);
849 if (err)
850 return err;
851 }
852 for (i = 0; i < 3; i++) {
853 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
854 EXT_CSD_ENH_SIZE_MULT+i,
855 (enh_size_mult >> (i*8)) & 0xFF);
856 if (err)
857 return err;
858 }
859 for (pidx = 0; pidx < 4; pidx++) {
860 for (i = 0; i < 3; i++) {
861 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
862 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
863 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
864 if (err)
865 return err;
866 }
867 }
868 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
869 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
870 if (err)
871 return err;
872
873 if (mode == MMC_HWPART_CONF_SET)
874 return 0;
875
876 /* The WR_REL_SET is a write-once register but shall be
877 * written before setting PART_SETTING_COMPLETED. As it is
878 * write-once we can only write it when completing the
879 * partitioning. */
880 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
881 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
882 EXT_CSD_WR_REL_SET, wr_rel_set);
883 if (err)
884 return err;
885 }
886
887 /* Setting PART_SETTING_COMPLETED confirms the partition
888 * configuration but it only becomes effective after power
889 * cycle, so we do not adjust the partition related settings
890 * in the mmc struct. */
891
892 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
893 EXT_CSD_PARTITION_SETTING,
894 EXT_CSD_PARTITION_SETTING_COMPLETED);
895 if (err)
896 return err;
897
898 return 0;
899 }
900
901 #if !CONFIG_IS_ENABLED(DM_MMC)
902 int mmc_getcd(struct mmc *mmc)
903 {
904 int cd;
905
906 cd = board_mmc_getcd(mmc);
907
908 if (cd < 0) {
909 if (mmc->cfg->ops->getcd)
910 cd = mmc->cfg->ops->getcd(mmc);
911 else
912 cd = 1;
913 }
914
915 return cd;
916 }
917 #endif
918
919 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
920 {
921 struct mmc_cmd cmd;
922 struct mmc_data data;
923
924 /* Switch the frequency */
925 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
926 cmd.resp_type = MMC_RSP_R1;
927 cmd.cmdarg = (mode << 31) | 0xffffff;
928 cmd.cmdarg &= ~(0xf << (group * 4));
929 cmd.cmdarg |= value << (group * 4);
930
931 data.dest = (char *)resp;
932 data.blocksize = 64;
933 data.blocks = 1;
934 data.flags = MMC_DATA_READ;
935
936 return mmc_send_cmd(mmc, &cmd, &data);
937 }
938
939
940 static int sd_get_capabilities(struct mmc *mmc)
941 {
942 int err;
943 struct mmc_cmd cmd;
944 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
945 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
946 struct mmc_data data;
947 int timeout;
948
949 mmc->card_caps = MMC_MODE_1BIT;
950
951 if (mmc_host_is_spi(mmc))
952 return 0;
953
954 /* Read the SCR to find out if this card supports higher speeds */
955 cmd.cmdidx = MMC_CMD_APP_CMD;
956 cmd.resp_type = MMC_RSP_R1;
957 cmd.cmdarg = mmc->rca << 16;
958
959 err = mmc_send_cmd(mmc, &cmd, NULL);
960
961 if (err)
962 return err;
963
964 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
965 cmd.resp_type = MMC_RSP_R1;
966 cmd.cmdarg = 0;
967
968 timeout = 3;
969
970 retry_scr:
971 data.dest = (char *)scr;
972 data.blocksize = 8;
973 data.blocks = 1;
974 data.flags = MMC_DATA_READ;
975
976 err = mmc_send_cmd(mmc, &cmd, &data);
977
978 if (err) {
979 if (timeout--)
980 goto retry_scr;
981
982 return err;
983 }
984
985 mmc->scr[0] = __be32_to_cpu(scr[0]);
986 mmc->scr[1] = __be32_to_cpu(scr[1]);
987
988 switch ((mmc->scr[0] >> 24) & 0xf) {
989 case 0:
990 mmc->version = SD_VERSION_1_0;
991 break;
992 case 1:
993 mmc->version = SD_VERSION_1_10;
994 break;
995 case 2:
996 mmc->version = SD_VERSION_2;
997 if ((mmc->scr[0] >> 15) & 0x1)
998 mmc->version = SD_VERSION_3;
999 break;
1000 default:
1001 mmc->version = SD_VERSION_1_0;
1002 break;
1003 }
1004
1005 if (mmc->scr[0] & SD_DATA_4BIT)
1006 mmc->card_caps |= MMC_MODE_4BIT;
1007
1008 /* Version 1.0 doesn't support switching */
1009 if (mmc->version == SD_VERSION_1_0)
1010 return 0;
1011
1012 timeout = 4;
1013 while (timeout--) {
1014 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
1015 (u8 *)switch_status);
1016
1017 if (err)
1018 return err;
1019
1020 /* The high-speed function is busy. Try again */
1021 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
1022 break;
1023 }
1024
1025 /* If high-speed isn't supported, we return */
1026 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1027 mmc->card_caps |= MMC_CAP(SD_HS);
1028
1029 return 0;
1030 }
1031
1032 static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1033 {
1034 int err;
1035
1036 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
1037
1038 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
1039 if (err)
1040 return err;
1041
1042 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) != 0x01000000)
1043 return -ENOTSUPP;
1044
1045 return 0;
1046 }
1047
1048 int sd_select_bus_width(struct mmc *mmc, int w)
1049 {
1050 int err;
1051 struct mmc_cmd cmd;
1052
1053 if ((w != 4) && (w != 1))
1054 return -EINVAL;
1055
1056 cmd.cmdidx = MMC_CMD_APP_CMD;
1057 cmd.resp_type = MMC_RSP_R1;
1058 cmd.cmdarg = mmc->rca << 16;
1059
1060 err = mmc_send_cmd(mmc, &cmd, NULL);
1061 if (err)
1062 return err;
1063
1064 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1065 cmd.resp_type = MMC_RSP_R1;
1066 if (w == 4)
1067 cmd.cmdarg = 2;
1068 else if (w == 1)
1069 cmd.cmdarg = 0;
1070 err = mmc_send_cmd(mmc, &cmd, NULL);
1071 if (err)
1072 return err;
1073
1074 return 0;
1075 }
1076
1077 static int sd_read_ssr(struct mmc *mmc)
1078 {
1079 int err, i;
1080 struct mmc_cmd cmd;
1081 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1082 struct mmc_data data;
1083 int timeout = 3;
1084 unsigned int au, eo, et, es;
1085
1086 cmd.cmdidx = MMC_CMD_APP_CMD;
1087 cmd.resp_type = MMC_RSP_R1;
1088 cmd.cmdarg = mmc->rca << 16;
1089
1090 err = mmc_send_cmd(mmc, &cmd, NULL);
1091 if (err)
1092 return err;
1093
1094 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1095 cmd.resp_type = MMC_RSP_R1;
1096 cmd.cmdarg = 0;
1097
1098 retry_ssr:
1099 data.dest = (char *)ssr;
1100 data.blocksize = 64;
1101 data.blocks = 1;
1102 data.flags = MMC_DATA_READ;
1103
1104 err = mmc_send_cmd(mmc, &cmd, &data);
1105 if (err) {
1106 if (timeout--)
1107 goto retry_ssr;
1108
1109 return err;
1110 }
1111
1112 for (i = 0; i < 16; i++)
1113 ssr[i] = be32_to_cpu(ssr[i]);
1114
1115 au = (ssr[2] >> 12) & 0xF;
1116 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1117 mmc->ssr.au = sd_au_size[au];
1118 es = (ssr[3] >> 24) & 0xFF;
1119 es |= (ssr[2] & 0xFF) << 8;
1120 et = (ssr[3] >> 18) & 0x3F;
1121 if (es && et) {
1122 eo = (ssr[3] >> 16) & 0x3;
1123 mmc->ssr.erase_timeout = (et * 1000) / es;
1124 mmc->ssr.erase_offset = eo * 1000;
1125 }
1126 } else {
1127 debug("Invalid Allocation Unit Size.\n");
1128 }
1129
1130 return 0;
1131 }
1132
1133 /* frequency bases */
1134 /* divided by 10 to be nice to platforms without floating point */
1135 static const int fbase[] = {
1136 10000,
1137 100000,
1138 1000000,
1139 10000000,
1140 };
1141
1142 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1143 * to platforms without floating point.
1144 */
1145 static const u8 multipliers[] = {
1146 0, /* reserved */
1147 10,
1148 12,
1149 13,
1150 15,
1151 20,
1152 25,
1153 30,
1154 35,
1155 40,
1156 45,
1157 50,
1158 55,
1159 60,
1160 70,
1161 80,
1162 };
1163
1164 static inline int bus_width(uint cap)
1165 {
1166 if (cap == MMC_MODE_8BIT)
1167 return 8;
1168 if (cap == MMC_MODE_4BIT)
1169 return 4;
1170 if (cap == MMC_MODE_1BIT)
1171 return 1;
1172 printf("invalid bus witdh capability 0x%x\n", cap);
1173 return 0;
1174 }
1175
1176 #if !CONFIG_IS_ENABLED(DM_MMC)
1177 static void mmc_set_ios(struct mmc *mmc)
1178 {
1179 if (mmc->cfg->ops->set_ios)
1180 mmc->cfg->ops->set_ios(mmc);
1181 }
1182 #endif
1183
1184 void mmc_set_clock(struct mmc *mmc, uint clock)
1185 {
1186 if (clock > mmc->cfg->f_max)
1187 clock = mmc->cfg->f_max;
1188
1189 if (clock < mmc->cfg->f_min)
1190 clock = mmc->cfg->f_min;
1191
1192 mmc->clock = clock;
1193
1194 mmc_set_ios(mmc);
1195 }
1196
1197 static void mmc_set_bus_width(struct mmc *mmc, uint width)
1198 {
1199 mmc->bus_width = width;
1200
1201 mmc_set_ios(mmc);
1202 }
1203
1204 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1205 /*
1206 * helper function to display the capabilities in a human
1207 * friendly manner. The capabilities include bus width and
1208 * supported modes.
1209 */
1210 void mmc_dump_capabilities(const char *text, uint caps)
1211 {
1212 enum bus_mode mode;
1213
1214 printf("%s: widths [", text);
1215 if (caps & MMC_MODE_8BIT)
1216 printf("8, ");
1217 if (caps & MMC_MODE_4BIT)
1218 printf("4, ");
1219 if (caps & MMC_MODE_1BIT)
1220 printf("1, ");
1221 printf("\b\b] modes [");
1222 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1223 if (MMC_CAP(mode) & caps)
1224 printf("%s, ", mmc_mode_name(mode));
1225 printf("\b\b]\n");
1226 }
1227 #endif
1228
1229 struct mode_width_tuning {
1230 enum bus_mode mode;
1231 uint widths;
1232 };
1233
1234 static const struct mode_width_tuning sd_modes_by_pref[] = {
1235 {
1236 .mode = SD_HS,
1237 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1238 },
1239 {
1240 .mode = SD_LEGACY,
1241 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1242 }
1243 };
1244
1245 #define for_each_sd_mode_by_pref(caps, mwt) \
1246 for (mwt = sd_modes_by_pref;\
1247 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1248 mwt++) \
1249 if (caps & MMC_CAP(mwt->mode))
1250
1251 static int sd_select_mode_and_width(struct mmc *mmc)
1252 {
1253 int err;
1254 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1255 const struct mode_width_tuning *mwt;
1256
1257 err = sd_get_capabilities(mmc);
1258 if (err)
1259 return err;
1260 /* Restrict card's capabilities by what the host can do */
1261 mmc->card_caps &= (mmc->cfg->host_caps | MMC_MODE_1BIT);
1262
1263 for_each_sd_mode_by_pref(mmc->card_caps, mwt) {
1264 uint *w;
1265
1266 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
1267 if (*w & mmc->card_caps & mwt->widths) {
1268 debug("trying mode %s width %d (at %d MHz)\n",
1269 mmc_mode_name(mwt->mode),
1270 bus_width(*w),
1271 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1272
1273 /* configure the bus width (card + host) */
1274 err = sd_select_bus_width(mmc, bus_width(*w));
1275 if (err)
1276 goto error;
1277 mmc_set_bus_width(mmc, bus_width(*w));
1278
1279 /* configure the bus mode (card) */
1280 err = sd_set_card_speed(mmc, mwt->mode);
1281 if (err)
1282 goto error;
1283
1284 /* configure the bus mode (host) */
1285 mmc_select_mode(mmc, mwt->mode);
1286 mmc_set_clock(mmc, mmc->tran_speed);
1287
1288 err = sd_read_ssr(mmc);
1289 if (!err)
1290 return 0;
1291
1292 printf("bad ssr\n");
1293
1294 error:
1295 /* revert to a safer bus speed */
1296 mmc_select_mode(mmc, SD_LEGACY);
1297 mmc_set_clock(mmc, mmc->tran_speed);
1298 }
1299 }
1300 }
1301
1302 printf("unable to select a mode\n");
1303 return -ENOTSUPP;
1304 }
1305
1306 /*
1307 * read the compare the part of ext csd that is constant.
1308 * This can be used to check that the transfer is working
1309 * as expected.
1310 */
1311 static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
1312 {
1313 int err;
1314 const u8 *ext_csd = mmc->ext_csd;
1315 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1316
1317 err = mmc_send_ext_csd(mmc, test_csd);
1318 if (err)
1319 return err;
1320
1321 /* Only compare read only fields */
1322 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1323 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1324 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1325 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1326 ext_csd[EXT_CSD_REV]
1327 == test_csd[EXT_CSD_REV] &&
1328 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1329 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1330 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1331 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1332 return 0;
1333
1334 return -EBADMSG;
1335 }
1336
1337 static int mmc_select_bus_freq_width(struct mmc *mmc)
1338 {
1339 /* An array of possible bus widths in order of preference */
1340 static const unsigned int ext_csd_bits[] = {
1341 EXT_CSD_DDR_BUS_WIDTH_8,
1342 EXT_CSD_DDR_BUS_WIDTH_4,
1343 EXT_CSD_BUS_WIDTH_8,
1344 EXT_CSD_BUS_WIDTH_4,
1345 EXT_CSD_BUS_WIDTH_1,
1346 };
1347 /* An array to map CSD bus widths to host cap bits */
1348 static const unsigned int ext_to_hostcaps[] = {
1349 [EXT_CSD_DDR_BUS_WIDTH_4] =
1350 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1351 [EXT_CSD_DDR_BUS_WIDTH_8] =
1352 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
1353 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1354 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1355 };
1356 /* An array to map chosen bus width to an integer */
1357 static const unsigned int widths[] = {
1358 8, 4, 8, 4, 1,
1359 };
1360 int err;
1361 int idx;
1362
1363 err = mmc_change_freq(mmc);
1364 if (err)
1365 return err;
1366
1367 /* Restrict card's capabilities by what the host can do */
1368 mmc->card_caps &= (mmc->cfg->host_caps | MMC_MODE_1BIT);
1369
1370 /* Only version 4 of MMC supports wider bus widths */
1371 if (mmc->version < MMC_VERSION_4)
1372 return 0;
1373
1374 if (!mmc->ext_csd) {
1375 debug("No ext_csd found!\n"); /* this should enver happen */
1376 return -ENOTSUPP;
1377 }
1378
1379 for (idx = 0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1380 unsigned int extw = ext_csd_bits[idx];
1381 unsigned int caps = ext_to_hostcaps[extw];
1382 /*
1383 * If the bus width is still not changed,
1384 * don't try to set the default again.
1385 * Otherwise, recover from switch attempts
1386 * by switching to 1-bit bus width.
1387 */
1388 if (extw == EXT_CSD_BUS_WIDTH_1 &&
1389 mmc->bus_width == 1) {
1390 err = 0;
1391 break;
1392 }
1393
1394 /*
1395 * Check to make sure the card and controller support
1396 * these capabilities
1397 */
1398 if ((mmc->card_caps & caps) != caps)
1399 continue;
1400
1401 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1402 EXT_CSD_BUS_WIDTH, extw);
1403
1404 if (err)
1405 continue;
1406
1407 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
1408 mmc_set_bus_width(mmc, widths[idx]);
1409
1410 err = mmc_read_and_compare_ext_csd(mmc);
1411 if (!err)
1412 break;
1413 }
1414
1415 if (err)
1416 return err;
1417
1418 if (mmc->card_caps & MMC_MODE_HS_52MHz) {
1419 if (mmc->ddr_mode)
1420 mmc_select_mode(mmc, MMC_DDR_52);
1421 else
1422 mmc_select_mode(mmc, MMC_HS_52);
1423 } else if (mmc->card_caps & MMC_MODE_HS)
1424 mmc_select_mode(mmc, MMC_HS);
1425
1426 return err;
1427 }
1428
1429 static int mmc_startup_v4(struct mmc *mmc)
1430 {
1431 int err, i;
1432 u64 capacity;
1433 bool has_parts = false;
1434 bool part_completed;
1435 u8 *ext_csd;
1436
1437 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
1438 return 0;
1439
1440 ext_csd = malloc_cache_aligned(MMC_MAX_BLOCK_LEN);
1441 if (!ext_csd)
1442 return -ENOMEM;
1443
1444 mmc->ext_csd = ext_csd;
1445
1446 /* check ext_csd version and capacity */
1447 err = mmc_send_ext_csd(mmc, ext_csd);
1448 if (err)
1449 return err;
1450 if (ext_csd[EXT_CSD_REV] >= 2) {
1451 /*
1452 * According to the JEDEC Standard, the value of
1453 * ext_csd's capacity is valid if the value is more
1454 * than 2GB
1455 */
1456 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1457 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1458 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1459 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1460 capacity *= MMC_MAX_BLOCK_LEN;
1461 if ((capacity >> 20) > 2 * 1024)
1462 mmc->capacity_user = capacity;
1463 }
1464
1465 switch (ext_csd[EXT_CSD_REV]) {
1466 case 1:
1467 mmc->version = MMC_VERSION_4_1;
1468 break;
1469 case 2:
1470 mmc->version = MMC_VERSION_4_2;
1471 break;
1472 case 3:
1473 mmc->version = MMC_VERSION_4_3;
1474 break;
1475 case 5:
1476 mmc->version = MMC_VERSION_4_41;
1477 break;
1478 case 6:
1479 mmc->version = MMC_VERSION_4_5;
1480 break;
1481 case 7:
1482 mmc->version = MMC_VERSION_5_0;
1483 break;
1484 case 8:
1485 mmc->version = MMC_VERSION_5_1;
1486 break;
1487 }
1488
1489 /* The partition data may be non-zero but it is only
1490 * effective if PARTITION_SETTING_COMPLETED is set in
1491 * EXT_CSD, so ignore any data if this bit is not set,
1492 * except for enabling the high-capacity group size
1493 * definition (see below).
1494 */
1495 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1496 EXT_CSD_PARTITION_SETTING_COMPLETED);
1497
1498 /* store the partition info of emmc */
1499 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1500 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1501 ext_csd[EXT_CSD_BOOT_MULT])
1502 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1503 if (part_completed &&
1504 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
1505 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1506
1507 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1508
1509 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1510
1511 for (i = 0; i < 4; i++) {
1512 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1513 uint mult = (ext_csd[idx + 2] << 16) +
1514 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1515 if (mult)
1516 has_parts = true;
1517 if (!part_completed)
1518 continue;
1519 mmc->capacity_gp[i] = mult;
1520 mmc->capacity_gp[i] *=
1521 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1522 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1523 mmc->capacity_gp[i] <<= 19;
1524 }
1525
1526 if (part_completed) {
1527 mmc->enh_user_size =
1528 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
1529 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
1530 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1531 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1532 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1533 mmc->enh_user_size <<= 19;
1534 mmc->enh_user_start =
1535 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
1536 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
1537 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
1538 ext_csd[EXT_CSD_ENH_START_ADDR];
1539 if (mmc->high_capacity)
1540 mmc->enh_user_start <<= 9;
1541 }
1542
1543 /*
1544 * Host needs to enable ERASE_GRP_DEF bit if device is
1545 * partitioned. This bit will be lost every time after a reset
1546 * or power off. This will affect erase size.
1547 */
1548 if (part_completed)
1549 has_parts = true;
1550 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1551 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1552 has_parts = true;
1553 if (has_parts) {
1554 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1555 EXT_CSD_ERASE_GROUP_DEF, 1);
1556
1557 if (err)
1558 return err;
1559
1560 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1561 }
1562
1563 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1564 /* Read out group size from ext_csd */
1565 mmc->erase_grp_size =
1566 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1567 /*
1568 * if high capacity and partition setting completed
1569 * SEC_COUNT is valid even if it is smaller than 2 GiB
1570 * JEDEC Standard JESD84-B45, 6.2.4
1571 */
1572 if (mmc->high_capacity && part_completed) {
1573 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1574 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1575 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1576 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1577 capacity *= MMC_MAX_BLOCK_LEN;
1578 mmc->capacity_user = capacity;
1579 }
1580 } else {
1581 /* Calculate the group size from the csd value. */
1582 int erase_gsz, erase_gmul;
1583
1584 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1585 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1586 mmc->erase_grp_size = (erase_gsz + 1)
1587 * (erase_gmul + 1);
1588 }
1589
1590 mmc->hc_wp_grp_size = 1024
1591 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1592 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1593
1594 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1595
1596 return 0;
1597 }
1598
1599 static int mmc_startup(struct mmc *mmc)
1600 {
1601 int err, i;
1602 uint mult, freq;
1603 u64 cmult, csize;
1604 struct mmc_cmd cmd;
1605 struct blk_desc *bdesc;
1606
1607 #ifdef CONFIG_MMC_SPI_CRC_ON
1608 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1609 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1610 cmd.resp_type = MMC_RSP_R1;
1611 cmd.cmdarg = 1;
1612 err = mmc_send_cmd(mmc, &cmd, NULL);
1613
1614 if (err)
1615 return err;
1616 }
1617 #endif
1618
1619 /* Put the Card in Identify Mode */
1620 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1621 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
1622 cmd.resp_type = MMC_RSP_R2;
1623 cmd.cmdarg = 0;
1624
1625 err = mmc_send_cmd(mmc, &cmd, NULL);
1626
1627 if (err)
1628 return err;
1629
1630 memcpy(mmc->cid, cmd.response, 16);
1631
1632 /*
1633 * For MMC cards, set the Relative Address.
1634 * For SD cards, get the Relatvie Address.
1635 * This also puts the cards into Standby State
1636 */
1637 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1638 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1639 cmd.cmdarg = mmc->rca << 16;
1640 cmd.resp_type = MMC_RSP_R6;
1641
1642 err = mmc_send_cmd(mmc, &cmd, NULL);
1643
1644 if (err)
1645 return err;
1646
1647 if (IS_SD(mmc))
1648 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1649 }
1650
1651 /* Get the Card-Specific Data */
1652 cmd.cmdidx = MMC_CMD_SEND_CSD;
1653 cmd.resp_type = MMC_RSP_R2;
1654 cmd.cmdarg = mmc->rca << 16;
1655
1656 err = mmc_send_cmd(mmc, &cmd, NULL);
1657
1658 if (err)
1659 return err;
1660
1661 mmc->csd[0] = cmd.response[0];
1662 mmc->csd[1] = cmd.response[1];
1663 mmc->csd[2] = cmd.response[2];
1664 mmc->csd[3] = cmd.response[3];
1665
1666 if (mmc->version == MMC_VERSION_UNKNOWN) {
1667 int version = (cmd.response[0] >> 26) & 0xf;
1668
1669 switch (version) {
1670 case 0:
1671 mmc->version = MMC_VERSION_1_2;
1672 break;
1673 case 1:
1674 mmc->version = MMC_VERSION_1_4;
1675 break;
1676 case 2:
1677 mmc->version = MMC_VERSION_2_2;
1678 break;
1679 case 3:
1680 mmc->version = MMC_VERSION_3;
1681 break;
1682 case 4:
1683 mmc->version = MMC_VERSION_4;
1684 break;
1685 default:
1686 mmc->version = MMC_VERSION_1_2;
1687 break;
1688 }
1689 }
1690
1691 /* divide frequency by 10, since the mults are 10x bigger */
1692 freq = fbase[(cmd.response[0] & 0x7)];
1693 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
1694
1695 mmc->legacy_speed = freq * mult;
1696 mmc_select_mode(mmc, MMC_LEGACY);
1697
1698 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
1699 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
1700
1701 if (IS_SD(mmc))
1702 mmc->write_bl_len = mmc->read_bl_len;
1703 else
1704 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
1705
1706 if (mmc->high_capacity) {
1707 csize = (mmc->csd[1] & 0x3f) << 16
1708 | (mmc->csd[2] & 0xffff0000) >> 16;
1709 cmult = 8;
1710 } else {
1711 csize = (mmc->csd[1] & 0x3ff) << 2
1712 | (mmc->csd[2] & 0xc0000000) >> 30;
1713 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1714 }
1715
1716 mmc->capacity_user = (csize + 1) << (cmult + 2);
1717 mmc->capacity_user *= mmc->read_bl_len;
1718 mmc->capacity_boot = 0;
1719 mmc->capacity_rpmb = 0;
1720 for (i = 0; i < 4; i++)
1721 mmc->capacity_gp[i] = 0;
1722
1723 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1724 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1725
1726 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1727 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1728
1729 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1730 cmd.cmdidx = MMC_CMD_SET_DSR;
1731 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1732 cmd.resp_type = MMC_RSP_NONE;
1733 if (mmc_send_cmd(mmc, &cmd, NULL))
1734 printf("MMC: SET_DSR failed\n");
1735 }
1736
1737 /* Select the card, and put it into Transfer Mode */
1738 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1739 cmd.cmdidx = MMC_CMD_SELECT_CARD;
1740 cmd.resp_type = MMC_RSP_R1;
1741 cmd.cmdarg = mmc->rca << 16;
1742 err = mmc_send_cmd(mmc, &cmd, NULL);
1743
1744 if (err)
1745 return err;
1746 }
1747
1748 /*
1749 * For SD, its erase group is always one sector
1750 */
1751 mmc->erase_grp_size = 1;
1752 mmc->part_config = MMCPART_NOAVAILABLE;
1753
1754 err = mmc_startup_v4(mmc);
1755 if (err)
1756 return err;
1757
1758 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
1759 if (err)
1760 return err;
1761
1762 if (IS_SD(mmc))
1763 err = sd_select_mode_and_width(mmc);
1764 else
1765 err = mmc_select_bus_freq_width(mmc);
1766
1767 if (err)
1768 return err;
1769
1770
1771 /* Fix the block length for DDR mode */
1772 if (mmc->ddr_mode) {
1773 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1774 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1775 }
1776
1777 /* fill in device description */
1778 bdesc = mmc_get_blk_desc(mmc);
1779 bdesc->lun = 0;
1780 bdesc->hwpart = 0;
1781 bdesc->type = 0;
1782 bdesc->blksz = mmc->read_bl_len;
1783 bdesc->log2blksz = LOG2(bdesc->blksz);
1784 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
1785 #if !defined(CONFIG_SPL_BUILD) || \
1786 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
1787 !defined(CONFIG_USE_TINY_PRINTF))
1788 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
1789 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1790 (mmc->cid[3] >> 16) & 0xffff);
1791 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1792 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1793 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1794 (mmc->cid[2] >> 24) & 0xff);
1795 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1796 (mmc->cid[2] >> 16) & 0xf);
1797 #else
1798 bdesc->vendor[0] = 0;
1799 bdesc->product[0] = 0;
1800 bdesc->revision[0] = 0;
1801 #endif
1802 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
1803 part_init(bdesc);
1804 #endif
1805
1806 return 0;
1807 }
1808
1809 static int mmc_send_if_cond(struct mmc *mmc)
1810 {
1811 struct mmc_cmd cmd;
1812 int err;
1813
1814 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1815 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
1816 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
1817 cmd.resp_type = MMC_RSP_R7;
1818
1819 err = mmc_send_cmd(mmc, &cmd, NULL);
1820
1821 if (err)
1822 return err;
1823
1824 if ((cmd.response[0] & 0xff) != 0xaa)
1825 return -EOPNOTSUPP;
1826 else
1827 mmc->version = SD_VERSION_2;
1828
1829 return 0;
1830 }
1831
1832 #if !CONFIG_IS_ENABLED(DM_MMC)
1833 /* board-specific MMC power initializations. */
1834 __weak void board_mmc_power_init(void)
1835 {
1836 }
1837 #endif
1838
1839 static int mmc_power_init(struct mmc *mmc)
1840 {
1841 #if CONFIG_IS_ENABLED(DM_MMC)
1842 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1843 int ret;
1844
1845 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
1846 &mmc->vmmc_supply);
1847 if (ret)
1848 debug("%s: No vmmc supply\n", mmc->dev->name);
1849
1850 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
1851 &mmc->vqmmc_supply);
1852 if (ret)
1853 debug("%s: No vqmmc supply\n", mmc->dev->name);
1854
1855 if (mmc->vmmc_supply) {
1856 ret = regulator_set_enable(mmc->vmmc_supply, true);
1857 if (ret) {
1858 puts("Error enabling VMMC supply\n");
1859 return ret;
1860 }
1861 }
1862 #endif
1863 #else /* !CONFIG_DM_MMC */
1864 /*
1865 * Driver model should use a regulator, as above, rather than calling
1866 * out to board code.
1867 */
1868 board_mmc_power_init();
1869 #endif
1870 return 0;
1871 }
1872
1873 int mmc_start_init(struct mmc *mmc)
1874 {
1875 bool no_card;
1876 int err;
1877
1878 /* we pretend there's no card when init is NULL */
1879 no_card = mmc_getcd(mmc) == 0;
1880 #if !CONFIG_IS_ENABLED(DM_MMC)
1881 no_card = no_card || (mmc->cfg->ops->init == NULL);
1882 #endif
1883 if (no_card) {
1884 mmc->has_init = 0;
1885 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1886 printf("MMC: no card present\n");
1887 #endif
1888 return -ENOMEDIUM;
1889 }
1890
1891 if (mmc->has_init)
1892 return 0;
1893
1894 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1895 mmc_adapter_card_type_ident();
1896 #endif
1897 err = mmc_power_init(mmc);
1898 if (err)
1899 return err;
1900
1901 #if CONFIG_IS_ENABLED(DM_MMC)
1902 /* The device has already been probed ready for use */
1903 #else
1904 /* made sure it's not NULL earlier */
1905 err = mmc->cfg->ops->init(mmc);
1906 if (err)
1907 return err;
1908 #endif
1909 mmc->ddr_mode = 0;
1910 mmc_set_bus_width(mmc, 1);
1911 mmc_set_clock(mmc, 1);
1912
1913 /* Reset the Card */
1914 err = mmc_go_idle(mmc);
1915
1916 if (err)
1917 return err;
1918
1919 /* The internal partition reset to user partition(0) at every CMD0*/
1920 mmc_get_blk_desc(mmc)->hwpart = 0;
1921
1922 /* Test for SD version 2 */
1923 err = mmc_send_if_cond(mmc);
1924
1925 /* Now try to get the SD card's operating condition */
1926 err = sd_send_op_cond(mmc);
1927
1928 /* If the command timed out, we check for an MMC card */
1929 if (err == -ETIMEDOUT) {
1930 err = mmc_send_op_cond(mmc);
1931
1932 if (err) {
1933 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1934 printf("Card did not respond to voltage select!\n");
1935 #endif
1936 return -EOPNOTSUPP;
1937 }
1938 }
1939
1940 if (!err)
1941 mmc->init_in_progress = 1;
1942
1943 return err;
1944 }
1945
1946 static int mmc_complete_init(struct mmc *mmc)
1947 {
1948 int err = 0;
1949
1950 mmc->init_in_progress = 0;
1951 if (mmc->op_cond_pending)
1952 err = mmc_complete_op_cond(mmc);
1953
1954 if (!err)
1955 err = mmc_startup(mmc);
1956 if (err)
1957 mmc->has_init = 0;
1958 else
1959 mmc->has_init = 1;
1960 return err;
1961 }
1962
1963 int mmc_init(struct mmc *mmc)
1964 {
1965 int err = 0;
1966 __maybe_unused unsigned start;
1967 #if CONFIG_IS_ENABLED(DM_MMC)
1968 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
1969
1970 upriv->mmc = mmc;
1971 #endif
1972 if (mmc->has_init)
1973 return 0;
1974
1975 start = get_timer(0);
1976
1977 if (!mmc->init_in_progress)
1978 err = mmc_start_init(mmc);
1979
1980 if (!err)
1981 err = mmc_complete_init(mmc);
1982 if (err)
1983 printf("%s: %d, time %lu\n", __func__, err, get_timer(start));
1984
1985 return err;
1986 }
1987
1988 int mmc_set_dsr(struct mmc *mmc, u16 val)
1989 {
1990 mmc->dsr = val;
1991 return 0;
1992 }
1993
1994 /* CPU-specific MMC initializations */
1995 __weak int cpu_mmc_init(bd_t *bis)
1996 {
1997 return -1;
1998 }
1999
2000 /* board-specific MMC initializations. */
2001 __weak int board_mmc_init(bd_t *bis)
2002 {
2003 return -1;
2004 }
2005
2006 void mmc_set_preinit(struct mmc *mmc, int preinit)
2007 {
2008 mmc->preinit = preinit;
2009 }
2010
2011 #if CONFIG_IS_ENABLED(DM_MMC) && defined(CONFIG_SPL_BUILD)
2012 static int mmc_probe(bd_t *bis)
2013 {
2014 return 0;
2015 }
2016 #elif CONFIG_IS_ENABLED(DM_MMC)
2017 static int mmc_probe(bd_t *bis)
2018 {
2019 int ret, i;
2020 struct uclass *uc;
2021 struct udevice *dev;
2022
2023 ret = uclass_get(UCLASS_MMC, &uc);
2024 if (ret)
2025 return ret;
2026
2027 /*
2028 * Try to add them in sequence order. Really with driver model we
2029 * should allow holes, but the current MMC list does not allow that.
2030 * So if we request 0, 1, 3 we will get 0, 1, 2.
2031 */
2032 for (i = 0; ; i++) {
2033 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2034 if (ret == -ENODEV)
2035 break;
2036 }
2037 uclass_foreach_dev(dev, uc) {
2038 ret = device_probe(dev);
2039 if (ret)
2040 printf("%s - probe failed: %d\n", dev->name, ret);
2041 }
2042
2043 return 0;
2044 }
2045 #else
2046 static int mmc_probe(bd_t *bis)
2047 {
2048 if (board_mmc_init(bis) < 0)
2049 cpu_mmc_init(bis);
2050
2051 return 0;
2052 }
2053 #endif
2054
2055 int mmc_initialize(bd_t *bis)
2056 {
2057 static int initialized = 0;
2058 int ret;
2059 if (initialized) /* Avoid initializing mmc multiple times */
2060 return 0;
2061 initialized = 1;
2062
2063 #if !CONFIG_IS_ENABLED(BLK)
2064 #if !CONFIG_IS_ENABLED(MMC_TINY)
2065 mmc_list_init();
2066 #endif
2067 #endif
2068 ret = mmc_probe(bis);
2069 if (ret)
2070 return ret;
2071
2072 #ifndef CONFIG_SPL_BUILD
2073 print_mmc_devices(',');
2074 #endif
2075
2076 mmc_do_preinit();
2077 return 0;
2078 }
2079
2080 #ifdef CONFIG_CMD_BKOPS_ENABLE
2081 int mmc_set_bkops_enable(struct mmc *mmc)
2082 {
2083 int err;
2084 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2085
2086 err = mmc_send_ext_csd(mmc, ext_csd);
2087 if (err) {
2088 puts("Could not get ext_csd register values\n");
2089 return err;
2090 }
2091
2092 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
2093 puts("Background operations not supported on device\n");
2094 return -EMEDIUMTYPE;
2095 }
2096
2097 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
2098 puts("Background operations already enabled\n");
2099 return 0;
2100 }
2101
2102 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
2103 if (err) {
2104 puts("Failed to enable manual background operations\n");
2105 return err;
2106 }
2107
2108 puts("Enabled manual background operations\n");
2109
2110 return 0;
2111 }
2112 #endif
"Das U-Boot" Source Tree