drivers/mmc/mxsmmc.c

   1 /*
   2  * Freescale i.MX28 SSP MMC driver
   3  *
   4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   5  * on behalf of DENX Software Engineering GmbH
   6  *
   7  * Based on code from LTIB:
   8  * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
   9  * Terry Lv
  10  *
  11  * Copyright 2007, Freescale Semiconductor, Inc
  12  * Andy Fleming
  13  *
  14  * Based vaguely on the pxa mmc code:
  15  * (C) Copyright 2003
  16  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  17  *
  18  * See file CREDITS for list of people who contributed to this
  19  * project.
  20  *
  21  * This program is free software; you can redistribute it and/or
  22  * modify it under the terms of the GNU General Public License as
  23  * published by the Free Software Foundation; either version 2 of
  24  * the License, or (at your option) any later version.
  25  *
  26  * This program is distributed in the hope that it will be useful,
  27  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  28  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  29  * GNU General Public License for more details.
  30  *
  31  * You should have received a copy of the GNU General Public License
  32  * along with this program; if not, write to the Free Software
  33  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  34  * MA 02111-1307 USA
  35  */
  36 #include <common.h>
  37 #include <malloc.h>
  38 #include <mmc.h>
  39 #include <asm/errno.h>
  40 #include <asm/io.h>
  41 #include <asm/arch/clock.h>
  42 #include <asm/arch/imx-regs.h>
  43 #include <asm/arch/sys_proto.h>
  44 #include <asm/arch/dma.h>
  45 #include <bouncebuf.h>
  46
  47 struct mxsmmc_priv {
  48         int                     id;
  49         struct mxs_ssp_regs     *regs;
  50         uint32_t                buswidth;
  51         int                     (*mmc_is_wp)(int);
  52         int                     (*mmc_cd)(int);
  53         struct mxs_dma_desc     *desc;
  54 };
  55
  56 #define MXSMMC_MAX_TIMEOUT      10000
  57 #define MXSMMC_SMALL_TRANSFER   512
  58
  59 static int mxsmmc_cd(struct mxsmmc_priv *priv)
  60 {
  61         struct mxs_ssp_regs *ssp_regs = priv->regs;
  62
  63         if (priv->mmc_cd)
  64                 return priv->mmc_cd(priv->id);
  65
  66         return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
  67 }
  68
  69 static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
  70 {
  71         struct mxs_ssp_regs *ssp_regs = priv->regs;
  72         uint32_t *data_ptr;
  73         int timeout = MXSMMC_MAX_TIMEOUT;
  74         uint32_t reg;
  75         uint32_t data_count = data->blocksize * data->blocks;
  76
  77         if (data->flags & MMC_DATA_READ) {
  78                 data_ptr = (uint32_t *)data->dest;
  79                 while (data_count && --timeout) {
  80                         reg = readl(&ssp_regs->hw_ssp_status);
  81                         if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
  82                                 *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
  83                                 data_count -= 4;
  84                                 timeout = MXSMMC_MAX_TIMEOUT;
  85                         } else
  86                                 udelay(1000);
  87                 }
  88         } else {
  89                 data_ptr = (uint32_t *)data->src;
  90                 timeout *= 100;
  91                 while (data_count && --timeout) {
  92                         reg = readl(&ssp_regs->hw_ssp_status);
  93                         if (!(reg & SSP_STATUS_FIFO_FULL)) {
  94                                 writel(*data_ptr++, &ssp_regs->hw_ssp_data);
  95                                 data_count -= 4;
  96                                 timeout = MXSMMC_MAX_TIMEOUT;
  97                         } else
  98                                 udelay(1000);
  99                 }
 100         }
 101
 102         return timeout ? 0 : COMM_ERR;
 103 }
 104
 105 static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
 106 {
 107         uint32_t data_count = data->blocksize * data->blocks;
 108         int dmach;
 109         struct mxs_dma_desc *desc = priv->desc;
 110         void *addr;
 111         unsigned int flags;
 112         struct bounce_buffer bbstate;
 113
 114         memset(desc, 0, sizeof(struct mxs_dma_desc));
 115         desc->address = (dma_addr_t)desc;
 116
 117         if (data->flags & MMC_DATA_READ) {
 118                 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
 119                 addr = data->dest;
 120                 flags = GEN_BB_WRITE;
 121         } else {
 122                 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
 123                 addr = (void *)data->src;
 124                 flags = GEN_BB_READ;
 125         }
 126
 127         bounce_buffer_start(&bbstate, addr, data_count, flags);
 128
 129         priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer;
 130
 131         priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
 132                                 (data_count << MXS_DMA_DESC_BYTES_OFFSET);
 133
 134         dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
 135         mxs_dma_desc_append(dmach, priv->desc);
 136         if (mxs_dma_go(dmach)) {
 137                 bounce_buffer_stop(&bbstate);
 138                 return COMM_ERR;
 139         }
 140
 141         bounce_buffer_stop(&bbstate);
 142
 143         return 0;
 144 }
 145
 146 /*
 147  * Sends a command out on the bus.  Takes the mmc pointer,
 148  * a command pointer, and an optional data pointer.
 149  */
 150 static int
 151 mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 152 {
 153         struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
 154         struct mxs_ssp_regs *ssp_regs = priv->regs;
 155         uint32_t reg;
 156         int timeout;
 157         uint32_t ctrl0;
 158         int ret;
 159
 160         debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
 161
 162         /* Check bus busy */
 163         timeout = MXSMMC_MAX_TIMEOUT;
 164         while (--timeout) {
 165                 udelay(1000);
 166                 reg = readl(&ssp_regs->hw_ssp_status);
 167                 if (!(reg &
 168                         (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
 169                         SSP_STATUS_CMD_BUSY))) {
 170                         break;
 171                 }
 172         }
 173
 174         if (!timeout) {
 175                 printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev);
 176                 return TIMEOUT;
 177         }
 178
 179         /* See if card is present */
 180         if (!mxsmmc_cd(priv)) {
 181                 printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
 182                 return NO_CARD_ERR;
 183         }
 184
 185         /* Start building CTRL0 contents */
 186         ctrl0 = priv->buswidth;
 187
 188         /* Set up command */
 189         if (!(cmd->resp_type & MMC_RSP_CRC))
 190                 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
 191         if (cmd->resp_type & MMC_RSP_PRESENT)   /* Need to get response */
 192                 ctrl0 |= SSP_CTRL0_GET_RESP;
 193         if (cmd->resp_type & MMC_RSP_136)       /* It's a 136 bits response */
 194                 ctrl0 |= SSP_CTRL0_LONG_RESP;
 195
 196         if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
 197                 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
 198         else
 199                 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
 200
 201         /* Command index */
 202         reg = readl(&ssp_regs->hw_ssp_cmd0);
 203         reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
 204         reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
 205         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 206                 reg |= SSP_CMD0_APPEND_8CYC;
 207         writel(reg, &ssp_regs->hw_ssp_cmd0);
 208
 209         /* Command argument */
 210         writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
 211
 212         /* Set up data */
 213         if (data) {
 214                 /* READ or WRITE */
 215                 if (data->flags & MMC_DATA_READ) {
 216                         ctrl0 |= SSP_CTRL0_READ;
 217                 } else if (priv->mmc_is_wp &&
 218                         priv->mmc_is_wp(mmc->block_dev.dev)) {
 219                         printf("MMC%d: Can not write a locked card!\n",
 220                                 mmc->block_dev.dev);
 221                         return UNUSABLE_ERR;
 222                 }
 223
 224                 ctrl0 |= SSP_CTRL0_DATA_XFER;
 225
 226                 reg = data->blocksize * data->blocks;
 227 #if defined(CONFIG_MX23)
 228                 ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;
 229
 230                 clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,
 231                         SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK,
 232                         ((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |
 233                         ((ffs(data->blocksize) - 1) <<
 234                                 SSP_CMD0_BLOCK_SIZE_OFFSET));
 235 #elif defined(CONFIG_MX28)
 236                 writel(reg, &ssp_regs->hw_ssp_xfer_size);
 237
 238                 reg = ((data->blocks - 1) <<
 239                         SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
 240                         ((ffs(data->blocksize) - 1) <<
 241                         SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
 242                 writel(reg, &ssp_regs->hw_ssp_block_size);
 243 #endif
 244         }
 245
 246         /* Kick off the command */
 247         ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
 248         writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
 249
 250         /* Wait for the command to complete */
 251         timeout = MXSMMC_MAX_TIMEOUT;
 252         while (--timeout) {
 253                 udelay(1000);
 254                 reg = readl(&ssp_regs->hw_ssp_status);
 255                 if (!(reg & SSP_STATUS_CMD_BUSY))
 256                         break;
 257         }
 258
 259         if (!timeout) {
 260                 printf("MMC%d: Command %d busy\n",
 261                         mmc->block_dev.dev, cmd->cmdidx);
 262                 return TIMEOUT;
 263         }
 264
 265         /* Check command timeout */
 266         if (reg & SSP_STATUS_RESP_TIMEOUT) {
 267                 printf("MMC%d: Command %d timeout (status 0x%08x)\n",
 268                         mmc->block_dev.dev, cmd->cmdidx, reg);
 269                 return TIMEOUT;
 270         }
 271
 272         /* Check command errors */
 273         if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
 274                 printf("MMC%d: Command %d error (status 0x%08x)!\n",
 275                         mmc->block_dev.dev, cmd->cmdidx, reg);
 276                 return COMM_ERR;
 277         }
 278
 279         /* Copy response to response buffer */
 280         if (cmd->resp_type & MMC_RSP_136) {
 281                 cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
 282                 cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
 283                 cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
 284                 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
 285         } else
 286                 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
 287
 288         /* Return if no data to process */
 289         if (!data)
 290                 return 0;
 291
 292         if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
 293                 ret = mxsmmc_send_cmd_pio(priv, data);
 294                 if (ret) {
 295                         printf("MMC%d: Data timeout with command %d "
 296                                 "(status 0x%08x)!\n",
 297                                 mmc->block_dev.dev, cmd->cmdidx, reg);
 298                         return ret;
 299                 }
 300         } else {
 301                 ret = mxsmmc_send_cmd_dma(priv, data);
 302                 if (ret) {
 303                         printf("MMC%d: DMA transfer failed\n",
 304                                 mmc->block_dev.dev);
 305                         return ret;
 306                 }
 307         }
 308
 309         /* Check data errors */
 310         reg = readl(&ssp_regs->hw_ssp_status);
 311         if (reg &
 312                 (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
 313                 SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
 314                 printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
 315                         mmc->block_dev.dev, cmd->cmdidx, reg);
 316                 return COMM_ERR;
 317         }
 318
 319         return 0;
 320 }
 321
 322 static void mxsmmc_set_ios(struct mmc *mmc)
 323 {
 324         struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
 325         struct mxs_ssp_regs *ssp_regs = priv->regs;
 326
 327         /* Set the clock speed */
 328         if (mmc->clock)
 329                 mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);
 330
 331         switch (mmc->bus_width) {
 332         case 1:
 333                 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
 334                 break;
 335         case 4:
 336                 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
 337                 break;
 338         case 8:
 339                 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
 340                 break;
 341         }
 342
 343         /* Set the bus width */
 344         clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
 345                         SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
 346
 347         debug("MMC%d: Set %d bits bus width\n",
 348                 mmc->block_dev.dev, mmc->bus_width);
 349 }
 350
 351 static int mxsmmc_init(struct mmc *mmc)
 352 {
 353         struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
 354         struct mxs_ssp_regs *ssp_regs = priv->regs;
 355
 356         /* Reset SSP */
 357         mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
 358
 359         /* Reconfigure the SSP block for MMC operation */
 360         writel(SSP_CTRL1_SSP_MODE_SD_MMC |
 361                 SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
 362                 SSP_CTRL1_DMA_ENABLE |
 363                 SSP_CTRL1_POLARITY |
 364                 SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
 365                 SSP_CTRL1_DATA_CRC_IRQ_EN |
 366                 SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
 367                 SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
 368                 SSP_CTRL1_RESP_ERR_IRQ_EN,
 369                 &ssp_regs->hw_ssp_ctrl1_set);
 370
 371         /* Set initial bit clock 400 KHz */
 372         mxs_set_ssp_busclock(priv->id, 400);
 373
 374         /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
 375         writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
 376         udelay(200);
 377         writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
 378
 379         return 0;
 380 }
 381
 382 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
 383 {
 384         struct mmc *mmc = NULL;
 385         struct mxsmmc_priv *priv = NULL;
 386         int ret;
 387         const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id);
 388
 389         if (!mxs_ssp_bus_id_valid(id))
 390                 return -ENODEV;
 391
 392         mmc = malloc(sizeof(struct mmc));
 393         if (!mmc)
 394                 return -ENOMEM;
 395
 396         priv = malloc(sizeof(struct mxsmmc_priv));
 397         if (!priv) {
 398                 free(mmc);
 399                 return -ENOMEM;
 400         }
 401
 402         priv->desc = mxs_dma_desc_alloc();
 403         if (!priv->desc) {
 404                 free(priv);
 405                 free(mmc);
 406                 return -ENOMEM;
 407         }
 408
 409         ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id);
 410         if (ret)
 411                 return ret;
 412
 413         priv->mmc_is_wp = wp;
 414         priv->mmc_cd = cd;
 415         priv->id = id;
 416         priv->regs = mxs_ssp_regs_by_bus(id);
 417
 418         sprintf(mmc->name, "MXS MMC");
 419         mmc->send_cmd = mxsmmc_send_cmd;
 420         mmc->set_ios = mxsmmc_set_ios;
 421         mmc->init = mxsmmc_init;
 422         mmc->getcd = NULL;
 423         mmc->getwp = NULL;
 424         mmc->priv = priv;
 425
 426         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 427
 428         mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
 429                          MMC_MODE_HS_52MHz | MMC_MODE_HS;
 430
 431         /*
 432          * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
 433          * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
 434          * CLOCK_DIVIDE has to be an even value from 2 to 254, and
 435          * CLOCK_RATE could be any integer from 0 to 255.
 436          */
 437         mmc->f_min = 400000;
 438         mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2;
 439         mmc->b_max = 0x20;
 440
 441         mmc_register(mmc);
 442         return 0;
 443 }