3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 #include <asm/arch/mmc_host_def.h>
36 #include <asm/arch/sys_proto.h>
38 /* simplify defines to OMAP_HSMMC_USE_GPIO */
39 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
40 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
41 #define OMAP_HSMMC_USE_GPIO
43 #undef OMAP_HSMMC_USE_GPIO
46 /* common definitions for all OMAPs */
47 #define SYSCTL_SRC (1 << 25)
48 #define SYSCTL_SRD (1 << 26)
50 struct omap_hsmmc_data
{
51 struct hsmmc
*base_addr
;
52 #ifdef OMAP_HSMMC_USE_GPIO
58 /* If we fail after 1 second wait, something is really bad */
59 #define MAX_RETRY_MS 1000
61 static int mmc_read_data(struct hsmmc
*mmc_base
, char *buf
, unsigned int size
);
62 static int mmc_write_data(struct hsmmc
*mmc_base
, const char *buf
,
64 static struct mmc hsmmc_dev
[3];
65 static struct omap_hsmmc_data hsmmc_dev_data
[3];
67 #ifdef OMAP_HSMMC_USE_GPIO
68 static int omap_mmc_setup_gpio_in(int gpio
, const char *label
)
70 if (!gpio_is_valid(gpio
))
73 if (gpio_request(gpio
, label
) < 0)
76 if (gpio_direction_input(gpio
) < 0)
83 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
84 static void omap4_vmmc_pbias_config(struct mmc
*mmc
)
88 value
= readl((*ctrl
)->control_pbiaslite
);
89 value
&= ~(MMC1_PBIASLITE_PWRDNZ
| MMC1_PWRDNZ
);
90 writel(value
, (*ctrl
)->control_pbiaslite
);
92 twl6030_power_mmc_init();
93 value
= readl((*ctrl
)->control_pbiaslite
);
94 value
|= MMC1_PBIASLITE_VMODE
| MMC1_PBIASLITE_PWRDNZ
| MMC1_PWRDNZ
;
95 writel(value
, (*ctrl
)->control_pbiaslite
);
99 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
100 static void omap5_pbias_config(struct mmc
*mmc
)
104 value
= readl((*ctrl
)->control_pbias
);
105 value
&= ~SDCARD_PWRDNZ
;
106 writel(value
, (*ctrl
)->control_pbias
);
107 udelay(10); /* wait 10 us */
108 value
&= ~SDCARD_BIAS_PWRDNZ
;
109 writel(value
, (*ctrl
)->control_pbias
);
111 palmas_mmc1_poweron_ldo();
113 value
= readl((*ctrl
)->control_pbias
);
114 value
|= SDCARD_BIAS_PWRDNZ
;
115 writel(value
, (*ctrl
)->control_pbias
);
116 udelay(150); /* wait 150 us */
117 value
|= SDCARD_PWRDNZ
;
118 writel(value
, (*ctrl
)->control_pbias
);
119 udelay(150); /* wait 150 us */
123 unsigned char mmc_board_init(struct mmc
*mmc
)
125 #if defined(CONFIG_OMAP34XX)
126 t2_t
*t2_base
= (t2_t
*)T2_BASE
;
127 struct prcm
*prcm_base
= (struct prcm
*)PRCM_BASE
;
130 pbias_lite
= readl(&t2_base
->pbias_lite
);
131 pbias_lite
&= ~(PBIASLITEPWRDNZ1
| PBIASLITEPWRDNZ0
);
132 writel(pbias_lite
, &t2_base
->pbias_lite
);
134 #if defined(CONFIG_TWL4030_POWER)
135 twl4030_power_mmc_init();
136 mdelay(100); /* ramp-up delay from Linux code */
138 #if defined(CONFIG_OMAP34XX)
139 writel(pbias_lite
| PBIASLITEPWRDNZ1
|
140 PBIASSPEEDCTRL0
| PBIASLITEPWRDNZ0
,
141 &t2_base
->pbias_lite
);
143 writel(readl(&t2_base
->devconf0
) | MMCSDIO1ADPCLKISEL
,
146 writel(readl(&t2_base
->devconf1
) | MMCSDIO2ADPCLKISEL
,
149 /* Change from default of 52MHz to 26MHz if necessary */
150 if (!(mmc
->host_caps
& MMC_MODE_HS_52MHz
))
151 writel(readl(&t2_base
->ctl_prog_io1
) & ~CTLPROGIO1SPEEDCTRL
,
152 &t2_base
->ctl_prog_io1
);
154 writel(readl(&prcm_base
->fclken1_core
) |
155 EN_MMC1
| EN_MMC2
| EN_MMC3
,
156 &prcm_base
->fclken1_core
);
158 writel(readl(&prcm_base
->iclken1_core
) |
159 EN_MMC1
| EN_MMC2
| EN_MMC3
,
160 &prcm_base
->iclken1_core
);
163 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
164 /* PBIAS config needed for MMC1 only */
165 if (mmc
->block_dev
.dev
== 0)
166 omap4_vmmc_pbias_config(mmc
);
168 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
169 if (mmc
->block_dev
.dev
== 0)
170 omap5_pbias_config(mmc
);
176 void mmc_init_stream(struct hsmmc
*mmc_base
)
180 writel(readl(&mmc_base
->con
) | INIT_INITSTREAM
, &mmc_base
->con
);
182 writel(MMC_CMD0
, &mmc_base
->cmd
);
183 start
= get_timer(0);
184 while (!(readl(&mmc_base
->stat
) & CC_MASK
)) {
185 if (get_timer(0) - start
> MAX_RETRY_MS
) {
186 printf("%s: timedout waiting for cc!\n", __func__
);
190 writel(CC_MASK
, &mmc_base
->stat
)
192 writel(MMC_CMD0
, &mmc_base
->cmd
)
194 start
= get_timer(0);
195 while (!(readl(&mmc_base
->stat
) & CC_MASK
)) {
196 if (get_timer(0) - start
> MAX_RETRY_MS
) {
197 printf("%s: timedout waiting for cc2!\n", __func__
);
201 writel(readl(&mmc_base
->con
) & ~INIT_INITSTREAM
, &mmc_base
->con
);
205 static int omap_hsmmc_init_setup(struct mmc
*mmc
)
207 struct hsmmc
*mmc_base
;
208 unsigned int reg_val
;
212 mmc_base
= ((struct omap_hsmmc_data
*)mmc
->priv
)->base_addr
;
215 writel(readl(&mmc_base
->sysconfig
) | MMC_SOFTRESET
,
216 &mmc_base
->sysconfig
);
217 start
= get_timer(0);
218 while ((readl(&mmc_base
->sysstatus
) & RESETDONE
) == 0) {
219 if (get_timer(0) - start
> MAX_RETRY_MS
) {
220 printf("%s: timedout waiting for cc2!\n", __func__
);
224 writel(readl(&mmc_base
->sysctl
) | SOFTRESETALL
, &mmc_base
->sysctl
);
225 start
= get_timer(0);
226 while ((readl(&mmc_base
->sysctl
) & SOFTRESETALL
) != 0x0) {
227 if (get_timer(0) - start
> MAX_RETRY_MS
) {
228 printf("%s: timedout waiting for softresetall!\n",
233 writel(DTW_1_BITMODE
| SDBP_PWROFF
| SDVS_3V0
, &mmc_base
->hctl
);
234 writel(readl(&mmc_base
->capa
) | VS30_3V0SUP
| VS18_1V8SUP
,
237 reg_val
= readl(&mmc_base
->con
) & RESERVED_MASK
;
239 writel(CTPL_MMC_SD
| reg_val
| WPP_ACTIVEHIGH
| CDP_ACTIVEHIGH
|
240 MIT_CTO
| DW8_1_4BITMODE
| MODE_FUNC
| STR_BLOCK
|
241 HR_NOHOSTRESP
| INIT_NOINIT
| NOOPENDRAIN
, &mmc_base
->con
);
244 mmc_reg_out(&mmc_base
->sysctl
, (ICE_MASK
| DTO_MASK
| CEN_MASK
),
245 (ICE_STOP
| DTO_15THDTO
| CEN_DISABLE
));
246 mmc_reg_out(&mmc_base
->sysctl
, ICE_MASK
| CLKD_MASK
,
247 (dsor
<< CLKD_OFFSET
) | ICE_OSCILLATE
);
248 start
= get_timer(0);
249 while ((readl(&mmc_base
->sysctl
) & ICS_MASK
) == ICS_NOTREADY
) {
250 if (get_timer(0) - start
> MAX_RETRY_MS
) {
251 printf("%s: timedout waiting for ics!\n", __func__
);
255 writel(readl(&mmc_base
->sysctl
) | CEN_ENABLE
, &mmc_base
->sysctl
);
257 writel(readl(&mmc_base
->hctl
) | SDBP_PWRON
, &mmc_base
->hctl
);
259 writel(IE_BADA
| IE_CERR
| IE_DEB
| IE_DCRC
| IE_DTO
| IE_CIE
|
260 IE_CEB
| IE_CCRC
| IE_CTO
| IE_BRR
| IE_BWR
| IE_TC
| IE_CC
,
263 mmc_init_stream(mmc_base
);
269 * MMC controller internal finite state machine reset
271 * Used to reset command or data internal state machines, using respectively
272 * SRC or SRD bit of SYSCTL register
274 static void mmc_reset_controller_fsm(struct hsmmc
*mmc_base
, u32 bit
)
278 mmc_reg_out(&mmc_base
->sysctl
, bit
, bit
);
281 * CMD(DAT) lines reset procedures are slightly different
282 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
283 * According to OMAP3 TRM:
284 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
286 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
287 * procedure steps must be as follows:
288 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
289 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
290 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
291 * 3. Wait until the SRC (SRD) bit returns to 0x0
292 * (reset procedure is completed).
294 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
295 defined(CONFIG_AM33XX)
296 if (!(readl(&mmc_base
->sysctl
) & bit
)) {
297 start
= get_timer(0);
298 while (!(readl(&mmc_base
->sysctl
) & bit
)) {
299 if (get_timer(0) - start
> MAX_RETRY_MS
)
304 start
= get_timer(0);
305 while ((readl(&mmc_base
->sysctl
) & bit
) != 0) {
306 if (get_timer(0) - start
> MAX_RETRY_MS
) {
307 printf("%s: timedout waiting for sysctl %x to clear\n",
314 static int omap_hsmmc_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*cmd
,
315 struct mmc_data
*data
)
317 struct hsmmc
*mmc_base
;
318 unsigned int flags
, mmc_stat
;
321 mmc_base
= ((struct omap_hsmmc_data
*)mmc
->priv
)->base_addr
;
322 start
= get_timer(0);
323 while ((readl(&mmc_base
->pstate
) & (DATI_MASK
| CMDI_MASK
)) != 0) {
324 if (get_timer(0) - start
> MAX_RETRY_MS
) {
325 printf("%s: timedout waiting on cmd inhibit to clear\n",
330 writel(0xFFFFFFFF, &mmc_base
->stat
);
331 start
= get_timer(0);
332 while (readl(&mmc_base
->stat
)) {
333 if (get_timer(0) - start
> MAX_RETRY_MS
) {
334 printf("%s: timedout waiting for STAT (%x) to clear\n",
335 __func__
, readl(&mmc_base
->stat
));
341 * CMDIDX[13:8] : Command index
342 * DATAPRNT[5] : Data Present Select
343 * ENCMDIDX[4] : Command Index Check Enable
344 * ENCMDCRC[3] : Command CRC Check Enable
349 * 11 = Length 48 Check busy after response
351 /* Delay added before checking the status of frq change
352 * retry not supported by mmc.c(core file)
354 if (cmd
->cmdidx
== SD_CMD_APP_SEND_SCR
)
355 udelay(50000); /* wait 50 ms */
357 if (!(cmd
->resp_type
& MMC_RSP_PRESENT
))
359 else if (cmd
->resp_type
& MMC_RSP_136
)
360 flags
= RSP_TYPE_LGHT136
| CICE_NOCHECK
;
361 else if (cmd
->resp_type
& MMC_RSP_BUSY
)
362 flags
= RSP_TYPE_LGHT48B
;
364 flags
= RSP_TYPE_LGHT48
;
366 /* enable default flags */
367 flags
= flags
| (CMD_TYPE_NORMAL
| CICE_NOCHECK
| CCCE_NOCHECK
|
368 MSBS_SGLEBLK
| ACEN_DISABLE
| BCE_DISABLE
| DE_DISABLE
);
370 if (cmd
->resp_type
& MMC_RSP_CRC
)
372 if (cmd
->resp_type
& MMC_RSP_OPCODE
)
376 if ((cmd
->cmdidx
== MMC_CMD_READ_MULTIPLE_BLOCK
) ||
377 (cmd
->cmdidx
== MMC_CMD_WRITE_MULTIPLE_BLOCK
)) {
378 flags
|= (MSBS_MULTIBLK
| BCE_ENABLE
);
379 data
->blocksize
= 512;
380 writel(data
->blocksize
| (data
->blocks
<< 16),
383 writel(data
->blocksize
| NBLK_STPCNT
, &mmc_base
->blk
);
385 if (data
->flags
& MMC_DATA_READ
)
386 flags
|= (DP_DATA
| DDIR_READ
);
388 flags
|= (DP_DATA
| DDIR_WRITE
);
391 writel(cmd
->cmdarg
, &mmc_base
->arg
);
392 udelay(20); /* To fix "No status update" error on eMMC */
393 writel((cmd
->cmdidx
<< 24) | flags
, &mmc_base
->cmd
);
395 start
= get_timer(0);
397 mmc_stat
= readl(&mmc_base
->stat
);
398 if (get_timer(0) - start
> MAX_RETRY_MS
) {
399 printf("%s : timeout: No status update\n", __func__
);
404 if ((mmc_stat
& IE_CTO
) != 0) {
405 mmc_reset_controller_fsm(mmc_base
, SYSCTL_SRC
);
407 } else if ((mmc_stat
& ERRI_MASK
) != 0)
410 if (mmc_stat
& CC_MASK
) {
411 writel(CC_MASK
, &mmc_base
->stat
);
412 if (cmd
->resp_type
& MMC_RSP_PRESENT
) {
413 if (cmd
->resp_type
& MMC_RSP_136
) {
414 /* response type 2 */
415 cmd
->response
[3] = readl(&mmc_base
->rsp10
);
416 cmd
->response
[2] = readl(&mmc_base
->rsp32
);
417 cmd
->response
[1] = readl(&mmc_base
->rsp54
);
418 cmd
->response
[0] = readl(&mmc_base
->rsp76
);
420 /* response types 1, 1b, 3, 4, 5, 6 */
421 cmd
->response
[0] = readl(&mmc_base
->rsp10
);
425 if (data
&& (data
->flags
& MMC_DATA_READ
)) {
426 mmc_read_data(mmc_base
, data
->dest
,
427 data
->blocksize
* data
->blocks
);
428 } else if (data
&& (data
->flags
& MMC_DATA_WRITE
)) {
429 mmc_write_data(mmc_base
, data
->src
,
430 data
->blocksize
* data
->blocks
);
435 static int mmc_read_data(struct hsmmc
*mmc_base
, char *buf
, unsigned int size
)
437 unsigned int *output_buf
= (unsigned int *)buf
;
438 unsigned int mmc_stat
;
444 count
= (size
> MMCSD_SECTOR_SIZE
) ? MMCSD_SECTOR_SIZE
: size
;
448 ulong start
= get_timer(0);
450 mmc_stat
= readl(&mmc_base
->stat
);
451 if (get_timer(0) - start
> MAX_RETRY_MS
) {
452 printf("%s: timedout waiting for status!\n",
456 } while (mmc_stat
== 0);
458 if ((mmc_stat
& (IE_DTO
| IE_DCRC
| IE_DEB
)) != 0)
459 mmc_reset_controller_fsm(mmc_base
, SYSCTL_SRD
);
461 if ((mmc_stat
& ERRI_MASK
) != 0)
464 if (mmc_stat
& BRR_MASK
) {
467 writel(readl(&mmc_base
->stat
) | BRR_MASK
,
469 for (k
= 0; k
< count
; k
++) {
470 *output_buf
= readl(&mmc_base
->data
);
476 if (mmc_stat
& BWR_MASK
)
477 writel(readl(&mmc_base
->stat
) | BWR_MASK
,
480 if (mmc_stat
& TC_MASK
) {
481 writel(readl(&mmc_base
->stat
) | TC_MASK
,
489 static int mmc_write_data(struct hsmmc
*mmc_base
, const char *buf
,
492 unsigned int *input_buf
= (unsigned int *)buf
;
493 unsigned int mmc_stat
;
499 count
= (size
> MMCSD_SECTOR_SIZE
) ? MMCSD_SECTOR_SIZE
: size
;
503 ulong start
= get_timer(0);
505 mmc_stat
= readl(&mmc_base
->stat
);
506 if (get_timer(0) - start
> MAX_RETRY_MS
) {
507 printf("%s: timedout waiting for status!\n",
511 } while (mmc_stat
== 0);
513 if ((mmc_stat
& (IE_DTO
| IE_DCRC
| IE_DEB
)) != 0)
514 mmc_reset_controller_fsm(mmc_base
, SYSCTL_SRD
);
516 if ((mmc_stat
& ERRI_MASK
) != 0)
519 if (mmc_stat
& BWR_MASK
) {
522 writel(readl(&mmc_base
->stat
) | BWR_MASK
,
524 for (k
= 0; k
< count
; k
++) {
525 writel(*input_buf
, &mmc_base
->data
);
531 if (mmc_stat
& BRR_MASK
)
532 writel(readl(&mmc_base
->stat
) | BRR_MASK
,
535 if (mmc_stat
& TC_MASK
) {
536 writel(readl(&mmc_base
->stat
) | TC_MASK
,
544 static void omap_hsmmc_set_ios(struct mmc
*mmc
)
546 struct hsmmc
*mmc_base
;
547 unsigned int dsor
= 0;
550 mmc_base
= ((struct omap_hsmmc_data
*)mmc
->priv
)->base_addr
;
551 /* configue bus width */
552 switch (mmc
->bus_width
) {
554 writel(readl(&mmc_base
->con
) | DTW_8_BITMODE
,
559 writel(readl(&mmc_base
->con
) & ~DTW_8_BITMODE
,
561 writel(readl(&mmc_base
->hctl
) | DTW_4_BITMODE
,
567 writel(readl(&mmc_base
->con
) & ~DTW_8_BITMODE
,
569 writel(readl(&mmc_base
->hctl
) & ~DTW_4_BITMODE
,
574 /* configure clock with 96Mhz system clock.
576 if (mmc
->clock
!= 0) {
577 dsor
= (MMC_CLOCK_REFERENCE
* 1000000 / mmc
->clock
);
578 if ((MMC_CLOCK_REFERENCE
* 1000000) / dsor
> mmc
->clock
)
582 mmc_reg_out(&mmc_base
->sysctl
, (ICE_MASK
| DTO_MASK
| CEN_MASK
),
583 (ICE_STOP
| DTO_15THDTO
| CEN_DISABLE
));
585 mmc_reg_out(&mmc_base
->sysctl
, ICE_MASK
| CLKD_MASK
,
586 (dsor
<< CLKD_OFFSET
) | ICE_OSCILLATE
);
588 start
= get_timer(0);
589 while ((readl(&mmc_base
->sysctl
) & ICS_MASK
) == ICS_NOTREADY
) {
590 if (get_timer(0) - start
> MAX_RETRY_MS
) {
591 printf("%s: timedout waiting for ics!\n", __func__
);
595 writel(readl(&mmc_base
->sysctl
) | CEN_ENABLE
, &mmc_base
->sysctl
);
598 #ifdef OMAP_HSMMC_USE_GPIO
599 static int omap_hsmmc_getcd(struct mmc
*mmc
)
601 struct omap_hsmmc_data
*priv_data
= mmc
->priv
;
604 /* if no CD return as 1 */
605 cd_gpio
= priv_data
->cd_gpio
;
609 return gpio_get_value(cd_gpio
);
612 static int omap_hsmmc_getwp(struct mmc
*mmc
)
614 struct omap_hsmmc_data
*priv_data
= mmc
->priv
;
617 /* if no WP return as 0 */
618 wp_gpio
= priv_data
->wp_gpio
;
622 return gpio_get_value(wp_gpio
);
626 static const struct mmc_ops omap_hsmmc_ops
= {
627 .send_cmd
= omap_hsmmc_send_cmd
,
628 .set_ios
= omap_hsmmc_set_ios
,
629 .init
= omap_hsmmc_init_setup
,
630 #ifdef OMAP_HSMMC_USE_GPIO
631 .getcd
= omap_hsmmc_getcd
,
632 .getwp
= omap_hsmmc_getwp
,
636 int omap_mmc_init(int dev_index
, uint host_caps_mask
, uint f_max
, int cd_gpio
,
639 struct mmc
*mmc
= &hsmmc_dev
[dev_index
];
640 struct omap_hsmmc_data
*priv_data
= &hsmmc_dev_data
[dev_index
];
641 uint host_caps_val
= MMC_MODE_4BIT
| MMC_MODE_HS_52MHz
| MMC_MODE_HS
|
644 sprintf(mmc
->name
, "OMAP SD/MMC");
645 mmc
->ops
= &omap_hsmmc_ops
;
646 mmc
->priv
= priv_data
;
650 priv_data
->base_addr
= (struct hsmmc
*)OMAP_HSMMC1_BASE
;
652 #ifdef OMAP_HSMMC2_BASE
654 priv_data
->base_addr
= (struct hsmmc
*)OMAP_HSMMC2_BASE
;
655 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
656 defined(CONFIG_DRA7XX)) && defined(CONFIG_HSMMC2_8BIT)
657 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
658 host_caps_val
|= MMC_MODE_8BIT
;
662 #ifdef OMAP_HSMMC3_BASE
664 priv_data
->base_addr
= (struct hsmmc
*)OMAP_HSMMC3_BASE
;
665 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
666 /* Enable 8-bit interface for eMMC on DRA7XX */
667 host_caps_val
|= MMC_MODE_8BIT
;
672 priv_data
->base_addr
= (struct hsmmc
*)OMAP_HSMMC1_BASE
;
675 #ifdef OMAP_HSMMC_USE_GPIO
676 /* on error gpio values are set to -1, which is what we want */
677 priv_data
->cd_gpio
= omap_mmc_setup_gpio_in(cd_gpio
, "mmc_cd");
678 priv_data
->wp_gpio
= omap_mmc_setup_gpio_in(wp_gpio
, "mmc_wp");
681 mmc
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
;
682 mmc
->host_caps
= host_caps_val
& ~host_caps_mask
;
689 if (mmc
->host_caps
& MMC_MODE_HS
) {
690 if (mmc
->host_caps
& MMC_MODE_HS_52MHz
)
691 mmc
->f_max
= 52000000;
693 mmc
->f_max
= 26000000;
695 mmc
->f_max
= 20000000;
700 #if defined(CONFIG_OMAP34XX)
702 * Silicon revs 2.1 and older do not support multiblock transfers.
704 if ((get_cpu_family() == CPU_OMAP34XX
) && (get_cpu_rev() <= CPU_3XX_ES21
))