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[people/ms/u-boot.git] / drivers / mmc / omap_hsmmc.c
1 /*
2 * (C) Copyright 2008
3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
12 * the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25 #include <config.h>
26 #include <common.h>
27 #include <malloc.h>
28 #include <memalign.h>
29 #include <mmc.h>
30 #include <part.h>
31 #include <i2c.h>
32 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
33 #include <palmas.h>
34 #endif
35 #include <asm/io.h>
36 #include <asm/arch/mmc_host_def.h>
37 #ifdef CONFIG_OMAP54XX
38 #include <asm/arch/mux_dra7xx.h>
39 #include <asm/arch/dra7xx_iodelay.h>
40 #endif
41 #if !defined(CONFIG_SOC_KEYSTONE)
42 #include <asm/gpio.h>
43 #include <asm/arch/sys_proto.h>
44 #endif
45 #ifdef CONFIG_MMC_OMAP36XX_PINS
46 #include <asm/arch/mux.h>
47 #endif
48 #include <dm.h>
49
50 DECLARE_GLOBAL_DATA_PTR;
51
52 /* simplify defines to OMAP_HSMMC_USE_GPIO */
53 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
54 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
55 #define OMAP_HSMMC_USE_GPIO
56 #else
57 #undef OMAP_HSMMC_USE_GPIO
58 #endif
59
60 /* common definitions for all OMAPs */
61 #define SYSCTL_SRC (1 << 25)
62 #define SYSCTL_SRD (1 << 26)
63
64 #ifdef CONFIG_IODELAY_RECALIBRATION
65 struct omap_hsmmc_pinctrl_state {
66 struct pad_conf_entry *padconf;
67 int npads;
68 struct iodelay_cfg_entry *iodelay;
69 int niodelays;
70 };
71 #endif
72
73 struct omap_hsmmc_data {
74 struct hsmmc *base_addr;
75 #if !CONFIG_IS_ENABLED(DM_MMC)
76 struct mmc_config cfg;
77 #endif
78 uint bus_width;
79 uint clock;
80 #ifdef OMAP_HSMMC_USE_GPIO
81 #if CONFIG_IS_ENABLED(DM_MMC)
82 struct gpio_desc cd_gpio; /* Change Detect GPIO */
83 struct gpio_desc wp_gpio; /* Write Protect GPIO */
84 bool cd_inverted;
85 #else
86 int cd_gpio;
87 int wp_gpio;
88 #endif
89 #endif
90 #if CONFIG_IS_ENABLED(DM_MMC)
91 uint iov;
92 enum bus_mode mode;
93 #endif
94 u8 controller_flags;
95 #ifndef CONFIG_OMAP34XX
96 struct omap_hsmmc_adma_desc *adma_desc_table;
97 uint desc_slot;
98 #endif
99 const char *hw_rev;
100 #ifdef CONFIG_IODELAY_RECALIBRATION
101 struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
102 struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
103 struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
104 struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
105 struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
106 struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
107 struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
108 struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
109 struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
110 #endif
111 };
112
113 struct omap_mmc_of_data {
114 u8 controller_flags;
115 };
116
117 #ifndef CONFIG_OMAP34XX
118 struct omap_hsmmc_adma_desc {
119 u8 attr;
120 u8 reserved;
121 u16 len;
122 u32 addr;
123 };
124
125 #define ADMA_MAX_LEN 63488
126
127 /* Decriptor table defines */
128 #define ADMA_DESC_ATTR_VALID BIT(0)
129 #define ADMA_DESC_ATTR_END BIT(1)
130 #define ADMA_DESC_ATTR_INT BIT(2)
131 #define ADMA_DESC_ATTR_ACT1 BIT(4)
132 #define ADMA_DESC_ATTR_ACT2 BIT(5)
133
134 #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
135 #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
136 #endif
137
138 /* If we fail after 1 second wait, something is really bad */
139 #define MAX_RETRY_MS 1000
140 #define MMC_TIMEOUT_MS 20
141
142 /* DMA transfers can take a long time if a lot a data is transferred.
143 * The timeout must take in account the amount of data. Let's assume
144 * that the time will never exceed 333 ms per MB (in other word we assume
145 * that the bandwidth is always above 3MB/s).
146 */
147 #define DMA_TIMEOUT_PER_MB 333
148 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0)
149 #define OMAP_HSMMC_NO_1_8_V BIT(1)
150 #define OMAP_HSMMC_USE_ADMA BIT(2)
151 #define OMAP_HSMMC_REQUIRE_IODELAY BIT(3)
152
153 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
154 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
155 unsigned int siz);
156 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
157 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
158 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
159
160 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
161 {
162 #if CONFIG_IS_ENABLED(DM_MMC)
163 return dev_get_priv(mmc->dev);
164 #else
165 return (struct omap_hsmmc_data *)mmc->priv;
166 #endif
167 }
168 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
169 {
170 #if CONFIG_IS_ENABLED(DM_MMC)
171 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
172 return &plat->cfg;
173 #else
174 return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
175 #endif
176 }
177
178 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
179 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
180 {
181 int ret;
182
183 #ifndef CONFIG_DM_GPIO
184 if (!gpio_is_valid(gpio))
185 return -1;
186 #endif
187 ret = gpio_request(gpio, label);
188 if (ret)
189 return ret;
190
191 ret = gpio_direction_input(gpio);
192 if (ret)
193 return ret;
194
195 return gpio;
196 }
197 #endif
198
199 static unsigned char mmc_board_init(struct mmc *mmc)
200 {
201 #if defined(CONFIG_OMAP34XX)
202 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
203 t2_t *t2_base = (t2_t *)T2_BASE;
204 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
205 u32 pbias_lite;
206 #ifdef CONFIG_MMC_OMAP36XX_PINS
207 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
208 #endif
209
210 pbias_lite = readl(&t2_base->pbias_lite);
211 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
212 #ifdef CONFIG_TARGET_OMAP3_CAIRO
213 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
214 pbias_lite &= ~PBIASLITEVMODE0;
215 #endif
216 #ifdef CONFIG_MMC_OMAP36XX_PINS
217 if (get_cpu_family() == CPU_OMAP36XX) {
218 /* Disable extended drain IO before changing PBIAS */
219 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
220 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
221 }
222 #endif
223 writel(pbias_lite, &t2_base->pbias_lite);
224
225 writel(pbias_lite | PBIASLITEPWRDNZ1 |
226 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
227 &t2_base->pbias_lite);
228
229 #ifdef CONFIG_MMC_OMAP36XX_PINS
230 if (get_cpu_family() == CPU_OMAP36XX)
231 /* Enable extended drain IO after changing PBIAS */
232 writel(wkup_ctrl |
233 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
234 OMAP34XX_CTRL_WKUP_CTRL);
235 #endif
236 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
237 &t2_base->devconf0);
238
239 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
240 &t2_base->devconf1);
241
242 /* Change from default of 52MHz to 26MHz if necessary */
243 if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
244 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
245 &t2_base->ctl_prog_io1);
246
247 writel(readl(&prcm_base->fclken1_core) |
248 EN_MMC1 | EN_MMC2 | EN_MMC3,
249 &prcm_base->fclken1_core);
250
251 writel(readl(&prcm_base->iclken1_core) |
252 EN_MMC1 | EN_MMC2 | EN_MMC3,
253 &prcm_base->iclken1_core);
254 #endif
255
256 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
257 /* PBIAS config needed for MMC1 only */
258 if (mmc_get_blk_desc(mmc)->devnum == 0)
259 vmmc_pbias_config(LDO_VOLT_3V0);
260 #endif
261
262 return 0;
263 }
264
265 void mmc_init_stream(struct hsmmc *mmc_base)
266 {
267 ulong start;
268
269 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
270
271 writel(MMC_CMD0, &mmc_base->cmd);
272 start = get_timer(0);
273 while (!(readl(&mmc_base->stat) & CC_MASK)) {
274 if (get_timer(0) - start > MAX_RETRY_MS) {
275 printf("%s: timedout waiting for cc!\n", __func__);
276 return;
277 }
278 }
279 writel(CC_MASK, &mmc_base->stat)
280 ;
281 writel(MMC_CMD0, &mmc_base->cmd)
282 ;
283 start = get_timer(0);
284 while (!(readl(&mmc_base->stat) & CC_MASK)) {
285 if (get_timer(0) - start > MAX_RETRY_MS) {
286 printf("%s: timedout waiting for cc2!\n", __func__);
287 return;
288 }
289 }
290 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
291 }
292
293 #if CONFIG_IS_ENABLED(DM_MMC)
294 #ifdef CONFIG_IODELAY_RECALIBRATION
295 static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
296 {
297 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
298 struct omap_hsmmc_pinctrl_state *pinctrl_state;
299
300 switch (priv->mode) {
301 case MMC_HS_200:
302 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
303 break;
304 case UHS_SDR104:
305 pinctrl_state = priv->sdr104_pinctrl_state;
306 break;
307 case UHS_SDR50:
308 pinctrl_state = priv->sdr50_pinctrl_state;
309 break;
310 case UHS_DDR50:
311 pinctrl_state = priv->ddr50_pinctrl_state;
312 break;
313 case UHS_SDR25:
314 pinctrl_state = priv->sdr25_pinctrl_state;
315 break;
316 case UHS_SDR12:
317 pinctrl_state = priv->sdr12_pinctrl_state;
318 break;
319 case SD_HS:
320 case MMC_HS:
321 case MMC_HS_52:
322 pinctrl_state = priv->hs_pinctrl_state;
323 break;
324 case MMC_DDR_52:
325 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
326 default:
327 pinctrl_state = priv->default_pinctrl_state;
328 break;
329 }
330
331 if (!pinctrl_state)
332 pinctrl_state = priv->default_pinctrl_state;
333
334 if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
335 if (pinctrl_state->iodelay)
336 late_recalibrate_iodelay(pinctrl_state->padconf,
337 pinctrl_state->npads,
338 pinctrl_state->iodelay,
339 pinctrl_state->niodelays);
340 else
341 do_set_mux32((*ctrl)->control_padconf_core_base,
342 pinctrl_state->padconf,
343 pinctrl_state->npads);
344 }
345 }
346 #endif
347 static void omap_hsmmc_set_timing(struct mmc *mmc)
348 {
349 u32 val;
350 struct hsmmc *mmc_base;
351 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
352
353 mmc_base = priv->base_addr;
354
355 omap_hsmmc_stop_clock(mmc_base);
356 val = readl(&mmc_base->ac12);
357 val &= ~AC12_UHSMC_MASK;
358 priv->mode = mmc->selected_mode;
359
360 if (mmc_is_mode_ddr(priv->mode))
361 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
362 else
363 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
364
365 switch (priv->mode) {
366 case MMC_HS_200:
367 case UHS_SDR104:
368 val |= AC12_UHSMC_SDR104;
369 break;
370 case UHS_SDR50:
371 val |= AC12_UHSMC_SDR50;
372 break;
373 case MMC_DDR_52:
374 case UHS_DDR50:
375 val |= AC12_UHSMC_DDR50;
376 break;
377 case SD_HS:
378 case MMC_HS_52:
379 case UHS_SDR25:
380 val |= AC12_UHSMC_SDR25;
381 break;
382 case MMC_LEGACY:
383 case MMC_HS:
384 case SD_LEGACY:
385 case UHS_SDR12:
386 val |= AC12_UHSMC_SDR12;
387 break;
388 default:
389 val |= AC12_UHSMC_RES;
390 break;
391 }
392 writel(val, &mmc_base->ac12);
393
394 #ifdef CONFIG_IODELAY_RECALIBRATION
395 omap_hsmmc_io_recalibrate(mmc);
396 #endif
397 omap_hsmmc_start_clock(mmc_base);
398 }
399
400 static void omap_hsmmc_conf_bus_power(struct mmc *mmc)
401 {
402 struct hsmmc *mmc_base;
403 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
404 u32 val;
405
406 mmc_base = priv->base_addr;
407
408 val = readl(&mmc_base->hctl) & ~SDVS_MASK;
409
410 switch (priv->iov) {
411 case IOV_3V3:
412 val |= SDVS_3V3;
413 break;
414 case IOV_3V0:
415 val |= SDVS_3V0;
416 break;
417 case IOV_1V8:
418 val |= SDVS_1V8;
419 break;
420 }
421
422 writel(val, &mmc_base->hctl);
423 }
424
425 static void omap_hsmmc_set_capabilities(struct mmc *mmc)
426 {
427 struct hsmmc *mmc_base;
428 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
429 u32 val;
430
431 mmc_base = priv->base_addr;
432 val = readl(&mmc_base->capa);
433
434 if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
435 val |= (VS30_3V0SUP | VS18_1V8SUP);
436 priv->iov = IOV_3V0;
437 } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
438 val |= VS30_3V0SUP;
439 val &= ~VS18_1V8SUP;
440 priv->iov = IOV_3V0;
441 } else {
442 val |= VS18_1V8SUP;
443 val &= ~VS30_3V0SUP;
444 priv->iov = IOV_1V8;
445 }
446
447 writel(val, &mmc_base->capa);
448 }
449
450 #ifdef MMC_SUPPORTS_TUNING
451 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
452 {
453 struct hsmmc *mmc_base;
454 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
455 u32 val;
456
457 mmc_base = priv->base_addr;
458 val = readl(&mmc_base->ac12);
459 val &= ~(AC12_SCLK_SEL);
460 writel(val, &mmc_base->ac12);
461
462 val = readl(&mmc_base->dll);
463 val &= ~(DLL_FORCE_VALUE | DLL_SWT);
464 writel(val, &mmc_base->dll);
465 }
466
467 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
468 {
469 int i;
470 struct hsmmc *mmc_base;
471 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
472 u32 val;
473
474 mmc_base = priv->base_addr;
475 val = readl(&mmc_base->dll);
476 val |= DLL_FORCE_VALUE;
477 val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
478 val |= (count << DLL_FORCE_SR_C_SHIFT);
479 writel(val, &mmc_base->dll);
480
481 val |= DLL_CALIB;
482 writel(val, &mmc_base->dll);
483 for (i = 0; i < 1000; i++) {
484 if (readl(&mmc_base->dll) & DLL_CALIB)
485 break;
486 }
487 val &= ~DLL_CALIB;
488 writel(val, &mmc_base->dll);
489 }
490
491 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
492 {
493 struct omap_hsmmc_data *priv = dev_get_priv(dev);
494 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
495 struct mmc *mmc = upriv->mmc;
496 struct hsmmc *mmc_base;
497 u32 val;
498 u8 cur_match, prev_match = 0;
499 int ret;
500 u32 phase_delay = 0;
501 u32 start_window = 0, max_window = 0;
502 u32 length = 0, max_len = 0;
503
504 mmc_base = priv->base_addr;
505 val = readl(&mmc_base->capa2);
506
507 /* clock tuning is not needed for upto 52MHz */
508 if (!((mmc->selected_mode == MMC_HS_200) ||
509 (mmc->selected_mode == UHS_SDR104) ||
510 ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
511 return 0;
512
513 val = readl(&mmc_base->dll);
514 val |= DLL_SWT;
515 writel(val, &mmc_base->dll);
516 while (phase_delay <= MAX_PHASE_DELAY) {
517 omap_hsmmc_set_dll(mmc, phase_delay);
518
519 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
520
521 if (cur_match) {
522 if (prev_match) {
523 length++;
524 } else {
525 start_window = phase_delay;
526 length = 1;
527 }
528 }
529
530 if (length > max_len) {
531 max_window = start_window;
532 max_len = length;
533 }
534
535 prev_match = cur_match;
536 phase_delay += 4;
537 }
538
539 if (!max_len) {
540 ret = -EIO;
541 goto tuning_error;
542 }
543
544 val = readl(&mmc_base->ac12);
545 if (!(val & AC12_SCLK_SEL)) {
546 ret = -EIO;
547 goto tuning_error;
548 }
549
550 phase_delay = max_window + 4 * ((3 * max_len) >> 2);
551 omap_hsmmc_set_dll(mmc, phase_delay);
552
553 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
554 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
555
556 return 0;
557
558 tuning_error:
559
560 omap_hsmmc_disable_tuning(mmc);
561 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
562 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
563
564 return ret;
565 }
566 #endif
567 #endif
568
569 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
570 {
571 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
572 struct hsmmc *mmc_base = priv->base_addr;
573 u32 irq_mask = INT_EN_MASK;
574
575 /*
576 * TODO: Errata i802 indicates only DCRC interrupts can occur during
577 * tuning procedure and DCRC should be disabled. But see occurences
578 * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
579 * interrupts occur along with BRR, so the data is actually in the
580 * buffer. It has to be debugged why these interrutps occur
581 */
582 if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
583 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
584
585 writel(irq_mask, &mmc_base->ie);
586 }
587
588 static int omap_hsmmc_init_setup(struct mmc *mmc)
589 {
590 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
591 struct hsmmc *mmc_base;
592 unsigned int reg_val;
593 unsigned int dsor;
594 ulong start;
595
596 mmc_base = priv->base_addr;
597 mmc_board_init(mmc);
598
599 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
600 &mmc_base->sysconfig);
601 start = get_timer(0);
602 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
603 if (get_timer(0) - start > MAX_RETRY_MS) {
604 printf("%s: timedout waiting for cc2!\n", __func__);
605 return -ETIMEDOUT;
606 }
607 }
608 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
609 start = get_timer(0);
610 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
611 if (get_timer(0) - start > MAX_RETRY_MS) {
612 printf("%s: timedout waiting for softresetall!\n",
613 __func__);
614 return -ETIMEDOUT;
615 }
616 }
617 #ifndef CONFIG_OMAP34XX
618 reg_val = readl(&mmc_base->hl_hwinfo);
619 if (reg_val & MADMA_EN)
620 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
621 #endif
622
623 #if CONFIG_IS_ENABLED(DM_MMC)
624 omap_hsmmc_set_capabilities(mmc);
625 omap_hsmmc_conf_bus_power(mmc);
626 #else
627 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
628 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
629 &mmc_base->capa);
630 #endif
631
632 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
633
634 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
635 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
636 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
637
638 dsor = 240;
639 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
640 (ICE_STOP | DTO_15THDTO));
641 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
642 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
643 start = get_timer(0);
644 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
645 if (get_timer(0) - start > MAX_RETRY_MS) {
646 printf("%s: timedout waiting for ics!\n", __func__);
647 return -ETIMEDOUT;
648 }
649 }
650 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
651
652 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
653
654 mmc_enable_irq(mmc, NULL);
655 mmc_init_stream(mmc_base);
656
657 return 0;
658 }
659
660 /*
661 * MMC controller internal finite state machine reset
662 *
663 * Used to reset command or data internal state machines, using respectively
664 * SRC or SRD bit of SYSCTL register
665 */
666 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
667 {
668 ulong start;
669
670 mmc_reg_out(&mmc_base->sysctl, bit, bit);
671
672 /*
673 * CMD(DAT) lines reset procedures are slightly different
674 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
675 * According to OMAP3 TRM:
676 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
677 * returns to 0x0.
678 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
679 * procedure steps must be as follows:
680 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
681 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
682 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
683 * 3. Wait until the SRC (SRD) bit returns to 0x0
684 * (reset procedure is completed).
685 */
686 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
687 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
688 if (!(readl(&mmc_base->sysctl) & bit)) {
689 start = get_timer(0);
690 while (!(readl(&mmc_base->sysctl) & bit)) {
691 if (get_timer(0) - start > MMC_TIMEOUT_MS)
692 return;
693 }
694 }
695 #endif
696 start = get_timer(0);
697 while ((readl(&mmc_base->sysctl) & bit) != 0) {
698 if (get_timer(0) - start > MAX_RETRY_MS) {
699 printf("%s: timedout waiting for sysctl %x to clear\n",
700 __func__, bit);
701 return;
702 }
703 }
704 }
705
706 #ifndef CONFIG_OMAP34XX
707 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
708 {
709 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
710 struct omap_hsmmc_adma_desc *desc;
711 u8 attr;
712
713 desc = &priv->adma_desc_table[priv->desc_slot];
714
715 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
716 if (!end)
717 priv->desc_slot++;
718 else
719 attr |= ADMA_DESC_ATTR_END;
720
721 desc->len = len;
722 desc->addr = (u32)buf;
723 desc->reserved = 0;
724 desc->attr = attr;
725 }
726
727 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
728 struct mmc_data *data)
729 {
730 uint total_len = data->blocksize * data->blocks;
731 uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
732 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
733 int i = desc_count;
734 char *buf;
735
736 priv->desc_slot = 0;
737 priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
738 memalign(ARCH_DMA_MINALIGN, desc_count *
739 sizeof(struct omap_hsmmc_adma_desc));
740
741 if (data->flags & MMC_DATA_READ)
742 buf = data->dest;
743 else
744 buf = (char *)data->src;
745
746 while (--i) {
747 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
748 buf += ADMA_MAX_LEN;
749 total_len -= ADMA_MAX_LEN;
750 }
751
752 omap_hsmmc_adma_desc(mmc, buf, total_len, true);
753
754 flush_dcache_range((long)priv->adma_desc_table,
755 (long)priv->adma_desc_table +
756 ROUND(desc_count *
757 sizeof(struct omap_hsmmc_adma_desc),
758 ARCH_DMA_MINALIGN));
759 }
760
761 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
762 {
763 struct hsmmc *mmc_base;
764 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
765 u32 val;
766 char *buf;
767
768 mmc_base = priv->base_addr;
769 omap_hsmmc_prepare_adma_table(mmc, data);
770
771 if (data->flags & MMC_DATA_READ)
772 buf = data->dest;
773 else
774 buf = (char *)data->src;
775
776 val = readl(&mmc_base->hctl);
777 val |= DMA_SELECT;
778 writel(val, &mmc_base->hctl);
779
780 val = readl(&mmc_base->con);
781 val |= DMA_MASTER;
782 writel(val, &mmc_base->con);
783
784 writel((u32)priv->adma_desc_table, &mmc_base->admasal);
785
786 flush_dcache_range((u32)buf,
787 (u32)buf +
788 ROUND(data->blocksize * data->blocks,
789 ARCH_DMA_MINALIGN));
790 }
791
792 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
793 {
794 struct hsmmc *mmc_base;
795 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
796 u32 val;
797
798 mmc_base = priv->base_addr;
799
800 val = readl(&mmc_base->con);
801 val &= ~DMA_MASTER;
802 writel(val, &mmc_base->con);
803
804 val = readl(&mmc_base->hctl);
805 val &= ~DMA_SELECT;
806 writel(val, &mmc_base->hctl);
807
808 kfree(priv->adma_desc_table);
809 }
810 #else
811 #define omap_hsmmc_adma_desc
812 #define omap_hsmmc_prepare_adma_table
813 #define omap_hsmmc_prepare_data
814 #define omap_hsmmc_dma_cleanup
815 #endif
816
817 #if !CONFIG_IS_ENABLED(DM_MMC)
818 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
819 struct mmc_data *data)
820 {
821 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
822 #else
823 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
824 struct mmc_data *data)
825 {
826 struct omap_hsmmc_data *priv = dev_get_priv(dev);
827 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
828 struct mmc *mmc = upriv->mmc;
829 #endif
830 struct hsmmc *mmc_base;
831 unsigned int flags, mmc_stat;
832 ulong start;
833
834 mmc_base = priv->base_addr;
835
836 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
837 return 0;
838
839 start = get_timer(0);
840 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
841 if (get_timer(0) - start > MAX_RETRY_MS) {
842 printf("%s: timedout waiting on cmd inhibit to clear\n",
843 __func__);
844 return -ETIMEDOUT;
845 }
846 }
847 writel(0xFFFFFFFF, &mmc_base->stat);
848 start = get_timer(0);
849 while (readl(&mmc_base->stat)) {
850 if (get_timer(0) - start > MAX_RETRY_MS) {
851 printf("%s: timedout waiting for STAT (%x) to clear\n",
852 __func__, readl(&mmc_base->stat));
853 return -ETIMEDOUT;
854 }
855 }
856 /*
857 * CMDREG
858 * CMDIDX[13:8] : Command index
859 * DATAPRNT[5] : Data Present Select
860 * ENCMDIDX[4] : Command Index Check Enable
861 * ENCMDCRC[3] : Command CRC Check Enable
862 * RSPTYP[1:0]
863 * 00 = No Response
864 * 01 = Length 136
865 * 10 = Length 48
866 * 11 = Length 48 Check busy after response
867 */
868 /* Delay added before checking the status of frq change
869 * retry not supported by mmc.c(core file)
870 */
871 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
872 udelay(50000); /* wait 50 ms */
873
874 if (!(cmd->resp_type & MMC_RSP_PRESENT))
875 flags = 0;
876 else if (cmd->resp_type & MMC_RSP_136)
877 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
878 else if (cmd->resp_type & MMC_RSP_BUSY)
879 flags = RSP_TYPE_LGHT48B;
880 else
881 flags = RSP_TYPE_LGHT48;
882
883 /* enable default flags */
884 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
885 MSBS_SGLEBLK);
886 flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
887
888 if (cmd->resp_type & MMC_RSP_CRC)
889 flags |= CCCE_CHECK;
890 if (cmd->resp_type & MMC_RSP_OPCODE)
891 flags |= CICE_CHECK;
892
893 if (data) {
894 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
895 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
896 flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
897 data->blocksize = 512;
898 writel(data->blocksize | (data->blocks << 16),
899 &mmc_base->blk);
900 } else
901 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
902
903 if (data->flags & MMC_DATA_READ)
904 flags |= (DP_DATA | DDIR_READ);
905 else
906 flags |= (DP_DATA | DDIR_WRITE);
907
908 #ifndef CONFIG_OMAP34XX
909 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
910 !mmc_is_tuning_cmd(cmd->cmdidx)) {
911 omap_hsmmc_prepare_data(mmc, data);
912 flags |= DE_ENABLE;
913 }
914 #endif
915 }
916
917 mmc_enable_irq(mmc, cmd);
918
919 writel(cmd->cmdarg, &mmc_base->arg);
920 udelay(20); /* To fix "No status update" error on eMMC */
921 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
922
923 start = get_timer(0);
924 do {
925 mmc_stat = readl(&mmc_base->stat);
926 if (get_timer(start) > MAX_RETRY_MS) {
927 printf("%s : timeout: No status update\n", __func__);
928 return -ETIMEDOUT;
929 }
930 } while (!mmc_stat);
931
932 if ((mmc_stat & IE_CTO) != 0) {
933 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
934 return -ETIMEDOUT;
935 } else if ((mmc_stat & ERRI_MASK) != 0)
936 return -1;
937
938 if (mmc_stat & CC_MASK) {
939 writel(CC_MASK, &mmc_base->stat);
940 if (cmd->resp_type & MMC_RSP_PRESENT) {
941 if (cmd->resp_type & MMC_RSP_136) {
942 /* response type 2 */
943 cmd->response[3] = readl(&mmc_base->rsp10);
944 cmd->response[2] = readl(&mmc_base->rsp32);
945 cmd->response[1] = readl(&mmc_base->rsp54);
946 cmd->response[0] = readl(&mmc_base->rsp76);
947 } else
948 /* response types 1, 1b, 3, 4, 5, 6 */
949 cmd->response[0] = readl(&mmc_base->rsp10);
950 }
951 }
952
953 #ifndef CONFIG_OMAP34XX
954 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
955 !mmc_is_tuning_cmd(cmd->cmdidx)) {
956 u32 sz_mb, timeout;
957
958 if (mmc_stat & IE_ADMAE) {
959 omap_hsmmc_dma_cleanup(mmc);
960 return -EIO;
961 }
962
963 sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
964 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
965 if (timeout < MAX_RETRY_MS)
966 timeout = MAX_RETRY_MS;
967
968 start = get_timer(0);
969 do {
970 mmc_stat = readl(&mmc_base->stat);
971 if (mmc_stat & TC_MASK) {
972 writel(readl(&mmc_base->stat) | TC_MASK,
973 &mmc_base->stat);
974 break;
975 }
976 if (get_timer(start) > timeout) {
977 printf("%s : DMA timeout: No status update\n",
978 __func__);
979 return -ETIMEDOUT;
980 }
981 } while (1);
982
983 omap_hsmmc_dma_cleanup(mmc);
984 return 0;
985 }
986 #endif
987
988 if (data && (data->flags & MMC_DATA_READ)) {
989 mmc_read_data(mmc_base, data->dest,
990 data->blocksize * data->blocks);
991 } else if (data && (data->flags & MMC_DATA_WRITE)) {
992 mmc_write_data(mmc_base, data->src,
993 data->blocksize * data->blocks);
994 }
995 return 0;
996 }
997
998 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
999 {
1000 unsigned int *output_buf = (unsigned int *)buf;
1001 unsigned int mmc_stat;
1002 unsigned int count;
1003
1004 /*
1005 * Start Polled Read
1006 */
1007 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1008 count /= 4;
1009
1010 while (size) {
1011 ulong start = get_timer(0);
1012 do {
1013 mmc_stat = readl(&mmc_base->stat);
1014 if (get_timer(0) - start > MAX_RETRY_MS) {
1015 printf("%s: timedout waiting for status!\n",
1016 __func__);
1017 return -ETIMEDOUT;
1018 }
1019 } while (mmc_stat == 0);
1020
1021 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1022 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1023
1024 if ((mmc_stat & ERRI_MASK) != 0)
1025 return 1;
1026
1027 if (mmc_stat & BRR_MASK) {
1028 unsigned int k;
1029
1030 writel(readl(&mmc_base->stat) | BRR_MASK,
1031 &mmc_base->stat);
1032 for (k = 0; k < count; k++) {
1033 *output_buf = readl(&mmc_base->data);
1034 output_buf++;
1035 }
1036 size -= (count*4);
1037 }
1038
1039 if (mmc_stat & BWR_MASK)
1040 writel(readl(&mmc_base->stat) | BWR_MASK,
1041 &mmc_base->stat);
1042
1043 if (mmc_stat & TC_MASK) {
1044 writel(readl(&mmc_base->stat) | TC_MASK,
1045 &mmc_base->stat);
1046 break;
1047 }
1048 }
1049 return 0;
1050 }
1051
1052 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1053 unsigned int size)
1054 {
1055 unsigned int *input_buf = (unsigned int *)buf;
1056 unsigned int mmc_stat;
1057 unsigned int count;
1058
1059 /*
1060 * Start Polled Write
1061 */
1062 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1063 count /= 4;
1064
1065 while (size) {
1066 ulong start = get_timer(0);
1067 do {
1068 mmc_stat = readl(&mmc_base->stat);
1069 if (get_timer(0) - start > MAX_RETRY_MS) {
1070 printf("%s: timedout waiting for status!\n",
1071 __func__);
1072 return -ETIMEDOUT;
1073 }
1074 } while (mmc_stat == 0);
1075
1076 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1077 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1078
1079 if ((mmc_stat & ERRI_MASK) != 0)
1080 return 1;
1081
1082 if (mmc_stat & BWR_MASK) {
1083 unsigned int k;
1084
1085 writel(readl(&mmc_base->stat) | BWR_MASK,
1086 &mmc_base->stat);
1087 for (k = 0; k < count; k++) {
1088 writel(*input_buf, &mmc_base->data);
1089 input_buf++;
1090 }
1091 size -= (count*4);
1092 }
1093
1094 if (mmc_stat & BRR_MASK)
1095 writel(readl(&mmc_base->stat) | BRR_MASK,
1096 &mmc_base->stat);
1097
1098 if (mmc_stat & TC_MASK) {
1099 writel(readl(&mmc_base->stat) | TC_MASK,
1100 &mmc_base->stat);
1101 break;
1102 }
1103 }
1104 return 0;
1105 }
1106
1107 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1108 {
1109 writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1110 }
1111
1112 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1113 {
1114 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1115 }
1116
1117 static void omap_hsmmc_set_clock(struct mmc *mmc)
1118 {
1119 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1120 struct hsmmc *mmc_base;
1121 unsigned int dsor = 0;
1122 ulong start;
1123
1124 mmc_base = priv->base_addr;
1125 omap_hsmmc_stop_clock(mmc_base);
1126
1127 /* TODO: Is setting DTO required here? */
1128 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1129 (ICE_STOP | DTO_15THDTO));
1130
1131 if (mmc->clock != 0) {
1132 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1133 if (dsor > CLKD_MAX)
1134 dsor = CLKD_MAX;
1135 } else {
1136 dsor = CLKD_MAX;
1137 }
1138
1139 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1140 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1141
1142 start = get_timer(0);
1143 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1144 if (get_timer(0) - start > MAX_RETRY_MS) {
1145 printf("%s: timedout waiting for ics!\n", __func__);
1146 return;
1147 }
1148 }
1149
1150 priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
1151 mmc->clock = priv->clock;
1152 omap_hsmmc_start_clock(mmc_base);
1153 }
1154
1155 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1156 {
1157 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1158 struct hsmmc *mmc_base;
1159
1160 mmc_base = priv->base_addr;
1161 /* configue bus width */
1162 switch (mmc->bus_width) {
1163 case 8:
1164 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1165 &mmc_base->con);
1166 break;
1167
1168 case 4:
1169 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1170 &mmc_base->con);
1171 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1172 &mmc_base->hctl);
1173 break;
1174
1175 case 1:
1176 default:
1177 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1178 &mmc_base->con);
1179 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1180 &mmc_base->hctl);
1181 break;
1182 }
1183
1184 priv->bus_width = mmc->bus_width;
1185 }
1186
1187 #if !CONFIG_IS_ENABLED(DM_MMC)
1188 static int omap_hsmmc_set_ios(struct mmc *mmc)
1189 {
1190 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1191 #else
1192 static int omap_hsmmc_set_ios(struct udevice *dev)
1193 {
1194 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1195 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1196 struct mmc *mmc = upriv->mmc;
1197 #endif
1198
1199 if (priv->bus_width != mmc->bus_width)
1200 omap_hsmmc_set_bus_width(mmc);
1201
1202 if (priv->clock != mmc->clock)
1203 omap_hsmmc_set_clock(mmc);
1204
1205 #if CONFIG_IS_ENABLED(DM_MMC)
1206 if (priv->mode != mmc->selected_mode)
1207 omap_hsmmc_set_timing(mmc);
1208 #endif
1209 return 0;
1210 }
1211
1212 #ifdef OMAP_HSMMC_USE_GPIO
1213 #if CONFIG_IS_ENABLED(DM_MMC)
1214 static int omap_hsmmc_getcd(struct udevice *dev)
1215 {
1216 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1217 int value;
1218
1219 value = dm_gpio_get_value(&priv->cd_gpio);
1220 /* if no CD return as 1 */
1221 if (value < 0)
1222 return 1;
1223
1224 if (priv->cd_inverted)
1225 return !value;
1226 return value;
1227 }
1228
1229 static int omap_hsmmc_getwp(struct udevice *dev)
1230 {
1231 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1232 int value;
1233
1234 value = dm_gpio_get_value(&priv->wp_gpio);
1235 /* if no WP return as 0 */
1236 if (value < 0)
1237 return 0;
1238 return value;
1239 }
1240 #else
1241 static int omap_hsmmc_getcd(struct mmc *mmc)
1242 {
1243 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1244 int cd_gpio;
1245
1246 /* if no CD return as 1 */
1247 cd_gpio = priv->cd_gpio;
1248 if (cd_gpio < 0)
1249 return 1;
1250
1251 /* NOTE: assumes card detect signal is active-low */
1252 return !gpio_get_value(cd_gpio);
1253 }
1254
1255 static int omap_hsmmc_getwp(struct mmc *mmc)
1256 {
1257 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1258 int wp_gpio;
1259
1260 /* if no WP return as 0 */
1261 wp_gpio = priv->wp_gpio;
1262 if (wp_gpio < 0)
1263 return 0;
1264
1265 /* NOTE: assumes write protect signal is active-high */
1266 return gpio_get_value(wp_gpio);
1267 }
1268 #endif
1269 #endif
1270
1271 #if CONFIG_IS_ENABLED(DM_MMC)
1272 static const struct dm_mmc_ops omap_hsmmc_ops = {
1273 .send_cmd = omap_hsmmc_send_cmd,
1274 .set_ios = omap_hsmmc_set_ios,
1275 #ifdef OMAP_HSMMC_USE_GPIO
1276 .get_cd = omap_hsmmc_getcd,
1277 .get_wp = omap_hsmmc_getwp,
1278 #endif
1279 #ifdef MMC_SUPPORTS_TUNING
1280 .execute_tuning = omap_hsmmc_execute_tuning,
1281 #endif
1282 };
1283 #else
1284 static const struct mmc_ops omap_hsmmc_ops = {
1285 .send_cmd = omap_hsmmc_send_cmd,
1286 .set_ios = omap_hsmmc_set_ios,
1287 .init = omap_hsmmc_init_setup,
1288 #ifdef OMAP_HSMMC_USE_GPIO
1289 .getcd = omap_hsmmc_getcd,
1290 .getwp = omap_hsmmc_getwp,
1291 #endif
1292 };
1293 #endif
1294
1295 #if !CONFIG_IS_ENABLED(DM_MMC)
1296 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1297 int wp_gpio)
1298 {
1299 struct mmc *mmc;
1300 struct omap_hsmmc_data *priv;
1301 struct mmc_config *cfg;
1302 uint host_caps_val;
1303
1304 priv = malloc(sizeof(*priv));
1305 if (priv == NULL)
1306 return -1;
1307
1308 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1309
1310 switch (dev_index) {
1311 case 0:
1312 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1313 break;
1314 #ifdef OMAP_HSMMC2_BASE
1315 case 1:
1316 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1317 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1318 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1319 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1320 defined(CONFIG_HSMMC2_8BIT)
1321 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1322 host_caps_val |= MMC_MODE_8BIT;
1323 #endif
1324 break;
1325 #endif
1326 #ifdef OMAP_HSMMC3_BASE
1327 case 2:
1328 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1329 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1330 /* Enable 8-bit interface for eMMC on DRA7XX */
1331 host_caps_val |= MMC_MODE_8BIT;
1332 #endif
1333 break;
1334 #endif
1335 default:
1336 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1337 return 1;
1338 }
1339 #ifdef OMAP_HSMMC_USE_GPIO
1340 /* on error gpio values are set to -1, which is what we want */
1341 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1342 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1343 #endif
1344
1345 cfg = &priv->cfg;
1346
1347 cfg->name = "OMAP SD/MMC";
1348 cfg->ops = &omap_hsmmc_ops;
1349
1350 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1351 cfg->host_caps = host_caps_val & ~host_caps_mask;
1352
1353 cfg->f_min = 400000;
1354
1355 if (f_max != 0)
1356 cfg->f_max = f_max;
1357 else {
1358 if (cfg->host_caps & MMC_MODE_HS) {
1359 if (cfg->host_caps & MMC_MODE_HS_52MHz)
1360 cfg->f_max = 52000000;
1361 else
1362 cfg->f_max = 26000000;
1363 } else
1364 cfg->f_max = 20000000;
1365 }
1366
1367 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1368
1369 #if defined(CONFIG_OMAP34XX)
1370 /*
1371 * Silicon revs 2.1 and older do not support multiblock transfers.
1372 */
1373 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1374 cfg->b_max = 1;
1375 #endif
1376
1377 mmc = mmc_create(cfg, priv);
1378 if (mmc == NULL)
1379 return -1;
1380
1381 return 0;
1382 }
1383 #else
1384
1385 #ifdef CONFIG_IODELAY_RECALIBRATION
1386 static struct pad_conf_entry *
1387 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1388 {
1389 int index = 0;
1390 struct pad_conf_entry *padconf;
1391
1392 padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1393 if (!padconf) {
1394 debug("failed to allocate memory\n");
1395 return 0;
1396 }
1397
1398 while (index < count) {
1399 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1400 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1401 index++;
1402 }
1403
1404 return padconf;
1405 }
1406
1407 static struct iodelay_cfg_entry *
1408 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1409 {
1410 int index = 0;
1411 struct iodelay_cfg_entry *iodelay;
1412
1413 iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1414 if (!iodelay) {
1415 debug("failed to allocate memory\n");
1416 return 0;
1417 }
1418
1419 while (index < count) {
1420 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1421 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1422 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1423 index++;
1424 }
1425
1426 return iodelay;
1427 }
1428
1429 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32 phandle,
1430 const char *name, int *len)
1431 {
1432 const void *fdt = gd->fdt_blob;
1433 int offset;
1434 const fdt32_t *pinctrl;
1435
1436 offset = fdt_node_offset_by_phandle(fdt, phandle);
1437 if (offset < 0) {
1438 debug("failed to get pinctrl node %s.\n",
1439 fdt_strerror(offset));
1440 return 0;
1441 }
1442
1443 pinctrl = fdt_getprop(fdt, offset, name, len);
1444 if (!pinctrl) {
1445 debug("failed to get property %s\n", name);
1446 return 0;
1447 }
1448
1449 return pinctrl;
1450 }
1451
1452 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1453 char *prop_name)
1454 {
1455 const void *fdt = gd->fdt_blob;
1456 const __be32 *phandle;
1457 int node = dev_of_offset(mmc->dev);
1458
1459 phandle = fdt_getprop(fdt, node, prop_name, NULL);
1460 if (!phandle) {
1461 debug("failed to get property %s\n", prop_name);
1462 return 0;
1463 }
1464
1465 return fdt32_to_cpu(*phandle);
1466 }
1467
1468 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1469 char *prop_name)
1470 {
1471 const void *fdt = gd->fdt_blob;
1472 const __be32 *phandle;
1473 int len;
1474 int count;
1475 int node = dev_of_offset(mmc->dev);
1476
1477 phandle = fdt_getprop(fdt, node, prop_name, &len);
1478 if (!phandle) {
1479 debug("failed to get property %s\n", prop_name);
1480 return 0;
1481 }
1482
1483 /* No manual mode iodelay values if count < 2 */
1484 count = len / sizeof(*phandle);
1485 if (count < 2)
1486 return 0;
1487
1488 return fdt32_to_cpu(*(phandle + 1));
1489 }
1490
1491 static struct pad_conf_entry *
1492 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1493 {
1494 int len;
1495 int count;
1496 struct pad_conf_entry *padconf;
1497 u32 phandle;
1498 const fdt32_t *pinctrl;
1499
1500 phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1501 if (!phandle)
1502 return ERR_PTR(-EINVAL);
1503
1504 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1505 &len);
1506 if (!pinctrl)
1507 return ERR_PTR(-EINVAL);
1508
1509 count = (len / sizeof(*pinctrl)) / 2;
1510 padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1511 if (!padconf)
1512 return ERR_PTR(-EINVAL);
1513
1514 *npads = count;
1515
1516 return padconf;
1517 }
1518
1519 static struct iodelay_cfg_entry *
1520 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1521 {
1522 int len;
1523 int count;
1524 struct iodelay_cfg_entry *iodelay;
1525 u32 phandle;
1526 const fdt32_t *pinctrl;
1527
1528 phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1529 /* Not all modes have manual mode iodelay values. So its not fatal */
1530 if (!phandle)
1531 return 0;
1532
1533 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1534 &len);
1535 if (!pinctrl)
1536 return ERR_PTR(-EINVAL);
1537
1538 count = (len / sizeof(*pinctrl)) / 3;
1539 iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1540 if (!iodelay)
1541 return ERR_PTR(-EINVAL);
1542
1543 *niodelay = count;
1544
1545 return iodelay;
1546 }
1547
1548 static struct omap_hsmmc_pinctrl_state *
1549 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1550 {
1551 int index;
1552 int npads = 0;
1553 int niodelays = 0;
1554 const void *fdt = gd->fdt_blob;
1555 int node = dev_of_offset(mmc->dev);
1556 char prop_name[11];
1557 struct omap_hsmmc_pinctrl_state *pinctrl_state;
1558
1559 pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1560 malloc(sizeof(*pinctrl_state));
1561 if (!pinctrl_state) {
1562 debug("failed to allocate memory\n");
1563 return 0;
1564 }
1565
1566 index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1567 if (index < 0) {
1568 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1569 goto err_pinctrl_state;
1570 }
1571
1572 sprintf(prop_name, "pinctrl-%d", index);
1573
1574 pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1575 &npads);
1576 if (IS_ERR(pinctrl_state->padconf))
1577 goto err_pinctrl_state;
1578 pinctrl_state->npads = npads;
1579
1580 pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1581 &niodelays);
1582 if (IS_ERR(pinctrl_state->iodelay))
1583 goto err_padconf;
1584 pinctrl_state->niodelays = niodelays;
1585
1586 return pinctrl_state;
1587
1588 err_padconf:
1589 kfree(pinctrl_state->padconf);
1590
1591 err_pinctrl_state:
1592 kfree(pinctrl_state);
1593 return 0;
1594 }
1595
1596 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional) \
1597 do { \
1598 struct omap_hsmmc_pinctrl_state *s = NULL; \
1599 char str[20]; \
1600 if (!(cfg->host_caps & capmask)) \
1601 break; \
1602 \
1603 if (priv->hw_rev) { \
1604 sprintf(str, "%s-%s", #mode, priv->hw_rev); \
1605 s = omap_hsmmc_get_pinctrl_by_mode(mmc, str); \
1606 } \
1607 \
1608 if (!s) \
1609 s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1610 \
1611 if (!s && !optional) { \
1612 debug("%s: no pinctrl for %s\n", \
1613 mmc->dev->name, #mode); \
1614 cfg->host_caps &= ~(capmask); \
1615 } else { \
1616 priv->mode##_pinctrl_state = s; \
1617 } \
1618 } while (0)
1619
1620 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1621 {
1622 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1623 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1624 struct omap_hsmmc_pinctrl_state *default_pinctrl;
1625
1626 if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1627 return 0;
1628
1629 default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1630 if (!default_pinctrl) {
1631 printf("no pinctrl state for default mode\n");
1632 return -EINVAL;
1633 }
1634
1635 priv->default_pinctrl_state = default_pinctrl;
1636
1637 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
1638 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
1639 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
1640 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
1641 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
1642
1643 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
1644 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
1645 OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
1646
1647 return 0;
1648 }
1649 #endif
1650
1651 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1652 #ifdef CONFIG_OMAP54XX
1653 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
1654 {
1655 return NULL;
1656 }
1657 #endif
1658
1659 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1660 {
1661 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1662 struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1663
1664 struct mmc_config *cfg = &plat->cfg;
1665 #ifdef CONFIG_OMAP54XX
1666 const struct mmc_platform_fixups *fixups;
1667 #endif
1668 const void *fdt = gd->fdt_blob;
1669 int node = dev_of_offset(dev);
1670 int ret;
1671
1672 plat->base_addr = map_physmem(devfdt_get_addr(dev),
1673 sizeof(struct hsmmc *),
1674 MAP_NOCACHE);
1675
1676 ret = mmc_of_parse(dev, cfg);
1677 if (ret < 0)
1678 return ret;
1679
1680 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1681 cfg->f_min = 400000;
1682 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1683 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1684 if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1685 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1686 if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1687 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1688 if (of_data)
1689 plat->controller_flags |= of_data->controller_flags;
1690
1691 #ifdef CONFIG_OMAP54XX
1692 fixups = platform_fixups_mmc(devfdt_get_addr(dev));
1693 if (fixups) {
1694 plat->hw_rev = fixups->hw_rev;
1695 cfg->host_caps &= ~fixups->unsupported_caps;
1696 cfg->f_max = fixups->max_freq;
1697 }
1698 #endif
1699
1700 #ifdef OMAP_HSMMC_USE_GPIO
1701 plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
1702 #endif
1703
1704 return 0;
1705 }
1706 #endif
1707
1708 #ifdef CONFIG_BLK
1709
1710 static int omap_hsmmc_bind(struct udevice *dev)
1711 {
1712 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1713
1714 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1715 }
1716 #endif
1717 static int omap_hsmmc_probe(struct udevice *dev)
1718 {
1719 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1720 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1721 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1722 struct mmc_config *cfg = &plat->cfg;
1723 struct mmc *mmc;
1724 #ifdef CONFIG_IODELAY_RECALIBRATION
1725 int ret;
1726 #endif
1727
1728 cfg->name = "OMAP SD/MMC";
1729 priv->base_addr = plat->base_addr;
1730 priv->controller_flags = plat->controller_flags;
1731 priv->hw_rev = plat->hw_rev;
1732 #ifdef OMAP_HSMMC_USE_GPIO
1733 priv->cd_inverted = plat->cd_inverted;
1734 #endif
1735
1736 #ifdef CONFIG_BLK
1737 mmc = &plat->mmc;
1738 #else
1739 mmc = mmc_create(cfg, priv);
1740 if (mmc == NULL)
1741 return -1;
1742 #endif
1743
1744 #if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
1745 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1746 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1747 #endif
1748
1749 mmc->dev = dev;
1750 upriv->mmc = mmc;
1751
1752 #ifdef CONFIG_IODELAY_RECALIBRATION
1753 ret = omap_hsmmc_get_pinctrl_state(mmc);
1754 /*
1755 * disable high speed modes for the platforms that require IO delay
1756 * and for which we don't have this information
1757 */
1758 if ((ret < 0) &&
1759 (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
1760 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
1761 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
1762 UHS_CAPS);
1763 }
1764 #endif
1765
1766 return omap_hsmmc_init_setup(mmc);
1767 }
1768
1769 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1770
1771 static const struct omap_mmc_of_data dra7_mmc_of_data = {
1772 .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
1773 };
1774
1775 static const struct udevice_id omap_hsmmc_ids[] = {
1776 { .compatible = "ti,omap3-hsmmc" },
1777 { .compatible = "ti,omap4-hsmmc" },
1778 { .compatible = "ti,am33xx-hsmmc" },
1779 { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
1780 { }
1781 };
1782 #endif
1783
1784 U_BOOT_DRIVER(omap_hsmmc) = {
1785 .name = "omap_hsmmc",
1786 .id = UCLASS_MMC,
1787 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1788 .of_match = omap_hsmmc_ids,
1789 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
1790 .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
1791 #endif
1792 #ifdef CONFIG_BLK
1793 .bind = omap_hsmmc_bind,
1794 #endif
1795 .ops = &omap_hsmmc_ops,
1796 .probe = omap_hsmmc_probe,
1797 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
1798 .flags = DM_FLAG_PRE_RELOC,
1799 };
1800 #endif
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