3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/arch/mmc_host_def.h>
34 #include <asm/arch/sys_proto.h>
36 /* If we fail after 1 second wait, something is really bad */
37 #define MAX_RETRY_MS 1000
39 static int mmc_read_data(hsmmc_t
*mmc_base
, char *buf
, unsigned int size
);
40 static int mmc_write_data(hsmmc_t
*mmc_base
, const char *buf
, unsigned int siz
);
41 static struct mmc hsmmc_dev
[2];
43 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
44 static void omap4_vmmc_pbias_config(struct mmc
*mmc
)
47 struct omap4_sys_ctrl_regs
*const ctrl
=
48 (struct omap4_sys_ctrl_regs
*)SYSCTRL_GENERAL_CORE_BASE
;
51 value
= readl(&ctrl
->control_pbiaslite
);
52 value
&= ~(MMC1_PBIASLITE_PWRDNZ
| MMC1_PWRDNZ
);
53 writel(value
, &ctrl
->control_pbiaslite
);
55 twl6030_power_mmc_init();
56 value
= readl(&ctrl
->control_pbiaslite
);
57 value
|= MMC1_PBIASLITE_VMODE
| MMC1_PBIASLITE_PWRDNZ
| MMC1_PWRDNZ
;
58 writel(value
, &ctrl
->control_pbiaslite
);
62 unsigned char mmc_board_init(struct mmc
*mmc
)
64 #if defined(CONFIG_TWL4030_POWER)
65 twl4030_power_mmc_init();
68 #if defined(CONFIG_OMAP34XX)
69 t2_t
*t2_base
= (t2_t
*)T2_BASE
;
70 struct prcm
*prcm_base
= (struct prcm
*)PRCM_BASE
;
72 writel(readl(&t2_base
->pbias_lite
) | PBIASLITEPWRDNZ1
|
73 PBIASSPEEDCTRL0
| PBIASLITEPWRDNZ0
,
74 &t2_base
->pbias_lite
);
76 writel(readl(&t2_base
->devconf0
) | MMCSDIO1ADPCLKISEL
,
79 writel(readl(&t2_base
->devconf1
) | MMCSDIO2ADPCLKISEL
,
82 writel(readl(&prcm_base
->fclken1_core
) |
83 EN_MMC1
| EN_MMC2
| EN_MMC3
,
84 &prcm_base
->fclken1_core
);
86 writel(readl(&prcm_base
->iclken1_core
) |
87 EN_MMC1
| EN_MMC2
| EN_MMC3
,
88 &prcm_base
->iclken1_core
);
91 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
92 /* PBIAS config needed for MMC1 only */
93 if (mmc
->block_dev
.dev
== 0)
94 omap4_vmmc_pbias_config(mmc
);
100 void mmc_init_stream(hsmmc_t
*mmc_base
)
104 writel(readl(&mmc_base
->con
) | INIT_INITSTREAM
, &mmc_base
->con
);
106 writel(MMC_CMD0
, &mmc_base
->cmd
);
107 start
= get_timer(0);
108 while (!(readl(&mmc_base
->stat
) & CC_MASK
)) {
109 if (get_timer(0) - start
> MAX_RETRY_MS
) {
110 printf("%s: timedout waiting for cc!\n", __func__
);
114 writel(CC_MASK
, &mmc_base
->stat
)
116 writel(MMC_CMD0
, &mmc_base
->cmd
)
118 start
= get_timer(0);
119 while (!(readl(&mmc_base
->stat
) & CC_MASK
)) {
120 if (get_timer(0) - start
> MAX_RETRY_MS
) {
121 printf("%s: timedout waiting for cc2!\n", __func__
);
125 writel(readl(&mmc_base
->con
) & ~INIT_INITSTREAM
, &mmc_base
->con
);
129 static int mmc_init_setup(struct mmc
*mmc
)
131 hsmmc_t
*mmc_base
= (hsmmc_t
*)mmc
->priv
;
132 unsigned int reg_val
;
138 writel(readl(&mmc_base
->sysconfig
) | MMC_SOFTRESET
,
139 &mmc_base
->sysconfig
);
140 start
= get_timer(0);
141 while ((readl(&mmc_base
->sysstatus
) & RESETDONE
) == 0) {
142 if (get_timer(0) - start
> MAX_RETRY_MS
) {
143 printf("%s: timedout waiting for cc2!\n", __func__
);
147 writel(readl(&mmc_base
->sysctl
) | SOFTRESETALL
, &mmc_base
->sysctl
);
148 start
= get_timer(0);
149 while ((readl(&mmc_base
->sysctl
) & SOFTRESETALL
) != 0x0) {
150 if (get_timer(0) - start
> MAX_RETRY_MS
) {
151 printf("%s: timedout waiting for softresetall!\n",
156 writel(DTW_1_BITMODE
| SDBP_PWROFF
| SDVS_3V0
, &mmc_base
->hctl
);
157 writel(readl(&mmc_base
->capa
) | VS30_3V0SUP
| VS18_1V8SUP
,
160 reg_val
= readl(&mmc_base
->con
) & RESERVED_MASK
;
162 writel(CTPL_MMC_SD
| reg_val
| WPP_ACTIVEHIGH
| CDP_ACTIVEHIGH
|
163 MIT_CTO
| DW8_1_4BITMODE
| MODE_FUNC
| STR_BLOCK
|
164 HR_NOHOSTRESP
| INIT_NOINIT
| NOOPENDRAIN
, &mmc_base
->con
);
167 mmc_reg_out(&mmc_base
->sysctl
, (ICE_MASK
| DTO_MASK
| CEN_MASK
),
168 (ICE_STOP
| DTO_15THDTO
| CEN_DISABLE
));
169 mmc_reg_out(&mmc_base
->sysctl
, ICE_MASK
| CLKD_MASK
,
170 (dsor
<< CLKD_OFFSET
) | ICE_OSCILLATE
);
171 start
= get_timer(0);
172 while ((readl(&mmc_base
->sysctl
) & ICS_MASK
) == ICS_NOTREADY
) {
173 if (get_timer(0) - start
> MAX_RETRY_MS
) {
174 printf("%s: timedout waiting for ics!\n", __func__
);
178 writel(readl(&mmc_base
->sysctl
) | CEN_ENABLE
, &mmc_base
->sysctl
);
180 writel(readl(&mmc_base
->hctl
) | SDBP_PWRON
, &mmc_base
->hctl
);
182 writel(IE_BADA
| IE_CERR
| IE_DEB
| IE_DCRC
| IE_DTO
| IE_CIE
|
183 IE_CEB
| IE_CCRC
| IE_CTO
| IE_BRR
| IE_BWR
| IE_TC
| IE_CC
,
186 mmc_init_stream(mmc_base
);
192 static int mmc_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*cmd
,
193 struct mmc_data
*data
)
195 hsmmc_t
*mmc_base
= (hsmmc_t
*)mmc
->priv
;
196 unsigned int flags
, mmc_stat
;
199 start
= get_timer(0);
200 while ((readl(&mmc_base
->pstate
) & DATI_MASK
) == DATI_CMDDIS
) {
201 if (get_timer(0) - start
> MAX_RETRY_MS
) {
202 printf("%s: timedout waiting for cmddis!\n", __func__
);
206 writel(0xFFFFFFFF, &mmc_base
->stat
);
207 start
= get_timer(0);
208 while (readl(&mmc_base
->stat
)) {
209 if (get_timer(0) - start
> MAX_RETRY_MS
) {
210 printf("%s: timedout waiting for stat!\n", __func__
);
216 * CMDIDX[13:8] : Command index
217 * DATAPRNT[5] : Data Present Select
218 * ENCMDIDX[4] : Command Index Check Enable
219 * ENCMDCRC[3] : Command CRC Check Enable
224 * 11 = Length 48 Check busy after response
226 /* Delay added before checking the status of frq change
227 * retry not supported by mmc.c(core file)
229 if (cmd
->cmdidx
== SD_CMD_APP_SEND_SCR
)
230 udelay(50000); /* wait 50 ms */
232 if (!(cmd
->resp_type
& MMC_RSP_PRESENT
))
234 else if (cmd
->resp_type
& MMC_RSP_136
)
235 flags
= RSP_TYPE_LGHT136
| CICE_NOCHECK
;
236 else if (cmd
->resp_type
& MMC_RSP_BUSY
)
237 flags
= RSP_TYPE_LGHT48B
;
239 flags
= RSP_TYPE_LGHT48
;
241 /* enable default flags */
242 flags
= flags
| (CMD_TYPE_NORMAL
| CICE_NOCHECK
| CCCE_NOCHECK
|
243 MSBS_SGLEBLK
| ACEN_DISABLE
| BCE_DISABLE
| DE_DISABLE
);
245 if (cmd
->resp_type
& MMC_RSP_CRC
)
247 if (cmd
->resp_type
& MMC_RSP_OPCODE
)
251 if ((cmd
->cmdidx
== MMC_CMD_READ_MULTIPLE_BLOCK
) ||
252 (cmd
->cmdidx
== MMC_CMD_WRITE_MULTIPLE_BLOCK
)) {
253 flags
|= (MSBS_MULTIBLK
| BCE_ENABLE
);
254 data
->blocksize
= 512;
255 writel(data
->blocksize
| (data
->blocks
<< 16),
258 writel(data
->blocksize
| NBLK_STPCNT
, &mmc_base
->blk
);
260 if (data
->flags
& MMC_DATA_READ
)
261 flags
|= (DP_DATA
| DDIR_READ
);
263 flags
|= (DP_DATA
| DDIR_WRITE
);
266 writel(cmd
->cmdarg
, &mmc_base
->arg
);
267 writel((cmd
->cmdidx
<< 24) | flags
, &mmc_base
->cmd
);
269 start
= get_timer(0);
271 mmc_stat
= readl(&mmc_base
->stat
);
272 if (get_timer(0) - start
> MAX_RETRY_MS
) {
273 printf("%s : timeout: No status update\n", __func__
);
278 if ((mmc_stat
& IE_CTO
) != 0)
280 else if ((mmc_stat
& ERRI_MASK
) != 0)
283 if (mmc_stat
& CC_MASK
) {
284 writel(CC_MASK
, &mmc_base
->stat
);
285 if (cmd
->resp_type
& MMC_RSP_PRESENT
) {
286 if (cmd
->resp_type
& MMC_RSP_136
) {
287 /* response type 2 */
288 cmd
->response
[3] = readl(&mmc_base
->rsp10
);
289 cmd
->response
[2] = readl(&mmc_base
->rsp32
);
290 cmd
->response
[1] = readl(&mmc_base
->rsp54
);
291 cmd
->response
[0] = readl(&mmc_base
->rsp76
);
293 /* response types 1, 1b, 3, 4, 5, 6 */
294 cmd
->response
[0] = readl(&mmc_base
->rsp10
);
298 if (data
&& (data
->flags
& MMC_DATA_READ
)) {
299 mmc_read_data(mmc_base
, data
->dest
,
300 data
->blocksize
* data
->blocks
);
301 } else if (data
&& (data
->flags
& MMC_DATA_WRITE
)) {
302 mmc_write_data(mmc_base
, data
->src
,
303 data
->blocksize
* data
->blocks
);
308 static int mmc_read_data(hsmmc_t
*mmc_base
, char *buf
, unsigned int size
)
310 unsigned int *output_buf
= (unsigned int *)buf
;
311 unsigned int mmc_stat
;
317 count
= (size
> MMCSD_SECTOR_SIZE
) ? MMCSD_SECTOR_SIZE
: size
;
321 ulong start
= get_timer(0);
323 mmc_stat
= readl(&mmc_base
->stat
);
324 if (get_timer(0) - start
> MAX_RETRY_MS
) {
325 printf("%s: timedout waiting for status!\n",
329 } while (mmc_stat
== 0);
331 if ((mmc_stat
& ERRI_MASK
) != 0)
334 if (mmc_stat
& BRR_MASK
) {
337 writel(readl(&mmc_base
->stat
) | BRR_MASK
,
339 for (k
= 0; k
< count
; k
++) {
340 *output_buf
= readl(&mmc_base
->data
);
346 if (mmc_stat
& BWR_MASK
)
347 writel(readl(&mmc_base
->stat
) | BWR_MASK
,
350 if (mmc_stat
& TC_MASK
) {
351 writel(readl(&mmc_base
->stat
) | TC_MASK
,
359 static int mmc_write_data(hsmmc_t
*mmc_base
, const char *buf
, unsigned int size
)
361 unsigned int *input_buf
= (unsigned int *)buf
;
362 unsigned int mmc_stat
;
368 count
= (size
> MMCSD_SECTOR_SIZE
) ? MMCSD_SECTOR_SIZE
: size
;
372 ulong start
= get_timer(0);
374 mmc_stat
= readl(&mmc_base
->stat
);
375 if (get_timer(0) - start
> MAX_RETRY_MS
) {
376 printf("%s: timedout waiting for status!\n",
380 } while (mmc_stat
== 0);
382 if ((mmc_stat
& ERRI_MASK
) != 0)
385 if (mmc_stat
& BWR_MASK
) {
388 writel(readl(&mmc_base
->stat
) | BWR_MASK
,
390 for (k
= 0; k
< count
; k
++) {
391 writel(*input_buf
, &mmc_base
->data
);
397 if (mmc_stat
& BRR_MASK
)
398 writel(readl(&mmc_base
->stat
) | BRR_MASK
,
401 if (mmc_stat
& TC_MASK
) {
402 writel(readl(&mmc_base
->stat
) | TC_MASK
,
410 static void mmc_set_ios(struct mmc
*mmc
)
412 hsmmc_t
*mmc_base
= (hsmmc_t
*)mmc
->priv
;
413 unsigned int dsor
= 0;
416 /* configue bus width */
417 switch (mmc
->bus_width
) {
419 writel(readl(&mmc_base
->con
) | DTW_8_BITMODE
,
424 writel(readl(&mmc_base
->con
) & ~DTW_8_BITMODE
,
426 writel(readl(&mmc_base
->hctl
) | DTW_4_BITMODE
,
432 writel(readl(&mmc_base
->con
) & ~DTW_8_BITMODE
,
434 writel(readl(&mmc_base
->hctl
) & ~DTW_4_BITMODE
,
439 /* configure clock with 96Mhz system clock.
441 if (mmc
->clock
!= 0) {
442 dsor
= (MMC_CLOCK_REFERENCE
* 1000000 / mmc
->clock
);
443 if ((MMC_CLOCK_REFERENCE
* 1000000) / dsor
> mmc
->clock
)
447 mmc_reg_out(&mmc_base
->sysctl
, (ICE_MASK
| DTO_MASK
| CEN_MASK
),
448 (ICE_STOP
| DTO_15THDTO
| CEN_DISABLE
));
450 mmc_reg_out(&mmc_base
->sysctl
, ICE_MASK
| CLKD_MASK
,
451 (dsor
<< CLKD_OFFSET
) | ICE_OSCILLATE
);
453 start
= get_timer(0);
454 while ((readl(&mmc_base
->sysctl
) & ICS_MASK
) == ICS_NOTREADY
) {
455 if (get_timer(0) - start
> MAX_RETRY_MS
) {
456 printf("%s: timedout waiting for ics!\n", __func__
);
460 writel(readl(&mmc_base
->sysctl
) | CEN_ENABLE
, &mmc_base
->sysctl
);
463 int omap_mmc_init(int dev_index
)
467 mmc
= &hsmmc_dev
[dev_index
];
469 sprintf(mmc
->name
, "OMAP SD/MMC");
470 mmc
->send_cmd
= mmc_send_cmd
;
471 mmc
->set_ios
= mmc_set_ios
;
472 mmc
->init
= mmc_init_setup
;
476 mmc
->priv
= (hsmmc_t
*)OMAP_HSMMC1_BASE
;
478 #ifdef OMAP_HSMMC2_BASE
480 mmc
->priv
= (hsmmc_t
*)OMAP_HSMMC2_BASE
;
483 #ifdef OMAP_HSMMC3_BASE
485 mmc
->priv
= (hsmmc_t
*)OMAP_HSMMC3_BASE
;
489 mmc
->priv
= (hsmmc_t
*)OMAP_HSMMC1_BASE
;
492 mmc
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
;
493 mmc
->host_caps
= MMC_MODE_4BIT
| MMC_MODE_HS_52MHz
| MMC_MODE_HS
|
497 mmc
->f_max
= 52000000;
501 #if defined(CONFIG_OMAP34XX)
503 * Silicon revs 2.1 and older do not support multiblock transfers.
505 if ((get_cpu_family() == CPU_OMAP34XX
) && (get_cpu_rev() <= CPU_3XX_ES21
))