3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm/arch/mmc_host_def.h>
33 #include <asm/arch/sys_proto.h>
35 /* If we fail after 1 second wait, something is really bad */
36 #define MAX_RETRY_MS 1000
38 static int mmc_read_data(hsmmc_t
*mmc_base
, char *buf
, unsigned int size
);
39 static int mmc_write_data(hsmmc_t
*mmc_base
, const char *buf
, unsigned int siz
);
40 static struct mmc hsmmc_dev
[2];
41 unsigned char mmc_board_init(hsmmc_t
*mmc_base
)
43 #if defined(CONFIG_TWL4030_POWER)
44 twl4030_power_mmc_init();
47 #if defined(CONFIG_OMAP34XX)
48 t2_t
*t2_base
= (t2_t
*)T2_BASE
;
49 struct prcm
*prcm_base
= (struct prcm
*)PRCM_BASE
;
51 writel(readl(&t2_base
->pbias_lite
) | PBIASLITEPWRDNZ1
|
52 PBIASSPEEDCTRL0
| PBIASLITEPWRDNZ0
,
53 &t2_base
->pbias_lite
);
55 writel(readl(&t2_base
->devconf0
) | MMCSDIO1ADPCLKISEL
,
58 writel(readl(&t2_base
->devconf1
) | MMCSDIO2ADPCLKISEL
,
61 writel(readl(&prcm_base
->fclken1_core
) |
62 EN_MMC1
| EN_MMC2
| EN_MMC3
,
63 &prcm_base
->fclken1_core
);
65 writel(readl(&prcm_base
->iclken1_core
) |
66 EN_MMC1
| EN_MMC2
| EN_MMC3
,
67 &prcm_base
->iclken1_core
);
70 /* TODO add appropriate OMAP4 init - none currently necessary */
75 void mmc_init_stream(hsmmc_t
*mmc_base
)
79 writel(readl(&mmc_base
->con
) | INIT_INITSTREAM
, &mmc_base
->con
);
81 writel(MMC_CMD0
, &mmc_base
->cmd
);
83 while (!(readl(&mmc_base
->stat
) & CC_MASK
)) {
84 if (get_timer(0) - start
> MAX_RETRY_MS
) {
85 printf("%s: timedout waiting for cc!\n", __func__
);
89 writel(CC_MASK
, &mmc_base
->stat
)
91 writel(MMC_CMD0
, &mmc_base
->cmd
)
94 while (!(readl(&mmc_base
->stat
) & CC_MASK
)) {
95 if (get_timer(0) - start
> MAX_RETRY_MS
) {
96 printf("%s: timedout waiting for cc2!\n", __func__
);
100 writel(readl(&mmc_base
->con
) & ~INIT_INITSTREAM
, &mmc_base
->con
);
104 static int mmc_init_setup(struct mmc
*mmc
)
106 hsmmc_t
*mmc_base
= (hsmmc_t
*)mmc
->priv
;
107 unsigned int reg_val
;
111 mmc_board_init(mmc_base
);
113 writel(readl(&mmc_base
->sysconfig
) | MMC_SOFTRESET
,
114 &mmc_base
->sysconfig
);
115 start
= get_timer(0);
116 while ((readl(&mmc_base
->sysstatus
) & RESETDONE
) == 0) {
117 if (get_timer(0) - start
> MAX_RETRY_MS
) {
118 printf("%s: timedout waiting for cc2!\n", __func__
);
122 writel(readl(&mmc_base
->sysctl
) | SOFTRESETALL
, &mmc_base
->sysctl
);
123 start
= get_timer(0);
124 while ((readl(&mmc_base
->sysctl
) & SOFTRESETALL
) != 0x0) {
125 if (get_timer(0) - start
> MAX_RETRY_MS
) {
126 printf("%s: timedout waiting for softresetall!\n",
131 writel(DTW_1_BITMODE
| SDBP_PWROFF
| SDVS_3V0
, &mmc_base
->hctl
);
132 writel(readl(&mmc_base
->capa
) | VS30_3V0SUP
| VS18_1V8SUP
,
135 reg_val
= readl(&mmc_base
->con
) & RESERVED_MASK
;
137 writel(CTPL_MMC_SD
| reg_val
| WPP_ACTIVEHIGH
| CDP_ACTIVEHIGH
|
138 MIT_CTO
| DW8_1_4BITMODE
| MODE_FUNC
| STR_BLOCK
|
139 HR_NOHOSTRESP
| INIT_NOINIT
| NOOPENDRAIN
, &mmc_base
->con
);
142 mmc_reg_out(&mmc_base
->sysctl
, (ICE_MASK
| DTO_MASK
| CEN_MASK
),
143 (ICE_STOP
| DTO_15THDTO
| CEN_DISABLE
));
144 mmc_reg_out(&mmc_base
->sysctl
, ICE_MASK
| CLKD_MASK
,
145 (dsor
<< CLKD_OFFSET
) | ICE_OSCILLATE
);
146 start
= get_timer(0);
147 while ((readl(&mmc_base
->sysctl
) & ICS_MASK
) == ICS_NOTREADY
) {
148 if (get_timer(0) - start
> MAX_RETRY_MS
) {
149 printf("%s: timedout waiting for ics!\n", __func__
);
153 writel(readl(&mmc_base
->sysctl
) | CEN_ENABLE
, &mmc_base
->sysctl
);
155 writel(readl(&mmc_base
->hctl
) | SDBP_PWRON
, &mmc_base
->hctl
);
157 writel(IE_BADA
| IE_CERR
| IE_DEB
| IE_DCRC
| IE_DTO
| IE_CIE
|
158 IE_CEB
| IE_CCRC
| IE_CTO
| IE_BRR
| IE_BWR
| IE_TC
| IE_CC
,
161 mmc_init_stream(mmc_base
);
167 static int mmc_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*cmd
,
168 struct mmc_data
*data
)
170 hsmmc_t
*mmc_base
= (hsmmc_t
*)mmc
->priv
;
171 unsigned int flags
, mmc_stat
;
174 start
= get_timer(0);
175 while ((readl(&mmc_base
->pstate
) & DATI_MASK
) == DATI_CMDDIS
) {
176 if (get_timer(0) - start
> MAX_RETRY_MS
) {
177 printf("%s: timedout waiting for cmddis!\n", __func__
);
181 writel(0xFFFFFFFF, &mmc_base
->stat
);
182 start
= get_timer(0);
183 while (readl(&mmc_base
->stat
)) {
184 if (get_timer(0) - start
> MAX_RETRY_MS
) {
185 printf("%s: timedout waiting for stat!\n", __func__
);
191 * CMDIDX[13:8] : Command index
192 * DATAPRNT[5] : Data Present Select
193 * ENCMDIDX[4] : Command Index Check Enable
194 * ENCMDCRC[3] : Command CRC Check Enable
199 * 11 = Length 48 Check busy after response
201 /* Delay added before checking the status of frq change
202 * retry not supported by mmc.c(core file)
204 if (cmd
->cmdidx
== SD_CMD_APP_SEND_SCR
)
205 udelay(50000); /* wait 50 ms */
207 if (!(cmd
->resp_type
& MMC_RSP_PRESENT
))
209 else if (cmd
->resp_type
& MMC_RSP_136
)
210 flags
= RSP_TYPE_LGHT136
| CICE_NOCHECK
;
211 else if (cmd
->resp_type
& MMC_RSP_BUSY
)
212 flags
= RSP_TYPE_LGHT48B
;
214 flags
= RSP_TYPE_LGHT48
;
216 /* enable default flags */
217 flags
= flags
| (CMD_TYPE_NORMAL
| CICE_NOCHECK
| CCCE_NOCHECK
|
218 MSBS_SGLEBLK
| ACEN_DISABLE
| BCE_DISABLE
| DE_DISABLE
);
220 if (cmd
->resp_type
& MMC_RSP_CRC
)
222 if (cmd
->resp_type
& MMC_RSP_OPCODE
)
226 if ((cmd
->cmdidx
== MMC_CMD_READ_MULTIPLE_BLOCK
) ||
227 (cmd
->cmdidx
== MMC_CMD_WRITE_MULTIPLE_BLOCK
)) {
228 flags
|= (MSBS_MULTIBLK
| BCE_ENABLE
);
229 data
->blocksize
= 512;
230 writel(data
->blocksize
| (data
->blocks
<< 16),
233 writel(data
->blocksize
| NBLK_STPCNT
, &mmc_base
->blk
);
235 if (data
->flags
& MMC_DATA_READ
)
236 flags
|= (DP_DATA
| DDIR_READ
);
238 flags
|= (DP_DATA
| DDIR_WRITE
);
241 writel(cmd
->cmdarg
, &mmc_base
->arg
);
242 writel((cmd
->cmdidx
<< 24) | flags
, &mmc_base
->cmd
);
244 start
= get_timer(0);
246 mmc_stat
= readl(&mmc_base
->stat
);
247 if (get_timer(0) - start
> MAX_RETRY_MS
) {
248 printf("%s : timeout: No status update\n", __func__
);
253 if ((mmc_stat
& IE_CTO
) != 0)
255 else if ((mmc_stat
& ERRI_MASK
) != 0)
258 if (mmc_stat
& CC_MASK
) {
259 writel(CC_MASK
, &mmc_base
->stat
);
260 if (cmd
->resp_type
& MMC_RSP_PRESENT
) {
261 if (cmd
->resp_type
& MMC_RSP_136
) {
262 /* response type 2 */
263 cmd
->response
[3] = readl(&mmc_base
->rsp10
);
264 cmd
->response
[2] = readl(&mmc_base
->rsp32
);
265 cmd
->response
[1] = readl(&mmc_base
->rsp54
);
266 cmd
->response
[0] = readl(&mmc_base
->rsp76
);
268 /* response types 1, 1b, 3, 4, 5, 6 */
269 cmd
->response
[0] = readl(&mmc_base
->rsp10
);
273 if (data
&& (data
->flags
& MMC_DATA_READ
)) {
274 mmc_read_data(mmc_base
, data
->dest
,
275 data
->blocksize
* data
->blocks
);
276 } else if (data
&& (data
->flags
& MMC_DATA_WRITE
)) {
277 mmc_write_data(mmc_base
, data
->src
,
278 data
->blocksize
* data
->blocks
);
283 static int mmc_read_data(hsmmc_t
*mmc_base
, char *buf
, unsigned int size
)
285 unsigned int *output_buf
= (unsigned int *)buf
;
286 unsigned int mmc_stat
;
292 count
= (size
> MMCSD_SECTOR_SIZE
) ? MMCSD_SECTOR_SIZE
: size
;
296 ulong start
= get_timer(0);
298 mmc_stat
= readl(&mmc_base
->stat
);
299 if (get_timer(0) - start
> MAX_RETRY_MS
) {
300 printf("%s: timedout waiting for status!\n",
304 } while (mmc_stat
== 0);
306 if ((mmc_stat
& ERRI_MASK
) != 0)
309 if (mmc_stat
& BRR_MASK
) {
312 writel(readl(&mmc_base
->stat
) | BRR_MASK
,
314 for (k
= 0; k
< count
; k
++) {
315 *output_buf
= readl(&mmc_base
->data
);
321 if (mmc_stat
& BWR_MASK
)
322 writel(readl(&mmc_base
->stat
) | BWR_MASK
,
325 if (mmc_stat
& TC_MASK
) {
326 writel(readl(&mmc_base
->stat
) | TC_MASK
,
334 static int mmc_write_data(hsmmc_t
*mmc_base
, const char *buf
, unsigned int size
)
336 unsigned int *input_buf
= (unsigned int *)buf
;
337 unsigned int mmc_stat
;
343 count
= (size
> MMCSD_SECTOR_SIZE
) ? MMCSD_SECTOR_SIZE
: size
;
347 ulong start
= get_timer(0);
349 mmc_stat
= readl(&mmc_base
->stat
);
350 if (get_timer(0) - start
> MAX_RETRY_MS
) {
351 printf("%s: timedout waiting for status!\n",
355 } while (mmc_stat
== 0);
357 if ((mmc_stat
& ERRI_MASK
) != 0)
360 if (mmc_stat
& BWR_MASK
) {
363 writel(readl(&mmc_base
->stat
) | BWR_MASK
,
365 for (k
= 0; k
< count
; k
++) {
366 writel(*input_buf
, &mmc_base
->data
);
372 if (mmc_stat
& BRR_MASK
)
373 writel(readl(&mmc_base
->stat
) | BRR_MASK
,
376 if (mmc_stat
& TC_MASK
) {
377 writel(readl(&mmc_base
->stat
) | TC_MASK
,
385 static void mmc_set_ios(struct mmc
*mmc
)
387 hsmmc_t
*mmc_base
= (hsmmc_t
*)mmc
->priv
;
388 unsigned int dsor
= 0;
391 /* configue bus width */
392 switch (mmc
->bus_width
) {
394 writel(readl(&mmc_base
->con
) | DTW_8_BITMODE
,
399 writel(readl(&mmc_base
->con
) & ~DTW_8_BITMODE
,
401 writel(readl(&mmc_base
->hctl
) | DTW_4_BITMODE
,
407 writel(readl(&mmc_base
->con
) & ~DTW_8_BITMODE
,
409 writel(readl(&mmc_base
->hctl
) & ~DTW_4_BITMODE
,
414 /* configure clock with 96Mhz system clock.
416 if (mmc
->clock
!= 0) {
417 dsor
= (MMC_CLOCK_REFERENCE
* 1000000 / mmc
->clock
);
418 if ((MMC_CLOCK_REFERENCE
* 1000000) / dsor
> mmc
->clock
)
422 mmc_reg_out(&mmc_base
->sysctl
, (ICE_MASK
| DTO_MASK
| CEN_MASK
),
423 (ICE_STOP
| DTO_15THDTO
| CEN_DISABLE
));
425 mmc_reg_out(&mmc_base
->sysctl
, ICE_MASK
| CLKD_MASK
,
426 (dsor
<< CLKD_OFFSET
) | ICE_OSCILLATE
);
428 start
= get_timer(0);
429 while ((readl(&mmc_base
->sysctl
) & ICS_MASK
) == ICS_NOTREADY
) {
430 if (get_timer(0) - start
> MAX_RETRY_MS
) {
431 printf("%s: timedout waiting for ics!\n", __func__
);
435 writel(readl(&mmc_base
->sysctl
) | CEN_ENABLE
, &mmc_base
->sysctl
);
438 int omap_mmc_init(int dev_index
)
442 mmc
= &hsmmc_dev
[dev_index
];
444 sprintf(mmc
->name
, "OMAP SD/MMC");
445 mmc
->send_cmd
= mmc_send_cmd
;
446 mmc
->set_ios
= mmc_set_ios
;
447 mmc
->init
= mmc_init_setup
;
451 mmc
->priv
= (hsmmc_t
*)OMAP_HSMMC1_BASE
;
454 mmc
->priv
= (hsmmc_t
*)OMAP_HSMMC2_BASE
;
457 mmc
->priv
= (hsmmc_t
*)OMAP_HSMMC3_BASE
;
460 mmc
->priv
= (hsmmc_t
*)OMAP_HSMMC1_BASE
;
463 mmc
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
;
464 mmc
->host_caps
= MMC_MODE_4BIT
| MMC_MODE_HS_52MHz
| MMC_MODE_HS
;
467 mmc
->f_max
= 52000000;
471 #if defined(CONFIG_OMAP34XX)
473 * Silicon revs 2.1 and older do not support multiblock transfers.
475 if ((get_cpu_family() == CPU_OMAP34XX
) && (get_cpu_rev() <= CPU_3XX_ES21
))