3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm/arch/mmc_host_def.h>
35 #include <asm/arch/sys_proto.h>
37 /* common definitions for all OMAPs */
38 #define SYSCTL_SRC (1 << 25)
39 #define SYSCTL_SRD (1 << 26)
41 /* If we fail after 1 second wait, something is really bad */
42 #define MAX_RETRY_MS 1000
44 static int mmc_read_data(struct hsmmc
*mmc_base
, char *buf
, unsigned int size
);
45 static int mmc_write_data(struct hsmmc
*mmc_base
, const char *buf
,
47 static struct mmc hsmmc_dev
[2];
49 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
50 static void omap4_vmmc_pbias_config(struct mmc
*mmc
)
53 struct omap_sys_ctrl_regs
*const ctrl
=
54 (struct omap_sys_ctrl_regs
*) SYSCTRL_GENERAL_CORE_BASE
;
57 value
= readl(&ctrl
->control_pbiaslite
);
58 value
&= ~(MMC1_PBIASLITE_PWRDNZ
| MMC1_PWRDNZ
);
59 writel(value
, &ctrl
->control_pbiaslite
);
61 twl6030_power_mmc_init();
62 value
= readl(&ctrl
->control_pbiaslite
);
63 value
|= MMC1_PBIASLITE_VMODE
| MMC1_PBIASLITE_PWRDNZ
| MMC1_PWRDNZ
;
64 writel(value
, &ctrl
->control_pbiaslite
);
68 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
69 static void omap5_pbias_config(struct mmc
*mmc
)
72 struct omap_sys_ctrl_regs
*const ctrl
=
73 (struct omap_sys_ctrl_regs
*) SYSCTRL_GENERAL_CORE_BASE
;
75 value
= readl(&ctrl
->control_pbias
);
76 value
&= ~(SDCARD_PWRDNZ
| SDCARD_BIAS_PWRDNZ
);
77 value
|= SDCARD_BIAS_HIZ_MODE
;
78 writel(value
, &ctrl
->control_pbias
);
80 twl6035_mmc1_poweron_ldo();
82 value
= readl(&ctrl
->control_pbias
);
83 value
&= ~SDCARD_BIAS_HIZ_MODE
;
84 value
|= SDCARD_PBIASLITE_VMODE
| SDCARD_PWRDNZ
| SDCARD_BIAS_PWRDNZ
;
85 writel(value
, &ctrl
->control_pbias
);
87 value
= readl(&ctrl
->control_pbias
);
88 if (value
& (1 << 23)) {
89 value
&= ~(SDCARD_PWRDNZ
| SDCARD_BIAS_PWRDNZ
);
90 value
|= SDCARD_BIAS_HIZ_MODE
;
91 writel(value
, &ctrl
->control_pbias
);
96 unsigned char mmc_board_init(struct mmc
*mmc
)
98 #if defined(CONFIG_OMAP34XX)
99 t2_t
*t2_base
= (t2_t
*)T2_BASE
;
100 struct prcm
*prcm_base
= (struct prcm
*)PRCM_BASE
;
103 pbias_lite
= readl(&t2_base
->pbias_lite
);
104 pbias_lite
&= ~(PBIASLITEPWRDNZ1
| PBIASLITEPWRDNZ0
);
105 writel(pbias_lite
, &t2_base
->pbias_lite
);
107 #if defined(CONFIG_TWL4030_POWER)
108 twl4030_power_mmc_init();
109 mdelay(100); /* ramp-up delay from Linux code */
111 #if defined(CONFIG_OMAP34XX)
112 writel(pbias_lite
| PBIASLITEPWRDNZ1
|
113 PBIASSPEEDCTRL0
| PBIASLITEPWRDNZ0
,
114 &t2_base
->pbias_lite
);
116 writel(readl(&t2_base
->devconf0
) | MMCSDIO1ADPCLKISEL
,
119 writel(readl(&t2_base
->devconf1
) | MMCSDIO2ADPCLKISEL
,
122 /* Change from default of 52MHz to 26MHz if necessary */
123 if (!(mmc
->host_caps
& MMC_MODE_HS_52MHz
))
124 writel(readl(&t2_base
->ctl_prog_io1
) & ~CTLPROGIO1SPEEDCTRL
,
125 &t2_base
->ctl_prog_io1
);
127 writel(readl(&prcm_base
->fclken1_core
) |
128 EN_MMC1
| EN_MMC2
| EN_MMC3
,
129 &prcm_base
->fclken1_core
);
131 writel(readl(&prcm_base
->iclken1_core
) |
132 EN_MMC1
| EN_MMC2
| EN_MMC3
,
133 &prcm_base
->iclken1_core
);
136 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
137 /* PBIAS config needed for MMC1 only */
138 if (mmc
->block_dev
.dev
== 0)
139 omap4_vmmc_pbias_config(mmc
);
141 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
142 if (mmc
->block_dev
.dev
== 0)
143 omap5_pbias_config(mmc
);
149 void mmc_init_stream(struct hsmmc
*mmc_base
)
153 writel(readl(&mmc_base
->con
) | INIT_INITSTREAM
, &mmc_base
->con
);
155 writel(MMC_CMD0
, &mmc_base
->cmd
);
156 start
= get_timer(0);
157 while (!(readl(&mmc_base
->stat
) & CC_MASK
)) {
158 if (get_timer(0) - start
> MAX_RETRY_MS
) {
159 printf("%s: timedout waiting for cc!\n", __func__
);
163 writel(CC_MASK
, &mmc_base
->stat
)
165 writel(MMC_CMD0
, &mmc_base
->cmd
)
167 start
= get_timer(0);
168 while (!(readl(&mmc_base
->stat
) & CC_MASK
)) {
169 if (get_timer(0) - start
> MAX_RETRY_MS
) {
170 printf("%s: timedout waiting for cc2!\n", __func__
);
174 writel(readl(&mmc_base
->con
) & ~INIT_INITSTREAM
, &mmc_base
->con
);
178 static int mmc_init_setup(struct mmc
*mmc
)
180 struct hsmmc
*mmc_base
= (struct hsmmc
*)mmc
->priv
;
181 unsigned int reg_val
;
187 writel(readl(&mmc_base
->sysconfig
) | MMC_SOFTRESET
,
188 &mmc_base
->sysconfig
);
189 start
= get_timer(0);
190 while ((readl(&mmc_base
->sysstatus
) & RESETDONE
) == 0) {
191 if (get_timer(0) - start
> MAX_RETRY_MS
) {
192 printf("%s: timedout waiting for cc2!\n", __func__
);
196 writel(readl(&mmc_base
->sysctl
) | SOFTRESETALL
, &mmc_base
->sysctl
);
197 start
= get_timer(0);
198 while ((readl(&mmc_base
->sysctl
) & SOFTRESETALL
) != 0x0) {
199 if (get_timer(0) - start
> MAX_RETRY_MS
) {
200 printf("%s: timedout waiting for softresetall!\n",
205 writel(DTW_1_BITMODE
| SDBP_PWROFF
| SDVS_3V0
, &mmc_base
->hctl
);
206 writel(readl(&mmc_base
->capa
) | VS30_3V0SUP
| VS18_1V8SUP
,
209 reg_val
= readl(&mmc_base
->con
) & RESERVED_MASK
;
211 writel(CTPL_MMC_SD
| reg_val
| WPP_ACTIVEHIGH
| CDP_ACTIVEHIGH
|
212 MIT_CTO
| DW8_1_4BITMODE
| MODE_FUNC
| STR_BLOCK
|
213 HR_NOHOSTRESP
| INIT_NOINIT
| NOOPENDRAIN
, &mmc_base
->con
);
216 mmc_reg_out(&mmc_base
->sysctl
, (ICE_MASK
| DTO_MASK
| CEN_MASK
),
217 (ICE_STOP
| DTO_15THDTO
| CEN_DISABLE
));
218 mmc_reg_out(&mmc_base
->sysctl
, ICE_MASK
| CLKD_MASK
,
219 (dsor
<< CLKD_OFFSET
) | ICE_OSCILLATE
);
220 start
= get_timer(0);
221 while ((readl(&mmc_base
->sysctl
) & ICS_MASK
) == ICS_NOTREADY
) {
222 if (get_timer(0) - start
> MAX_RETRY_MS
) {
223 printf("%s: timedout waiting for ics!\n", __func__
);
227 writel(readl(&mmc_base
->sysctl
) | CEN_ENABLE
, &mmc_base
->sysctl
);
229 writel(readl(&mmc_base
->hctl
) | SDBP_PWRON
, &mmc_base
->hctl
);
231 writel(IE_BADA
| IE_CERR
| IE_DEB
| IE_DCRC
| IE_DTO
| IE_CIE
|
232 IE_CEB
| IE_CCRC
| IE_CTO
| IE_BRR
| IE_BWR
| IE_TC
| IE_CC
,
235 mmc_init_stream(mmc_base
);
241 * MMC controller internal finite state machine reset
243 * Used to reset command or data internal state machines, using respectively
244 * SRC or SRD bit of SYSCTL register
246 static void mmc_reset_controller_fsm(struct hsmmc
*mmc_base
, u32 bit
)
250 mmc_reg_out(&mmc_base
->sysctl
, bit
, bit
);
252 start
= get_timer(0);
253 while ((readl(&mmc_base
->sysctl
) & bit
) != 0) {
254 if (get_timer(0) - start
> MAX_RETRY_MS
) {
255 printf("%s: timedout waiting for sysctl %x to clear\n",
262 static int mmc_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*cmd
,
263 struct mmc_data
*data
)
265 struct hsmmc
*mmc_base
= (struct hsmmc
*)mmc
->priv
;
266 unsigned int flags
, mmc_stat
;
269 start
= get_timer(0);
270 while ((readl(&mmc_base
->pstate
) & (DATI_MASK
| CMDI_MASK
)) != 0) {
271 if (get_timer(0) - start
> MAX_RETRY_MS
) {
272 printf("%s: timedout waiting on cmd inhibit to clear\n",
277 writel(0xFFFFFFFF, &mmc_base
->stat
);
278 start
= get_timer(0);
279 while (readl(&mmc_base
->stat
)) {
280 if (get_timer(0) - start
> MAX_RETRY_MS
) {
281 printf("%s: timedout waiting for STAT (%x) to clear\n",
282 __func__
, readl(&mmc_base
->stat
));
288 * CMDIDX[13:8] : Command index
289 * DATAPRNT[5] : Data Present Select
290 * ENCMDIDX[4] : Command Index Check Enable
291 * ENCMDCRC[3] : Command CRC Check Enable
296 * 11 = Length 48 Check busy after response
298 /* Delay added before checking the status of frq change
299 * retry not supported by mmc.c(core file)
301 if (cmd
->cmdidx
== SD_CMD_APP_SEND_SCR
)
302 udelay(50000); /* wait 50 ms */
304 if (!(cmd
->resp_type
& MMC_RSP_PRESENT
))
306 else if (cmd
->resp_type
& MMC_RSP_136
)
307 flags
= RSP_TYPE_LGHT136
| CICE_NOCHECK
;
308 else if (cmd
->resp_type
& MMC_RSP_BUSY
)
309 flags
= RSP_TYPE_LGHT48B
;
311 flags
= RSP_TYPE_LGHT48
;
313 /* enable default flags */
314 flags
= flags
| (CMD_TYPE_NORMAL
| CICE_NOCHECK
| CCCE_NOCHECK
|
315 MSBS_SGLEBLK
| ACEN_DISABLE
| BCE_DISABLE
| DE_DISABLE
);
317 if (cmd
->resp_type
& MMC_RSP_CRC
)
319 if (cmd
->resp_type
& MMC_RSP_OPCODE
)
323 if ((cmd
->cmdidx
== MMC_CMD_READ_MULTIPLE_BLOCK
) ||
324 (cmd
->cmdidx
== MMC_CMD_WRITE_MULTIPLE_BLOCK
)) {
325 flags
|= (MSBS_MULTIBLK
| BCE_ENABLE
);
326 data
->blocksize
= 512;
327 writel(data
->blocksize
| (data
->blocks
<< 16),
330 writel(data
->blocksize
| NBLK_STPCNT
, &mmc_base
->blk
);
332 if (data
->flags
& MMC_DATA_READ
)
333 flags
|= (DP_DATA
| DDIR_READ
);
335 flags
|= (DP_DATA
| DDIR_WRITE
);
338 writel(cmd
->cmdarg
, &mmc_base
->arg
);
339 writel((cmd
->cmdidx
<< 24) | flags
, &mmc_base
->cmd
);
341 start
= get_timer(0);
343 mmc_stat
= readl(&mmc_base
->stat
);
344 if (get_timer(0) - start
> MAX_RETRY_MS
) {
345 printf("%s : timeout: No status update\n", __func__
);
350 if ((mmc_stat
& IE_CTO
) != 0) {
351 mmc_reset_controller_fsm(mmc_base
, SYSCTL_SRC
);
353 } else if ((mmc_stat
& ERRI_MASK
) != 0)
356 if (mmc_stat
& CC_MASK
) {
357 writel(CC_MASK
, &mmc_base
->stat
);
358 if (cmd
->resp_type
& MMC_RSP_PRESENT
) {
359 if (cmd
->resp_type
& MMC_RSP_136
) {
360 /* response type 2 */
361 cmd
->response
[3] = readl(&mmc_base
->rsp10
);
362 cmd
->response
[2] = readl(&mmc_base
->rsp32
);
363 cmd
->response
[1] = readl(&mmc_base
->rsp54
);
364 cmd
->response
[0] = readl(&mmc_base
->rsp76
);
366 /* response types 1, 1b, 3, 4, 5, 6 */
367 cmd
->response
[0] = readl(&mmc_base
->rsp10
);
371 if (data
&& (data
->flags
& MMC_DATA_READ
)) {
372 mmc_read_data(mmc_base
, data
->dest
,
373 data
->blocksize
* data
->blocks
);
374 } else if (data
&& (data
->flags
& MMC_DATA_WRITE
)) {
375 mmc_write_data(mmc_base
, data
->src
,
376 data
->blocksize
* data
->blocks
);
381 static int mmc_read_data(struct hsmmc
*mmc_base
, char *buf
, unsigned int size
)
383 unsigned int *output_buf
= (unsigned int *)buf
;
384 unsigned int mmc_stat
;
390 count
= (size
> MMCSD_SECTOR_SIZE
) ? MMCSD_SECTOR_SIZE
: size
;
394 ulong start
= get_timer(0);
396 mmc_stat
= readl(&mmc_base
->stat
);
397 if (get_timer(0) - start
> MAX_RETRY_MS
) {
398 printf("%s: timedout waiting for status!\n",
402 } while (mmc_stat
== 0);
404 if ((mmc_stat
& (IE_DTO
| IE_DCRC
| IE_DEB
)) != 0)
405 mmc_reset_controller_fsm(mmc_base
, SYSCTL_SRD
);
407 if ((mmc_stat
& ERRI_MASK
) != 0)
410 if (mmc_stat
& BRR_MASK
) {
413 writel(readl(&mmc_base
->stat
) | BRR_MASK
,
415 for (k
= 0; k
< count
; k
++) {
416 *output_buf
= readl(&mmc_base
->data
);
422 if (mmc_stat
& BWR_MASK
)
423 writel(readl(&mmc_base
->stat
) | BWR_MASK
,
426 if (mmc_stat
& TC_MASK
) {
427 writel(readl(&mmc_base
->stat
) | TC_MASK
,
435 static int mmc_write_data(struct hsmmc
*mmc_base
, const char *buf
,
438 unsigned int *input_buf
= (unsigned int *)buf
;
439 unsigned int mmc_stat
;
445 count
= (size
> MMCSD_SECTOR_SIZE
) ? MMCSD_SECTOR_SIZE
: size
;
449 ulong start
= get_timer(0);
451 mmc_stat
= readl(&mmc_base
->stat
);
452 if (get_timer(0) - start
> MAX_RETRY_MS
) {
453 printf("%s: timedout waiting for status!\n",
457 } while (mmc_stat
== 0);
459 if ((mmc_stat
& (IE_DTO
| IE_DCRC
| IE_DEB
)) != 0)
460 mmc_reset_controller_fsm(mmc_base
, SYSCTL_SRD
);
462 if ((mmc_stat
& ERRI_MASK
) != 0)
465 if (mmc_stat
& BWR_MASK
) {
468 writel(readl(&mmc_base
->stat
) | BWR_MASK
,
470 for (k
= 0; k
< count
; k
++) {
471 writel(*input_buf
, &mmc_base
->data
);
477 if (mmc_stat
& BRR_MASK
)
478 writel(readl(&mmc_base
->stat
) | BRR_MASK
,
481 if (mmc_stat
& TC_MASK
) {
482 writel(readl(&mmc_base
->stat
) | TC_MASK
,
490 static void mmc_set_ios(struct mmc
*mmc
)
492 struct hsmmc
*mmc_base
= (struct hsmmc
*)mmc
->priv
;
493 unsigned int dsor
= 0;
496 /* configue bus width */
497 switch (mmc
->bus_width
) {
499 writel(readl(&mmc_base
->con
) | DTW_8_BITMODE
,
504 writel(readl(&mmc_base
->con
) & ~DTW_8_BITMODE
,
506 writel(readl(&mmc_base
->hctl
) | DTW_4_BITMODE
,
512 writel(readl(&mmc_base
->con
) & ~DTW_8_BITMODE
,
514 writel(readl(&mmc_base
->hctl
) & ~DTW_4_BITMODE
,
519 /* configure clock with 96Mhz system clock.
521 if (mmc
->clock
!= 0) {
522 dsor
= (MMC_CLOCK_REFERENCE
* 1000000 / mmc
->clock
);
523 if ((MMC_CLOCK_REFERENCE
* 1000000) / dsor
> mmc
->clock
)
527 mmc_reg_out(&mmc_base
->sysctl
, (ICE_MASK
| DTO_MASK
| CEN_MASK
),
528 (ICE_STOP
| DTO_15THDTO
| CEN_DISABLE
));
530 mmc_reg_out(&mmc_base
->sysctl
, ICE_MASK
| CLKD_MASK
,
531 (dsor
<< CLKD_OFFSET
) | ICE_OSCILLATE
);
533 start
= get_timer(0);
534 while ((readl(&mmc_base
->sysctl
) & ICS_MASK
) == ICS_NOTREADY
) {
535 if (get_timer(0) - start
> MAX_RETRY_MS
) {
536 printf("%s: timedout waiting for ics!\n", __func__
);
540 writel(readl(&mmc_base
->sysctl
) | CEN_ENABLE
, &mmc_base
->sysctl
);
543 int omap_mmc_init(int dev_index
, uint host_caps_mask
, uint f_max
)
547 mmc
= &hsmmc_dev
[dev_index
];
549 sprintf(mmc
->name
, "OMAP SD/MMC");
550 mmc
->send_cmd
= mmc_send_cmd
;
551 mmc
->set_ios
= mmc_set_ios
;
552 mmc
->init
= mmc_init_setup
;
557 mmc
->priv
= (struct hsmmc
*)OMAP_HSMMC1_BASE
;
559 #ifdef OMAP_HSMMC2_BASE
561 mmc
->priv
= (struct hsmmc
*)OMAP_HSMMC2_BASE
;
564 #ifdef OMAP_HSMMC3_BASE
566 mmc
->priv
= (struct hsmmc
*)OMAP_HSMMC3_BASE
;
570 mmc
->priv
= (struct hsmmc
*)OMAP_HSMMC1_BASE
;
573 mmc
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
;
574 mmc
->host_caps
= (MMC_MODE_4BIT
| MMC_MODE_HS_52MHz
| MMC_MODE_HS
|
575 MMC_MODE_HC
) & ~host_caps_mask
;
582 if (mmc
->host_caps
& MMC_MODE_HS
) {
583 if (mmc
->host_caps
& MMC_MODE_HS_52MHz
)
584 mmc
->f_max
= 52000000;
586 mmc
->f_max
= 26000000;
588 mmc
->f_max
= 20000000;
593 #if defined(CONFIG_OMAP34XX)
595 * Silicon revs 2.1 and older do not support multiblock transfers.
597 if ((get_cpu_family() == CPU_OMAP34XX
) && (get_cpu_rev() <= CPU_3XX_ES21
))