2 * Copyright (c) 2013 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <dt-structs.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/periph.h>
19 #include <linux/err.h>
21 DECLARE_GLOBAL_DATA_PTR
;
23 struct rockchip_mmc_plat
{
24 #if CONFIG_IS_ENABLED(OF_PLATDATA)
25 struct dtd_rockchip_rk3288_dw_mshc dtplat
;
27 struct mmc_config cfg
;
31 struct rockchip_dwmmc_priv
{
33 struct dwmci_host host
;
39 static uint
rockchip_dwmmc_get_mmc_clk(struct dwmci_host
*host
, uint freq
)
41 struct udevice
*dev
= host
->priv
;
42 struct rockchip_dwmmc_priv
*priv
= dev_get_priv(dev
);
45 ret
= clk_set_rate(&priv
->clk
, freq
);
47 printf("%s: err=%d\n", __func__
, ret
);
54 static int rockchip_dwmmc_ofdata_to_platdata(struct udevice
*dev
)
56 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
57 struct rockchip_dwmmc_priv
*priv
= dev_get_priv(dev
);
58 struct dwmci_host
*host
= &priv
->host
;
60 host
->name
= dev
->name
;
61 host
->ioaddr
= (void *)devfdt_get_addr(dev
);
62 host
->buswidth
= dev_read_u32_default(dev
, "bus-width", 4);
63 host
->get_mmc_clk
= rockchip_dwmmc_get_mmc_clk
;
66 /* use non-removeable as sdcard and emmc as judgement */
67 if (dev_read_bool(dev
, "non-removable"))
72 priv
->fifo_depth
= dev_read_u32_default(dev
, "fifo-depth", 0);
74 if (priv
->fifo_depth
< 0)
76 priv
->fifo_mode
= dev_read_bool(dev
, "fifo-mode");
79 * 'clock-freq-min-max' is deprecated
80 * (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b)
82 if (dev_read_u32_array(dev
, "clock-freq-min-max", priv
->minmax
, 2)) {
83 int val
= dev_read_u32_default(dev
, "max-frequency", -EINVAL
);
88 priv
->minmax
[0] = 400000; /* 400 kHz */
89 priv
->minmax
[1] = val
;
91 debug("%s: 'clock-freq-min-max' property was deprecated.\n",
98 static int rockchip_dwmmc_probe(struct udevice
*dev
)
100 struct rockchip_mmc_plat
*plat
= dev_get_platdata(dev
);
101 struct mmc_uclass_priv
*upriv
= dev_get_uclass_priv(dev
);
102 struct rockchip_dwmmc_priv
*priv
= dev_get_priv(dev
);
103 struct dwmci_host
*host
= &priv
->host
;
104 struct udevice
*pwr_dev __maybe_unused
;
107 #if CONFIG_IS_ENABLED(OF_PLATDATA)
108 struct dtd_rockchip_rk3288_dw_mshc
*dtplat
= &plat
->dtplat
;
110 host
->name
= dev
->name
;
111 host
->ioaddr
= map_sysmem(dtplat
->reg
[0], dtplat
->reg
[1]);
112 host
->buswidth
= dtplat
->bus_width
;
113 host
->get_mmc_clk
= rockchip_dwmmc_get_mmc_clk
;
116 priv
->fifo_depth
= dtplat
->fifo_depth
;
118 priv
->minmax
[0] = 400000; /* 400 kHz */
119 priv
->minmax
[1] = dtplat
->max_frequency
;
121 ret
= clk_get_by_index_platdata(dev
, 0, dtplat
->clocks
, &priv
->clk
);
125 ret
= clk_get_by_name(dev
, "ciu", &priv
->clk
);
129 host
->fifoth_val
= MSIZE(0x2) |
130 RX_WMARK(priv
->fifo_depth
/ 2 - 1) |
131 TX_WMARK(priv
->fifo_depth
/ 2);
133 host
->fifo_mode
= priv
->fifo_mode
;
136 /* Enable power if needed */
137 ret
= uclass_get_device_by_phandle(UCLASS_PWRSEQ
, dev
, "mmc-pwrseq",
140 ret
= pwrseq_set_power(pwr_dev
, true);
145 dwmci_setup_cfg(&plat
->cfg
, host
, priv
->minmax
[1], priv
->minmax
[0]);
146 host
->mmc
= &plat
->mmc
;
147 host
->mmc
->priv
= &priv
->host
;
148 host
->mmc
->dev
= dev
;
149 upriv
->mmc
= host
->mmc
;
151 return dwmci_probe(dev
);
154 static int rockchip_dwmmc_bind(struct udevice
*dev
)
156 struct rockchip_mmc_plat
*plat
= dev_get_platdata(dev
);
158 return dwmci_bind(dev
, &plat
->mmc
, &plat
->cfg
);
161 static const struct udevice_id rockchip_dwmmc_ids
[] = {
162 { .compatible
= "rockchip,rk3288-dw-mshc" },
166 U_BOOT_DRIVER(rockchip_dwmmc_drv
) = {
167 .name
= "rockchip_rk3288_dw_mshc",
169 .of_match
= rockchip_dwmmc_ids
,
170 .ofdata_to_platdata
= rockchip_dwmmc_ofdata_to_platdata
,
171 .ops
= &dm_dwmci_ops
,
172 .bind
= rockchip_dwmmc_bind
,
173 .probe
= rockchip_dwmmc_probe
,
174 .priv_auto_alloc_size
= sizeof(struct rockchip_dwmmc_priv
),
175 .platdata_auto_alloc_size
= sizeof(struct rockchip_mmc_plat
),
179 static int rockchip_dwmmc_pwrseq_set_power(struct udevice
*dev
, bool enable
)
181 struct gpio_desc reset
;
184 ret
= gpio_request_by_name(dev
, "reset-gpios", 0, &reset
, GPIOD_IS_OUT
);
187 dm_gpio_set_value(&reset
, 1);
189 dm_gpio_set_value(&reset
, 0);
195 static const struct pwrseq_ops rockchip_dwmmc_pwrseq_ops
= {
196 .set_power
= rockchip_dwmmc_pwrseq_set_power
,
199 static const struct udevice_id rockchip_dwmmc_pwrseq_ids
[] = {
200 { .compatible
= "mmc-pwrseq-emmc" },
204 U_BOOT_DRIVER(rockchip_dwmmc_pwrseq_drv
) = {
205 .name
= "mmc_pwrseq_emmc",
207 .of_match
= rockchip_dwmmc_pwrseq_ids
,
208 .ops
= &rockchip_dwmmc_pwrseq_ops
,